1 /* $NetBSD: intel_dpio_phy.h,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 /* 5 * Copyright © 2019 Intel Corporation 6 */ 7 8 #ifndef __INTEL_DPIO_PHY_H__ 9 #define __INTEL_DPIO_PHY_H__ 10 11 #include <linux/types.h> 12 13 enum dpio_channel; 14 enum dpio_phy; 15 enum port; 16 struct drm_i915_private; 17 struct intel_crtc_state; 18 struct intel_encoder; 19 20 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, 21 enum dpio_phy *phy, enum dpio_channel *ch); 22 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, 23 enum port port, u32 margin, u32 scale, 24 u32 enable, u32 deemphasis); 25 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); 26 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); 27 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 28 enum dpio_phy phy); 29 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 30 enum dpio_phy phy); 31 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count); 32 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, 33 u8 lane_lat_optim_mask); 34 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); 35 36 void chv_set_phy_signal_level(struct intel_encoder *encoder, 37 u32 deemph_reg_value, u32 margin_reg_value, 38 bool uniq_trans_scale); 39 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 40 const struct intel_crtc_state *crtc_state, 41 bool reset); 42 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 43 const struct intel_crtc_state *crtc_state); 44 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 45 const struct intel_crtc_state *crtc_state); 46 void chv_phy_release_cl2_override(struct intel_encoder *encoder); 47 void chv_phy_post_pll_disable(struct intel_encoder *encoder, 48 const struct intel_crtc_state *old_crtc_state); 49 50 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 51 u32 demph_reg_value, u32 preemph_reg_value, 52 u32 uniqtranscale_reg_value, u32 tx3_demph); 53 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 54 const struct intel_crtc_state *crtc_state); 55 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 56 const struct intel_crtc_state *crtc_state); 57 void vlv_phy_reset_lanes(struct intel_encoder *encoder, 58 const struct intel_crtc_state *old_crtc_state); 59 60 #endif /* __INTEL_DPIO_PHY_H__ */ 61