1 /* $NetBSD: intel_dp.h,v 1.4 2023/08/01 07:04:16 mrg Exp $ */
2
3 /* SPDX-License-Identifier: MIT */
4 /*
5 * Copyright © 2019 Intel Corporation
6 */
7
8 #ifndef __INTEL_DP_H__
9 #define __INTEL_DP_H__
10
11 #include <linux/types.h>
12
13 #include <drm/i915_drm.h>
14 #include <drm/drm_dp_helper.h>
15
16 #include "i915_reg.h"
17
18 #include <sys/file.h>
19 #define pipe pipe_drmhack /* see intel_display.h */
20
21 enum pipe;
22 enum port;
23 struct drm_connector_state;
24 struct drm_encoder;
25 struct drm_i915_private;
26 struct drm_modeset_acquire_ctx;
27 struct intel_connector;
28 struct intel_crtc_state;
29 struct intel_digital_port;
30 struct intel_dp;
31 struct intel_encoder;
32
33 struct link_config_limits {
34 int min_clock, max_clock;
35 int min_lane_count, max_lane_count;
36 int min_bpp, max_bpp;
37 };
38
39 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
40 struct intel_crtc_state *pipe_config,
41 struct link_config_limits *limits);
42 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
43 const struct drm_connector_state *conn_state);
44 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
45 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
46 i915_reg_t dp_reg, enum port port,
47 enum pipe *pipe);
48 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
49 enum port port);
50 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
51 struct intel_connector *intel_connector);
52 void intel_dp_set_link_params(struct intel_dp *intel_dp,
53 int link_rate, u8 lane_count,
54 bool link_mst);
55 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
56 int link_rate, u8 lane_count);
57 int intel_dp_retrain_link(struct intel_encoder *encoder,
58 struct drm_modeset_acquire_ctx *ctx);
59 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
60 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
61 const struct intel_crtc_state *crtc_state,
62 bool enable);
63 void intel_dp_encoder_reset(struct drm_encoder *encoder);
64 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
65 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
66 int intel_dp_compute_config(struct intel_encoder *encoder,
67 struct intel_crtc_state *pipe_config,
68 struct drm_connector_state *conn_state);
69 bool intel_dp_is_edp(struct intel_dp *intel_dp);
70 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
71 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
72 bool long_hpd);
73 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
74 const struct drm_connector_state *conn_state);
75 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
76 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
77 void intel_edp_panel_on(struct intel_dp *intel_dp);
78 void intel_edp_panel_off(struct intel_dp *intel_dp);
79 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
80 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
81 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
82 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
83 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
84 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
85 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
86
87 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
88 const struct intel_crtc_state *crtc_state);
89 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
90 const struct intel_crtc_state *crtc_state);
91 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
92 unsigned int frontbuffer_bits);
93 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
94 unsigned int frontbuffer_bits);
95
96 void
97 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
98 u8 dp_train_pat);
99 void
100 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
101 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
102 u8
103 intel_dp_voltage_max(struct intel_dp *intel_dp);
104 u8
105 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
106 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
107 u8 *link_bw, u8 *rate_select);
108 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
109 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
110 bool
111 intel_dp_get_link_status(struct intel_dp *intel_dp, u8
112 link_status[DP_LINK_STATUS_SIZE]);
113
114 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
115 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
116 int intel_dp_link_required(int pixel_clock, int bpp);
117 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
118 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
119 const struct drm_connector_state *conn_state);
120 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
121 const struct intel_crtc_state *crtc_state,
122 const struct drm_connector_state *conn_state);
123 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
124 const struct intel_crtc_state *crtc_state,
125 const struct drm_connector_state *conn_state);
126 bool intel_digital_port_connected(struct intel_encoder *encoder);
127
intel_dp_unused_lane_mask(int lane_count)128 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
129 {
130 return ~((1 << lane_count) - 1) & 0xf;
131 }
132
133 u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
134
135 #endif /* __INTEL_DP_H__ */
136