1 /* $NetBSD: intel_ddi.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $ */
2
3 /*
4 * Copyright © 2012 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eugeni Dodonov <eugeni.dodonov@intel.com>
27 *
28 */
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: intel_ddi.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $");
32
33 #include <drm/drm_scdc_helper.h>
34
35 #include "i915_drv.h"
36 #include "intel_audio.h"
37 #include "intel_combo_phy.h"
38 #include "intel_connector.h"
39 #include "intel_ddi.h"
40 #include "intel_display_types.h"
41 #include "intel_dp.h"
42 #include "intel_dp_mst.h"
43 #include "intel_dp_link_training.h"
44 #include "intel_dpio_phy.h"
45 #include "intel_dsi.h"
46 #include "intel_fifo_underrun.h"
47 #include "intel_gmbus.h"
48 #include "intel_hdcp.h"
49 #include "intel_hdmi.h"
50 #include "intel_hotplug.h"
51 #include "intel_lspcon.h"
52 #include "intel_panel.h"
53 #include "intel_psr.h"
54 #include "intel_sprite.h"
55 #include "intel_tc.h"
56 #include "intel_vdsc.h"
57
58 struct ddi_buf_trans {
59 u32 trans1; /* balance leg enable, de-emph level */
60 u32 trans2; /* vref sel, vswing */
61 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
62 };
63
64 static const u8 index_to_dp_signal_levels[] = {
65 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
66 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
67 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
68 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
69 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
70 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
71 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
72 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
73 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
74 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
75 };
76
77 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
78 * them for both DP and FDI transports, allowing those ports to
79 * automatically adapt to HDMI connections as well
80 */
81 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
82 { 0x00FFFFFF, 0x0006000E, 0x0 },
83 { 0x00D75FFF, 0x0005000A, 0x0 },
84 { 0x00C30FFF, 0x00040006, 0x0 },
85 { 0x80AAAFFF, 0x000B0000, 0x0 },
86 { 0x00FFFFFF, 0x0005000A, 0x0 },
87 { 0x00D75FFF, 0x000C0004, 0x0 },
88 { 0x80C30FFF, 0x000B0000, 0x0 },
89 { 0x00FFFFFF, 0x00040006, 0x0 },
90 { 0x80D75FFF, 0x000B0000, 0x0 },
91 };
92
93 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000F000A, 0x0 },
96 { 0x00C30FFF, 0x00060006, 0x0 },
97 { 0x00AAAFFF, 0x001E0000, 0x0 },
98 { 0x00FFFFFF, 0x000F000A, 0x0 },
99 { 0x00D75FFF, 0x00160004, 0x0 },
100 { 0x00C30FFF, 0x001E0000, 0x0 },
101 { 0x00FFFFFF, 0x00060006, 0x0 },
102 { 0x00D75FFF, 0x001E0000, 0x0 },
103 };
104
105 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
106 /* Idx NT mV d T mV d db */
107 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
108 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
109 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
110 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
111 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
112 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
113 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
114 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
115 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
116 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
117 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
118 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
119 };
120
121 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
122 { 0x00FFFFFF, 0x00000012, 0x0 },
123 { 0x00EBAFFF, 0x00020011, 0x0 },
124 { 0x00C71FFF, 0x0006000F, 0x0 },
125 { 0x00AAAFFF, 0x000E000A, 0x0 },
126 { 0x00FFFFFF, 0x00020011, 0x0 },
127 { 0x00DB6FFF, 0x0005000F, 0x0 },
128 { 0x00BEEFFF, 0x000A000C, 0x0 },
129 { 0x00FFFFFF, 0x0005000F, 0x0 },
130 { 0x00DB6FFF, 0x000A000C, 0x0 },
131 };
132
133 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
134 { 0x00FFFFFF, 0x0007000E, 0x0 },
135 { 0x00D75FFF, 0x000E000A, 0x0 },
136 { 0x00BEFFFF, 0x00140006, 0x0 },
137 { 0x80B2CFFF, 0x001B0002, 0x0 },
138 { 0x00FFFFFF, 0x000E000A, 0x0 },
139 { 0x00DB6FFF, 0x00160005, 0x0 },
140 { 0x80C71FFF, 0x001A0002, 0x0 },
141 { 0x00F7DFFF, 0x00180004, 0x0 },
142 { 0x80D75FFF, 0x001B0002, 0x0 },
143 };
144
145 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
146 { 0x00FFFFFF, 0x0001000E, 0x0 },
147 { 0x00D75FFF, 0x0004000A, 0x0 },
148 { 0x00C30FFF, 0x00070006, 0x0 },
149 { 0x00AAAFFF, 0x000C0000, 0x0 },
150 { 0x00FFFFFF, 0x0004000A, 0x0 },
151 { 0x00D75FFF, 0x00090004, 0x0 },
152 { 0x00C30FFF, 0x000C0000, 0x0 },
153 { 0x00FFFFFF, 0x00070006, 0x0 },
154 { 0x00D75FFF, 0x000C0000, 0x0 },
155 };
156
157 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
158 /* Idx NT mV d T mV df db */
159 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
160 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
161 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
162 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
163 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
164 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
165 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
166 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
167 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
168 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
169 };
170
171 /* Skylake H and S */
172 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
173 { 0x00002016, 0x000000A0, 0x0 },
174 { 0x00005012, 0x0000009B, 0x0 },
175 { 0x00007011, 0x00000088, 0x0 },
176 { 0x80009010, 0x000000C0, 0x1 },
177 { 0x00002016, 0x0000009B, 0x0 },
178 { 0x00005012, 0x00000088, 0x0 },
179 { 0x80007011, 0x000000C0, 0x1 },
180 { 0x00002016, 0x000000DF, 0x0 },
181 { 0x80005012, 0x000000C0, 0x1 },
182 };
183
184 /* Skylake U */
185 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
186 { 0x0000201B, 0x000000A2, 0x0 },
187 { 0x00005012, 0x00000088, 0x0 },
188 { 0x80007011, 0x000000CD, 0x1 },
189 { 0x80009010, 0x000000C0, 0x1 },
190 { 0x0000201B, 0x0000009D, 0x0 },
191 { 0x80005012, 0x000000C0, 0x1 },
192 { 0x80007011, 0x000000C0, 0x1 },
193 { 0x00002016, 0x00000088, 0x0 },
194 { 0x80005012, 0x000000C0, 0x1 },
195 };
196
197 /* Skylake Y */
198 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
199 { 0x00000018, 0x000000A2, 0x0 },
200 { 0x00005012, 0x00000088, 0x0 },
201 { 0x80007011, 0x000000CD, 0x3 },
202 { 0x80009010, 0x000000C0, 0x3 },
203 { 0x00000018, 0x0000009D, 0x0 },
204 { 0x80005012, 0x000000C0, 0x3 },
205 { 0x80007011, 0x000000C0, 0x3 },
206 { 0x00000018, 0x00000088, 0x0 },
207 { 0x80005012, 0x000000C0, 0x3 },
208 };
209
210 /* Kabylake H and S */
211 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
212 { 0x00002016, 0x000000A0, 0x0 },
213 { 0x00005012, 0x0000009B, 0x0 },
214 { 0x00007011, 0x00000088, 0x0 },
215 { 0x80009010, 0x000000C0, 0x1 },
216 { 0x00002016, 0x0000009B, 0x0 },
217 { 0x00005012, 0x00000088, 0x0 },
218 { 0x80007011, 0x000000C0, 0x1 },
219 { 0x00002016, 0x00000097, 0x0 },
220 { 0x80005012, 0x000000C0, 0x1 },
221 };
222
223 /* Kabylake U */
224 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
225 { 0x0000201B, 0x000000A1, 0x0 },
226 { 0x00005012, 0x00000088, 0x0 },
227 { 0x80007011, 0x000000CD, 0x3 },
228 { 0x80009010, 0x000000C0, 0x3 },
229 { 0x0000201B, 0x0000009D, 0x0 },
230 { 0x80005012, 0x000000C0, 0x3 },
231 { 0x80007011, 0x000000C0, 0x3 },
232 { 0x00002016, 0x0000004F, 0x0 },
233 { 0x80005012, 0x000000C0, 0x3 },
234 };
235
236 /* Kabylake Y */
237 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
238 { 0x00001017, 0x000000A1, 0x0 },
239 { 0x00005012, 0x00000088, 0x0 },
240 { 0x80007011, 0x000000CD, 0x3 },
241 { 0x8000800F, 0x000000C0, 0x3 },
242 { 0x00001017, 0x0000009D, 0x0 },
243 { 0x80005012, 0x000000C0, 0x3 },
244 { 0x80007011, 0x000000C0, 0x3 },
245 { 0x00001017, 0x0000004C, 0x0 },
246 { 0x80005012, 0x000000C0, 0x3 },
247 };
248
249 /*
250 * Skylake/Kabylake H and S
251 * eDP 1.4 low vswing translation parameters
252 */
253 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
254 { 0x00000018, 0x000000A8, 0x0 },
255 { 0x00004013, 0x000000A9, 0x0 },
256 { 0x00007011, 0x000000A2, 0x0 },
257 { 0x00009010, 0x0000009C, 0x0 },
258 { 0x00000018, 0x000000A9, 0x0 },
259 { 0x00006013, 0x000000A2, 0x0 },
260 { 0x00007011, 0x000000A6, 0x0 },
261 { 0x00000018, 0x000000AB, 0x0 },
262 { 0x00007013, 0x0000009F, 0x0 },
263 { 0x00000018, 0x000000DF, 0x0 },
264 };
265
266 /*
267 * Skylake/Kabylake U
268 * eDP 1.4 low vswing translation parameters
269 */
270 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
271 { 0x00000018, 0x000000A8, 0x0 },
272 { 0x00004013, 0x000000A9, 0x0 },
273 { 0x00007011, 0x000000A2, 0x0 },
274 { 0x00009010, 0x0000009C, 0x0 },
275 { 0x00000018, 0x000000A9, 0x0 },
276 { 0x00006013, 0x000000A2, 0x0 },
277 { 0x00007011, 0x000000A6, 0x0 },
278 { 0x00002016, 0x000000AB, 0x0 },
279 { 0x00005013, 0x0000009F, 0x0 },
280 { 0x00000018, 0x000000DF, 0x0 },
281 };
282
283 /*
284 * Skylake/Kabylake Y
285 * eDP 1.4 low vswing translation parameters
286 */
287 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
288 { 0x00000018, 0x000000A8, 0x0 },
289 { 0x00004013, 0x000000AB, 0x0 },
290 { 0x00007011, 0x000000A4, 0x0 },
291 { 0x00009010, 0x000000DF, 0x0 },
292 { 0x00000018, 0x000000AA, 0x0 },
293 { 0x00006013, 0x000000A4, 0x0 },
294 { 0x00007011, 0x0000009D, 0x0 },
295 { 0x00000018, 0x000000A0, 0x0 },
296 { 0x00006012, 0x000000DF, 0x0 },
297 { 0x00000018, 0x0000008A, 0x0 },
298 };
299
300 /* Skylake/Kabylake U, H and S */
301 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
302 { 0x00000018, 0x000000AC, 0x0 },
303 { 0x00005012, 0x0000009D, 0x0 },
304 { 0x00007011, 0x00000088, 0x0 },
305 { 0x00000018, 0x000000A1, 0x0 },
306 { 0x00000018, 0x00000098, 0x0 },
307 { 0x00004013, 0x00000088, 0x0 },
308 { 0x80006012, 0x000000CD, 0x1 },
309 { 0x00000018, 0x000000DF, 0x0 },
310 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
311 { 0x80003015, 0x000000C0, 0x1 },
312 { 0x80000018, 0x000000C0, 0x1 },
313 };
314
315 /* Skylake/Kabylake Y */
316 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
317 { 0x00000018, 0x000000A1, 0x0 },
318 { 0x00005012, 0x000000DF, 0x0 },
319 { 0x80007011, 0x000000CB, 0x3 },
320 { 0x00000018, 0x000000A4, 0x0 },
321 { 0x00000018, 0x0000009D, 0x0 },
322 { 0x00004013, 0x00000080, 0x0 },
323 { 0x80006013, 0x000000C0, 0x3 },
324 { 0x00000018, 0x0000008A, 0x0 },
325 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
326 { 0x80003015, 0x000000C0, 0x3 },
327 { 0x80000018, 0x000000C0, 0x3 },
328 };
329
330 struct bxt_ddi_buf_trans {
331 u8 margin; /* swing value */
332 u8 scale; /* scale value */
333 u8 enable; /* scale enable */
334 u8 deemphasis;
335 };
336
337 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
338 /* Idx NT mV diff db */
339 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
340 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
341 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
342 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
343 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
344 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
345 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
346 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
347 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
348 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
349 };
350
351 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
352 /* Idx NT mV diff db */
353 { 26, 0, 0, 128, }, /* 0: 200 0 */
354 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
355 { 48, 0, 0, 96, }, /* 2: 200 4 */
356 { 54, 0, 0, 69, }, /* 3: 200 6 */
357 { 32, 0, 0, 128, }, /* 4: 250 0 */
358 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
359 { 54, 0, 0, 85, }, /* 6: 250 4 */
360 { 43, 0, 0, 128, }, /* 7: 300 0 */
361 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
362 { 48, 0, 0, 128, }, /* 9: 300 0 */
363 };
364
365 /* BSpec has 2 recommended values - entries 0 and 8.
366 * Using the entry with higher vswing.
367 */
368 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
369 /* Idx NT mV diff db */
370 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
371 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
372 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
373 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
374 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
375 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
376 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
377 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
378 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
379 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
380 };
381
382 struct cnl_ddi_buf_trans {
383 u8 dw2_swing_sel;
384 u8 dw7_n_scalar;
385 u8 dw4_cursor_coeff;
386 u8 dw4_post_cursor_2;
387 u8 dw4_post_cursor_1;
388 };
389
390 /* Voltage Swing Programming for VccIO 0.85V for DP */
391 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
392 /* NT mV Trans mV db */
393 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
394 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
395 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
396 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
397 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
398 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
399 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
400 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
401 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
402 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
403 };
404
405 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
406 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
407 /* NT mV Trans mV db */
408 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
409 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
410 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
411 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
412 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
413 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
414 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
415 };
416
417 /* Voltage Swing Programming for VccIO 0.85V for eDP */
418 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
419 /* NT mV Trans mV db */
420 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
421 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
422 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
423 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
424 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
425 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
426 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
427 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
428 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
429 };
430
431 /* Voltage Swing Programming for VccIO 0.95V for DP */
432 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
433 /* NT mV Trans mV db */
434 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
435 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
436 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
437 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
438 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
439 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
440 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
441 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
442 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
443 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
444 };
445
446 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
447 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
448 /* NT mV Trans mV db */
449 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
450 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
451 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
452 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
453 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
454 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
455 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
456 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
457 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
458 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
459 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
460 };
461
462 /* Voltage Swing Programming for VccIO 0.95V for eDP */
463 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
464 /* NT mV Trans mV db */
465 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
466 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
467 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
468 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
469 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
470 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
471 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
472 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
473 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
474 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
475 };
476
477 /* Voltage Swing Programming for VccIO 1.05V for DP */
478 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
479 /* NT mV Trans mV db */
480 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
481 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
482 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
483 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
484 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
485 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
486 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
487 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
488 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
489 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
490 };
491
492 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
493 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
494 /* NT mV Trans mV db */
495 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
496 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
497 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
498 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
499 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
500 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
501 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
502 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
503 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
504 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
505 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
506 };
507
508 /* Voltage Swing Programming for VccIO 1.05V for eDP */
509 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
510 /* NT mV Trans mV db */
511 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
512 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
513 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
514 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
515 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
516 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
517 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
518 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
519 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
520 };
521
522 /* icl_combo_phy_ddi_translations */
523 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
524 /* NT mV Trans mV db */
525 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
526 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
527 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
528 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
529 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
530 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
531 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
532 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
533 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
534 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
535 };
536
537 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
538 /* NT mV Trans mV db */
539 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
540 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
541 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
542 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
543 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
544 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
545 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
546 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
547 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
548 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
549 };
550
551 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
552 /* NT mV Trans mV db */
553 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
554 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
555 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
556 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
557 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
558 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
559 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
560 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
561 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
562 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
563 };
564
565 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
566 /* NT mV Trans mV db */
567 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
568 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
569 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
570 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
571 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
572 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
573 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
574 };
575
576 struct icl_mg_phy_ddi_buf_trans {
577 u32 cri_txdeemph_override_5_0;
578 u32 cri_txdeemph_override_11_6;
579 u32 cri_txdeemph_override_17_12;
580 };
581
582 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations[] = {
583 /* Voltage swing pre-emphasis */
584 { 0x0, 0x1B, 0x00 }, /* 0 0 */
585 { 0x0, 0x23, 0x08 }, /* 0 1 */
586 { 0x0, 0x2D, 0x12 }, /* 0 2 */
587 { 0x0, 0x00, 0x00 }, /* 0 3 */
588 { 0x0, 0x23, 0x00 }, /* 1 0 */
589 { 0x0, 0x2B, 0x09 }, /* 1 1 */
590 { 0x0, 0x2E, 0x11 }, /* 1 2 */
591 { 0x0, 0x2F, 0x00 }, /* 2 0 */
592 { 0x0, 0x33, 0x0C }, /* 2 1 */
593 { 0x0, 0x00, 0x00 }, /* 3 0 */
594 };
595
596 struct tgl_dkl_phy_ddi_buf_trans {
597 u32 dkl_vswing_control;
598 u32 dkl_preshoot_control;
599 u32 dkl_de_emphasis_control;
600 };
601
602 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
603 /* VS pre-emp Non-trans mV Pre-emph dB */
604 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
605 { 0x5, 0x0, 0x03 }, /* 0 1 400mV 3.5 dB */
606 { 0x2, 0x0, 0x0b }, /* 0 2 400mV 6 dB */
607 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */
608 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
609 { 0x2, 0x0, 0x03 }, /* 1 1 600mV 3.5 dB */
610 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
611 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
612 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
613 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
614 };
615
616 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
617 /* HDMI Preset VS Pre-emph */
618 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */
619 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */
620 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */
621 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */
622 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */
623 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */
624 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */
625 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */
626 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */
627 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
628 };
629
630 static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private * dev_priv,int * n_entries)631 bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
632 {
633 if (dev_priv->vbt.edp.low_vswing) {
634 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
635 return bdw_ddi_translations_edp;
636 } else {
637 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
638 return bdw_ddi_translations_dp;
639 }
640 }
641
642 static const struct ddi_buf_trans *
skl_get_buf_trans_dp(struct drm_i915_private * dev_priv,int * n_entries)643 skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
644 {
645 if (IS_SKL_ULX(dev_priv)) {
646 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
647 return skl_y_ddi_translations_dp;
648 } else if (IS_SKL_ULT(dev_priv)) {
649 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
650 return skl_u_ddi_translations_dp;
651 } else {
652 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
653 return skl_ddi_translations_dp;
654 }
655 }
656
657 static const struct ddi_buf_trans *
kbl_get_buf_trans_dp(struct drm_i915_private * dev_priv,int * n_entries)658 kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
659 {
660 if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
661 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
662 return kbl_y_ddi_translations_dp;
663 } else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
664 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
665 return kbl_u_ddi_translations_dp;
666 } else {
667 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
668 return kbl_ddi_translations_dp;
669 }
670 }
671
672 static const struct ddi_buf_trans *
skl_get_buf_trans_edp(struct drm_i915_private * dev_priv,int * n_entries)673 skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
674 {
675 if (dev_priv->vbt.edp.low_vswing) {
676 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
677 IS_CFL_ULX(dev_priv)) {
678 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
679 return skl_y_ddi_translations_edp;
680 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
681 IS_CFL_ULT(dev_priv)) {
682 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
683 return skl_u_ddi_translations_edp;
684 } else {
685 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
686 return skl_ddi_translations_edp;
687 }
688 }
689
690 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
691 return kbl_get_buf_trans_dp(dev_priv, n_entries);
692 else
693 return skl_get_buf_trans_dp(dev_priv, n_entries);
694 }
695
696 static const struct ddi_buf_trans *
skl_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)697 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
698 {
699 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
700 IS_CFL_ULX(dev_priv)) {
701 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
702 return skl_y_ddi_translations_hdmi;
703 } else {
704 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
705 return skl_ddi_translations_hdmi;
706 }
707 }
708
skl_buf_trans_num_entries(enum port port,int n_entries)709 static int skl_buf_trans_num_entries(enum port port, int n_entries)
710 {
711 /* Only DDIA and DDIE can select the 10th register with DP */
712 if (port == PORT_A || port == PORT_E)
713 return min(n_entries, 10);
714 else
715 return min(n_entries, 9);
716 }
717
718 static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_dp(struct drm_i915_private * dev_priv,enum port port,int * n_entries)719 intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
720 enum port port, int *n_entries)
721 {
722 if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
723 const struct ddi_buf_trans *ddi_translations =
724 kbl_get_buf_trans_dp(dev_priv, n_entries);
725 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
726 return ddi_translations;
727 } else if (IS_SKYLAKE(dev_priv)) {
728 const struct ddi_buf_trans *ddi_translations =
729 skl_get_buf_trans_dp(dev_priv, n_entries);
730 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
731 return ddi_translations;
732 } else if (IS_BROADWELL(dev_priv)) {
733 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
734 return bdw_ddi_translations_dp;
735 } else if (IS_HASWELL(dev_priv)) {
736 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
737 return hsw_ddi_translations_dp;
738 }
739
740 *n_entries = 0;
741 return NULL;
742 }
743
744 static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_edp(struct drm_i915_private * dev_priv,enum port port,int * n_entries)745 intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
746 enum port port, int *n_entries)
747 {
748 if (IS_GEN9_BC(dev_priv)) {
749 const struct ddi_buf_trans *ddi_translations =
750 skl_get_buf_trans_edp(dev_priv, n_entries);
751 *n_entries = skl_buf_trans_num_entries(port, *n_entries);
752 return ddi_translations;
753 } else if (IS_BROADWELL(dev_priv)) {
754 return bdw_get_buf_trans_edp(dev_priv, n_entries);
755 } else if (IS_HASWELL(dev_priv)) {
756 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
757 return hsw_ddi_translations_dp;
758 }
759
760 *n_entries = 0;
761 return NULL;
762 }
763
764 static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_fdi(struct drm_i915_private * dev_priv,int * n_entries)765 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
766 int *n_entries)
767 {
768 if (IS_BROADWELL(dev_priv)) {
769 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
770 return bdw_ddi_translations_fdi;
771 } else if (IS_HASWELL(dev_priv)) {
772 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
773 return hsw_ddi_translations_fdi;
774 }
775
776 *n_entries = 0;
777 return NULL;
778 }
779
780 static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)781 intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
782 int *n_entries)
783 {
784 if (IS_GEN9_BC(dev_priv)) {
785 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
786 } else if (IS_BROADWELL(dev_priv)) {
787 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
788 return bdw_ddi_translations_hdmi;
789 } else if (IS_HASWELL(dev_priv)) {
790 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
791 return hsw_ddi_translations_hdmi;
792 }
793
794 *n_entries = 0;
795 return NULL;
796 }
797
798 static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_dp(struct drm_i915_private * dev_priv,int * n_entries)799 bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
800 {
801 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
802 return bxt_ddi_translations_dp;
803 }
804
805 static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_edp(struct drm_i915_private * dev_priv,int * n_entries)806 bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
807 {
808 if (dev_priv->vbt.edp.low_vswing) {
809 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
810 return bxt_ddi_translations_edp;
811 }
812
813 return bxt_get_buf_trans_dp(dev_priv, n_entries);
814 }
815
816 static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)817 bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
818 {
819 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
820 return bxt_ddi_translations_hdmi;
821 }
822
823 static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)824 cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
825 {
826 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
827
828 if (voltage == VOLTAGE_INFO_0_85V) {
829 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
830 return cnl_ddi_translations_hdmi_0_85V;
831 } else if (voltage == VOLTAGE_INFO_0_95V) {
832 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
833 return cnl_ddi_translations_hdmi_0_95V;
834 } else if (voltage == VOLTAGE_INFO_1_05V) {
835 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
836 return cnl_ddi_translations_hdmi_1_05V;
837 } else {
838 *n_entries = 1; /* shut up gcc */
839 MISSING_CASE(voltage);
840 }
841 return NULL;
842 }
843
844 static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_dp(struct drm_i915_private * dev_priv,int * n_entries)845 cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
846 {
847 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
848
849 if (voltage == VOLTAGE_INFO_0_85V) {
850 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
851 return cnl_ddi_translations_dp_0_85V;
852 } else if (voltage == VOLTAGE_INFO_0_95V) {
853 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
854 return cnl_ddi_translations_dp_0_95V;
855 } else if (voltage == VOLTAGE_INFO_1_05V) {
856 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
857 return cnl_ddi_translations_dp_1_05V;
858 } else {
859 *n_entries = 1; /* shut up gcc */
860 MISSING_CASE(voltage);
861 }
862 return NULL;
863 }
864
865 static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_edp(struct drm_i915_private * dev_priv,int * n_entries)866 cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
867 {
868 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
869
870 if (dev_priv->vbt.edp.low_vswing) {
871 if (voltage == VOLTAGE_INFO_0_85V) {
872 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
873 return cnl_ddi_translations_edp_0_85V;
874 } else if (voltage == VOLTAGE_INFO_0_95V) {
875 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
876 return cnl_ddi_translations_edp_0_95V;
877 } else if (voltage == VOLTAGE_INFO_1_05V) {
878 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
879 return cnl_ddi_translations_edp_1_05V;
880 } else {
881 *n_entries = 1; /* shut up gcc */
882 MISSING_CASE(voltage);
883 }
884 return NULL;
885 } else {
886 return cnl_get_buf_trans_dp(dev_priv, n_entries);
887 }
888 }
889
890 static const struct cnl_ddi_buf_trans *
icl_get_combo_buf_trans(struct drm_i915_private * dev_priv,int type,int rate,int * n_entries)891 icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
892 int *n_entries)
893 {
894 if (type == INTEL_OUTPUT_HDMI) {
895 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
896 return icl_combo_phy_ddi_translations_hdmi;
897 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
898 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
899 return icl_combo_phy_ddi_translations_edp_hbr3;
900 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
901 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
902 return icl_combo_phy_ddi_translations_edp_hbr2;
903 }
904
905 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
906 return icl_combo_phy_ddi_translations_dp_hbr2;
907 }
908
intel_ddi_hdmi_level(struct drm_i915_private * dev_priv,enum port port)909 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
910 {
911 struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port];
912 int n_entries, level, default_entry;
913 enum phy phy = intel_port_to_phy(dev_priv, port);
914
915 if (INTEL_GEN(dev_priv) >= 12) {
916 if (intel_phy_is_combo(dev_priv, phy))
917 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
918 0, &n_entries);
919 else
920 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
921 default_entry = n_entries - 1;
922 } else if (INTEL_GEN(dev_priv) == 11) {
923 if (intel_phy_is_combo(dev_priv, phy))
924 icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
925 0, &n_entries);
926 else
927 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
928 default_entry = n_entries - 1;
929 } else if (IS_CANNONLAKE(dev_priv)) {
930 cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
931 default_entry = n_entries - 1;
932 } else if (IS_GEN9_LP(dev_priv)) {
933 bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
934 default_entry = n_entries - 1;
935 } else if (IS_GEN9_BC(dev_priv)) {
936 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
937 default_entry = 8;
938 } else if (IS_BROADWELL(dev_priv)) {
939 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
940 default_entry = 7;
941 } else if (IS_HASWELL(dev_priv)) {
942 intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
943 default_entry = 6;
944 } else {
945 WARN(1, "ddi translation table missing\n");
946 return 0;
947 }
948
949 if (WARN_ON_ONCE(n_entries == 0))
950 return 0;
951
952 if (port_info->hdmi_level_shift_set)
953 level = port_info->hdmi_level_shift;
954 else
955 level = default_entry;
956
957 if (WARN_ON_ONCE(level >= n_entries))
958 level = n_entries - 1;
959
960 return level;
961 }
962
963 /*
964 * Starting with Haswell, DDI port buffers must be programmed with correct
965 * values in advance. This function programs the correct values for
966 * DP/eDP/FDI use cases.
967 */
intel_prepare_dp_ddi_buffers(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)968 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
969 const struct intel_crtc_state *crtc_state)
970 {
971 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
972 u32 iboost_bit = 0;
973 int i, n_entries;
974 enum port port = encoder->port;
975 const struct ddi_buf_trans *ddi_translations;
976
977 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
978 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
979 &n_entries);
980 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
981 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port,
982 &n_entries);
983 else
984 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port,
985 &n_entries);
986
987 /* If we're boosting the current, set bit 31 of trans1 */
988 if (IS_GEN9_BC(dev_priv) &&
989 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
990 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
991
992 for (i = 0; i < n_entries; i++) {
993 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
994 ddi_translations[i].trans1 | iboost_bit);
995 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
996 ddi_translations[i].trans2);
997 }
998 }
999
1000 /*
1001 * Starting with Haswell, DDI port buffers must be programmed with correct
1002 * values in advance. This function programs the correct values for
1003 * HDMI/DVI use cases.
1004 */
intel_prepare_hdmi_ddi_buffers(struct intel_encoder * encoder,int level)1005 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1006 int level)
1007 {
1008 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1009 u32 iboost_bit = 0;
1010 int n_entries;
1011 enum port port = encoder->port;
1012 const struct ddi_buf_trans *ddi_translations;
1013
1014 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
1015
1016 if (WARN_ON_ONCE(!ddi_translations))
1017 return;
1018 if (WARN_ON_ONCE(level >= n_entries))
1019 level = n_entries - 1;
1020
1021 /* If we're boosting the current, set bit 31 of trans1 */
1022 if (IS_GEN9_BC(dev_priv) &&
1023 dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
1024 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1025
1026 /* Entry 9 is for HDMI: */
1027 I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
1028 ddi_translations[level].trans1 | iboost_bit);
1029 I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
1030 ddi_translations[level].trans2);
1031 }
1032
intel_wait_ddi_buf_idle(struct drm_i915_private * dev_priv,enum port port)1033 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1034 enum port port)
1035 {
1036 i915_reg_t reg = DDI_BUF_CTL(port);
1037 int i;
1038
1039 for (i = 0; i < 16; i++) {
1040 udelay(1);
1041 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1042 return;
1043 }
1044 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
1045 }
1046
hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll * pll)1047 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1048 {
1049 switch (pll->info->id) {
1050 case DPLL_ID_WRPLL1:
1051 return PORT_CLK_SEL_WRPLL1;
1052 case DPLL_ID_WRPLL2:
1053 return PORT_CLK_SEL_WRPLL2;
1054 case DPLL_ID_SPLL:
1055 return PORT_CLK_SEL_SPLL;
1056 case DPLL_ID_LCPLL_810:
1057 return PORT_CLK_SEL_LCPLL_810;
1058 case DPLL_ID_LCPLL_1350:
1059 return PORT_CLK_SEL_LCPLL_1350;
1060 case DPLL_ID_LCPLL_2700:
1061 return PORT_CLK_SEL_LCPLL_2700;
1062 default:
1063 MISSING_CASE(pll->info->id);
1064 return PORT_CLK_SEL_NONE;
1065 }
1066 }
1067
icl_pll_to_ddi_clk_sel(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1068 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1069 const struct intel_crtc_state *crtc_state)
1070 {
1071 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1072 int clock = crtc_state->port_clock;
1073 const enum intel_dpll_id id = pll->info->id;
1074
1075 switch (id) {
1076 default:
1077 /*
1078 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1079 * here, so do warn if this get passed in
1080 */
1081 MISSING_CASE(id);
1082 return DDI_CLK_SEL_NONE;
1083 case DPLL_ID_ICL_TBTPLL:
1084 switch (clock) {
1085 case 162000:
1086 return DDI_CLK_SEL_TBT_162;
1087 case 270000:
1088 return DDI_CLK_SEL_TBT_270;
1089 case 540000:
1090 return DDI_CLK_SEL_TBT_540;
1091 case 810000:
1092 return DDI_CLK_SEL_TBT_810;
1093 default:
1094 MISSING_CASE(clock);
1095 return DDI_CLK_SEL_NONE;
1096 }
1097 case DPLL_ID_ICL_MGPLL1:
1098 case DPLL_ID_ICL_MGPLL2:
1099 case DPLL_ID_ICL_MGPLL3:
1100 case DPLL_ID_ICL_MGPLL4:
1101 case DPLL_ID_TGL_MGPLL5:
1102 case DPLL_ID_TGL_MGPLL6:
1103 return DDI_CLK_SEL_MG;
1104 }
1105 }
1106
1107 /* Starting with Haswell, different DDI ports can work in FDI mode for
1108 * connection to the PCH-located connectors. For this, it is necessary to train
1109 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1110 *
1111 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1112 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1113 * DDI A (which is used for eDP)
1114 */
1115
hsw_fdi_link_train(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1116 void hsw_fdi_link_train(struct intel_encoder *encoder,
1117 const struct intel_crtc_state *crtc_state)
1118 {
1119 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1120 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1121 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1122
1123 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1124
1125 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1126 * mode set "sequence for CRT port" document:
1127 * - TP1 to TP2 time with the default value
1128 * - FDI delay to 90h
1129 *
1130 * WaFDIAutoLinkSetTimingOverrride:hsw
1131 */
1132 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
1133 FDI_RX_PWRDN_LANE0_VAL(2) |
1134 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1135
1136 /* Enable the PCH Receiver FDI PLL */
1137 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1138 FDI_RX_PLL_ENABLE |
1139 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1140 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1141 POSTING_READ(FDI_RX_CTL(PIPE_A));
1142 udelay(220);
1143
1144 /* Switch from Rawclk to PCDclk */
1145 rx_ctl_val |= FDI_PCDCLK;
1146 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1147
1148 /* Configure Port Clock Select */
1149 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1150 I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1151 WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
1152
1153 /* Start the training iterating through available voltages and emphasis,
1154 * testing each value twice. */
1155 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1156 /* Configure DP_TP_CTL with auto-training */
1157 I915_WRITE(DP_TP_CTL(PORT_E),
1158 DP_TP_CTL_FDI_AUTOTRAIN |
1159 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1160 DP_TP_CTL_LINK_TRAIN_PAT1 |
1161 DP_TP_CTL_ENABLE);
1162
1163 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1164 * DDI E does not support port reversal, the functionality is
1165 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1166 * port reversal bit */
1167 I915_WRITE(DDI_BUF_CTL(PORT_E),
1168 DDI_BUF_CTL_ENABLE |
1169 ((crtc_state->fdi_lanes - 1) << 1) |
1170 DDI_BUF_TRANS_SELECT(i / 2));
1171 POSTING_READ(DDI_BUF_CTL(PORT_E));
1172
1173 udelay(600);
1174
1175 /* Program PCH FDI Receiver TU */
1176 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1177
1178 /* Enable PCH FDI Receiver with auto-training */
1179 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1180 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1181 POSTING_READ(FDI_RX_CTL(PIPE_A));
1182
1183 /* Wait for FDI receiver lane calibration */
1184 udelay(30);
1185
1186 /* Unset FDI_RX_MISC pwrdn lanes */
1187 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1188 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1189 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1190 POSTING_READ(FDI_RX_MISC(PIPE_A));
1191
1192 /* Wait for FDI auto training time */
1193 udelay(5);
1194
1195 temp = I915_READ(DP_TP_STATUS(PORT_E));
1196 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1197 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
1198 break;
1199 }
1200
1201 /*
1202 * Leave things enabled even if we failed to train FDI.
1203 * Results in less fireworks from the state checker.
1204 */
1205 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1206 DRM_ERROR("FDI link training failed!\n");
1207 break;
1208 }
1209
1210 rx_ctl_val &= ~FDI_RX_ENABLE;
1211 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
1212 POSTING_READ(FDI_RX_CTL(PIPE_A));
1213
1214 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1215 temp &= ~DDI_BUF_CTL_ENABLE;
1216 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
1217 POSTING_READ(DDI_BUF_CTL(PORT_E));
1218
1219 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1220 temp = I915_READ(DP_TP_CTL(PORT_E));
1221 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1222 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1223 I915_WRITE(DP_TP_CTL(PORT_E), temp);
1224 POSTING_READ(DP_TP_CTL(PORT_E));
1225
1226 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1227
1228 /* Reset FDI_RX_MISC pwrdn lanes */
1229 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1230 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1231 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1232 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
1233 POSTING_READ(FDI_RX_MISC(PIPE_A));
1234 }
1235
1236 /* Enable normal pixel sending for FDI */
1237 I915_WRITE(DP_TP_CTL(PORT_E),
1238 DP_TP_CTL_FDI_AUTOTRAIN |
1239 DP_TP_CTL_LINK_TRAIN_NORMAL |
1240 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1241 DP_TP_CTL_ENABLE);
1242 }
1243
intel_ddi_init_dp_buf_reg(struct intel_encoder * encoder)1244 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1245 {
1246 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1247 struct intel_digital_port *intel_dig_port =
1248 enc_to_dig_port(encoder);
1249
1250 intel_dp->DP = intel_dig_port->saved_port_bits |
1251 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1252 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1253 }
1254
1255 static struct intel_encoder *
intel_ddi_get_crtc_encoder(struct intel_crtc * crtc)1256 intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
1257 {
1258 struct drm_device *dev = crtc->base.dev;
1259 struct intel_encoder *encoder, *ret = NULL;
1260 int num_encoders = 0;
1261
1262 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
1263 ret = encoder;
1264 num_encoders++;
1265 }
1266
1267 if (num_encoders != 1)
1268 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
1269 pipe_name(crtc->pipe));
1270
1271 BUG_ON(ret == NULL);
1272 return ret;
1273 }
1274
hsw_ddi_calc_wrpll_link(struct drm_i915_private * dev_priv,i915_reg_t reg)1275 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
1276 i915_reg_t reg)
1277 {
1278 int refclk;
1279 int n, p, r;
1280 u32 wrpll;
1281
1282 wrpll = I915_READ(reg);
1283 switch (wrpll & WRPLL_REF_MASK) {
1284 case WRPLL_REF_SPECIAL_HSW:
1285 /*
1286 * muxed-SSC for BDW.
1287 * non-SSC for non-ULT HSW. Check FUSE_STRAP3
1288 * for the non-SSC reference frequency.
1289 */
1290 if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
1291 if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1292 refclk = 24;
1293 else
1294 refclk = 135;
1295 break;
1296 }
1297 /* fall through */
1298 case WRPLL_REF_PCH_SSC:
1299 /*
1300 * We could calculate spread here, but our checking
1301 * code only cares about 5% accuracy, and spread is a max of
1302 * 0.5% downspread.
1303 */
1304 refclk = 135;
1305 break;
1306 case WRPLL_REF_LCPLL:
1307 refclk = 2700;
1308 break;
1309 default:
1310 MISSING_CASE(wrpll);
1311 return 0;
1312 }
1313
1314 r = wrpll & WRPLL_DIVIDER_REF_MASK;
1315 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
1316 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
1317
1318 /* Convert to KHz, p & r have a fixed point portion */
1319 return (refclk * n * 100) / (p * r);
1320 }
1321
skl_calc_wrpll_link(const struct intel_dpll_hw_state * pll_state)1322 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)
1323 {
1324 u32 p0, p1, p2, dco_freq;
1325
1326 p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1327 p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1328
1329 if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1))
1330 p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1331 else
1332 p1 = 1;
1333
1334
1335 switch (p0) {
1336 case DPLL_CFGCR2_PDIV_1:
1337 p0 = 1;
1338 break;
1339 case DPLL_CFGCR2_PDIV_2:
1340 p0 = 2;
1341 break;
1342 case DPLL_CFGCR2_PDIV_3:
1343 p0 = 3;
1344 break;
1345 case DPLL_CFGCR2_PDIV_7:
1346 p0 = 7;
1347 break;
1348 }
1349
1350 switch (p2) {
1351 case DPLL_CFGCR2_KDIV_5:
1352 p2 = 5;
1353 break;
1354 case DPLL_CFGCR2_KDIV_2:
1355 p2 = 2;
1356 break;
1357 case DPLL_CFGCR2_KDIV_3:
1358 p2 = 3;
1359 break;
1360 case DPLL_CFGCR2_KDIV_1:
1361 p2 = 1;
1362 break;
1363 }
1364
1365 dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)
1366 * 24 * 1000;
1367
1368 dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)
1369 * 24 * 1000) / 0x8000;
1370
1371 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1372 return 0;
1373
1374 return dco_freq / (p0 * p1 * p2 * 5);
1375 }
1376
cnl_calc_wrpll_link(struct drm_i915_private * dev_priv,struct intel_dpll_hw_state * pll_state)1377 int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
1378 struct intel_dpll_hw_state *pll_state)
1379 {
1380 u32 p0, p1, p2, dco_freq, ref_clock;
1381
1382 p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
1383 p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
1384
1385 if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
1386 p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
1387 DPLL_CFGCR1_QDIV_RATIO_SHIFT;
1388 else
1389 p1 = 1;
1390
1391
1392 switch (p0) {
1393 case DPLL_CFGCR1_PDIV_2:
1394 p0 = 2;
1395 break;
1396 case DPLL_CFGCR1_PDIV_3:
1397 p0 = 3;
1398 break;
1399 case DPLL_CFGCR1_PDIV_5:
1400 p0 = 5;
1401 break;
1402 case DPLL_CFGCR1_PDIV_7:
1403 p0 = 7;
1404 break;
1405 }
1406
1407 switch (p2) {
1408 case DPLL_CFGCR1_KDIV_1:
1409 p2 = 1;
1410 break;
1411 case DPLL_CFGCR1_KDIV_2:
1412 p2 = 2;
1413 break;
1414 case DPLL_CFGCR1_KDIV_3:
1415 p2 = 3;
1416 break;
1417 }
1418
1419 ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
1420
1421 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)
1422 * ref_clock;
1423
1424 dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
1425 DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
1426
1427 if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0))
1428 return 0;
1429
1430 return dco_freq / (p0 * p1 * p2 * 5);
1431 }
1432
icl_calc_tbt_pll_link(struct drm_i915_private * dev_priv,enum port port)1433 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1434 enum port port)
1435 {
1436 u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1437
1438 switch (val) {
1439 case DDI_CLK_SEL_NONE:
1440 return 0;
1441 case DDI_CLK_SEL_TBT_162:
1442 return 162000;
1443 case DDI_CLK_SEL_TBT_270:
1444 return 270000;
1445 case DDI_CLK_SEL_TBT_540:
1446 return 540000;
1447 case DDI_CLK_SEL_TBT_810:
1448 return 810000;
1449 default:
1450 MISSING_CASE(val);
1451 return 0;
1452 }
1453 }
1454
icl_calc_mg_pll_link(struct drm_i915_private * dev_priv,const struct intel_dpll_hw_state * pll_state)1455 static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv,
1456 const struct intel_dpll_hw_state *pll_state)
1457 {
1458 u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
1459 u64 tmp;
1460
1461 ref_clock = dev_priv->cdclk.hw.ref;
1462
1463 if (INTEL_GEN(dev_priv) >= 12) {
1464 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
1465 m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
1466 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
1467
1468 if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
1469 m2_frac = pll_state->mg_pll_bias &
1470 DKL_PLL_BIAS_FBDIV_FRAC_MASK;
1471 m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
1472 } else {
1473 m2_frac = 0;
1474 }
1475 } else {
1476 m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
1477 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
1478
1479 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
1480 m2_frac = pll_state->mg_pll_div0 &
1481 MG_PLL_DIV0_FBDIV_FRAC_MASK;
1482 m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
1483 } else {
1484 m2_frac = 0;
1485 }
1486 }
1487
1488 switch (pll_state->mg_clktop2_hsclkctl &
1489 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
1490 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
1491 div1 = 2;
1492 break;
1493 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
1494 div1 = 3;
1495 break;
1496 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
1497 div1 = 5;
1498 break;
1499 case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
1500 div1 = 7;
1501 break;
1502 default:
1503 MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
1504 return 0;
1505 }
1506
1507 div2 = (pll_state->mg_clktop2_hsclkctl &
1508 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
1509 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
1510
1511 /* div2 value of 0 is same as 1 means no div */
1512 if (div2 == 0)
1513 div2 = 1;
1514
1515 /*
1516 * Adjust the original formula to delay the division by 2^22 in order to
1517 * minimize possible rounding errors.
1518 */
1519 tmp = (u64)m1 * m2_int * ref_clock +
1520 (((u64)m1 * m2_frac * ref_clock) >> 22);
1521 tmp = div_u64(tmp, 5 * div1 * div2);
1522
1523 return tmp;
1524 }
1525
ddi_dotclock_get(struct intel_crtc_state * pipe_config)1526 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1527 {
1528 int dotclock;
1529
1530 if (pipe_config->has_pch_encoder)
1531 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1532 &pipe_config->fdi_m_n);
1533 else if (intel_crtc_has_dp_encoder(pipe_config))
1534 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1535 &pipe_config->dp_m_n);
1536 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1537 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1538 else
1539 dotclock = pipe_config->port_clock;
1540
1541 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1542 !intel_crtc_has_dp_encoder(pipe_config))
1543 dotclock *= 2;
1544
1545 if (pipe_config->pixel_multiplier)
1546 dotclock /= pipe_config->pixel_multiplier;
1547
1548 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1549 }
1550
icl_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1551 static void icl_ddi_clock_get(struct intel_encoder *encoder,
1552 struct intel_crtc_state *pipe_config)
1553 {
1554 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1555 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1556 enum port port = encoder->port;
1557 enum phy phy = intel_port_to_phy(dev_priv, port);
1558 int link_clock;
1559
1560 if (intel_phy_is_combo(dev_priv, phy)) {
1561 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1562 } else {
1563 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
1564 pipe_config->shared_dpll);
1565
1566 if (pll_id == DPLL_ID_ICL_TBTPLL)
1567 link_clock = icl_calc_tbt_pll_link(dev_priv, port);
1568 else
1569 link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);
1570 }
1571
1572 pipe_config->port_clock = link_clock;
1573
1574 ddi_dotclock_get(pipe_config);
1575 }
1576
cnl_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1577 static void cnl_ddi_clock_get(struct intel_encoder *encoder,
1578 struct intel_crtc_state *pipe_config)
1579 {
1580 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1581 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1582 int link_clock;
1583
1584 if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
1585 link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1586 } else {
1587 link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;
1588
1589 switch (link_clock) {
1590 case DPLL_CFGCR0_LINK_RATE_810:
1591 link_clock = 81000;
1592 break;
1593 case DPLL_CFGCR0_LINK_RATE_1080:
1594 link_clock = 108000;
1595 break;
1596 case DPLL_CFGCR0_LINK_RATE_1350:
1597 link_clock = 135000;
1598 break;
1599 case DPLL_CFGCR0_LINK_RATE_1620:
1600 link_clock = 162000;
1601 break;
1602 case DPLL_CFGCR0_LINK_RATE_2160:
1603 link_clock = 216000;
1604 break;
1605 case DPLL_CFGCR0_LINK_RATE_2700:
1606 link_clock = 270000;
1607 break;
1608 case DPLL_CFGCR0_LINK_RATE_3240:
1609 link_clock = 324000;
1610 break;
1611 case DPLL_CFGCR0_LINK_RATE_4050:
1612 link_clock = 405000;
1613 break;
1614 default:
1615 WARN(1, "Unsupported link rate\n");
1616 break;
1617 }
1618 link_clock *= 2;
1619 }
1620
1621 pipe_config->port_clock = link_clock;
1622
1623 ddi_dotclock_get(pipe_config);
1624 }
1625
skl_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1626 static void skl_ddi_clock_get(struct intel_encoder *encoder,
1627 struct intel_crtc_state *pipe_config)
1628 {
1629 struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1630 int link_clock;
1631
1632 /*
1633 * ctrl1 register is already shifted for each pll, just use 0 to get
1634 * the internal shift for each field
1635 */
1636 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {
1637 link_clock = skl_calc_wrpll_link(pll_state);
1638 } else {
1639 link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);
1640 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0);
1641
1642 switch (link_clock) {
1643 case DPLL_CTRL1_LINK_RATE_810:
1644 link_clock = 81000;
1645 break;
1646 case DPLL_CTRL1_LINK_RATE_1080:
1647 link_clock = 108000;
1648 break;
1649 case DPLL_CTRL1_LINK_RATE_1350:
1650 link_clock = 135000;
1651 break;
1652 case DPLL_CTRL1_LINK_RATE_1620:
1653 link_clock = 162000;
1654 break;
1655 case DPLL_CTRL1_LINK_RATE_2160:
1656 link_clock = 216000;
1657 break;
1658 case DPLL_CTRL1_LINK_RATE_2700:
1659 link_clock = 270000;
1660 break;
1661 default:
1662 WARN(1, "Unsupported link rate\n");
1663 break;
1664 }
1665 link_clock *= 2;
1666 }
1667
1668 pipe_config->port_clock = link_clock;
1669
1670 ddi_dotclock_get(pipe_config);
1671 }
1672
hsw_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1673 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1674 struct intel_crtc_state *pipe_config)
1675 {
1676 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1677 int link_clock = 0;
1678 u32 val, pll;
1679
1680 val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1681 switch (val & PORT_CLK_SEL_MASK) {
1682 case PORT_CLK_SEL_LCPLL_810:
1683 link_clock = 81000;
1684 break;
1685 case PORT_CLK_SEL_LCPLL_1350:
1686 link_clock = 135000;
1687 break;
1688 case PORT_CLK_SEL_LCPLL_2700:
1689 link_clock = 270000;
1690 break;
1691 case PORT_CLK_SEL_WRPLL1:
1692 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1693 break;
1694 case PORT_CLK_SEL_WRPLL2:
1695 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1696 break;
1697 case PORT_CLK_SEL_SPLL:
1698 pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
1699 if (pll == SPLL_FREQ_810MHz)
1700 link_clock = 81000;
1701 else if (pll == SPLL_FREQ_1350MHz)
1702 link_clock = 135000;
1703 else if (pll == SPLL_FREQ_2700MHz)
1704 link_clock = 270000;
1705 else {
1706 WARN(1, "bad spll freq\n");
1707 return;
1708 }
1709 break;
1710 default:
1711 WARN(1, "bad port clock sel\n");
1712 return;
1713 }
1714
1715 pipe_config->port_clock = link_clock * 2;
1716
1717 ddi_dotclock_get(pipe_config);
1718 }
1719
bxt_calc_pll_link(const struct intel_dpll_hw_state * pll_state)1720 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)
1721 {
1722 struct dpll clock;
1723
1724 clock.m1 = 2;
1725 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;
1726 if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
1727 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
1728 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
1729 clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
1730 clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
1731
1732 return chv_calc_dpll_params(100000, &clock);
1733 }
1734
bxt_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1735 static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1736 struct intel_crtc_state *pipe_config)
1737 {
1738 pipe_config->port_clock =
1739 bxt_calc_pll_link(&pipe_config->dpll_hw_state);
1740
1741 ddi_dotclock_get(pipe_config);
1742 }
1743
intel_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1744 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1745 struct intel_crtc_state *pipe_config)
1746 {
1747 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1748
1749 if (INTEL_GEN(dev_priv) >= 11)
1750 icl_ddi_clock_get(encoder, pipe_config);
1751 else if (IS_CANNONLAKE(dev_priv))
1752 cnl_ddi_clock_get(encoder, pipe_config);
1753 else if (IS_GEN9_LP(dev_priv))
1754 bxt_ddi_clock_get(encoder, pipe_config);
1755 else if (IS_GEN9_BC(dev_priv))
1756 skl_ddi_clock_get(encoder, pipe_config);
1757 else if (INTEL_GEN(dev_priv) <= 8)
1758 hsw_ddi_clock_get(encoder, pipe_config);
1759 }
1760
intel_ddi_set_dp_msa(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1761 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1762 const struct drm_connector_state *conn_state)
1763 {
1764 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1766 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1767 u32 temp;
1768
1769 if (!intel_crtc_has_dp_encoder(crtc_state))
1770 return;
1771
1772 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1773
1774 temp = DP_MSA_MISC_SYNC_CLOCK;
1775
1776 switch (crtc_state->pipe_bpp) {
1777 case 18:
1778 temp |= DP_MSA_MISC_6_BPC;
1779 break;
1780 case 24:
1781 temp |= DP_MSA_MISC_8_BPC;
1782 break;
1783 case 30:
1784 temp |= DP_MSA_MISC_10_BPC;
1785 break;
1786 case 36:
1787 temp |= DP_MSA_MISC_12_BPC;
1788 break;
1789 default:
1790 MISSING_CASE(crtc_state->pipe_bpp);
1791 break;
1792 }
1793
1794 /* nonsense combination */
1795 WARN_ON(crtc_state->limited_color_range &&
1796 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1797
1798 if (crtc_state->limited_color_range)
1799 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1800
1801 /*
1802 * As per DP 1.2 spec section 2.3.4.3 while sending
1803 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1804 * colorspace information.
1805 */
1806 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1807 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1808
1809 /*
1810 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1811 * of Color Encoding Format and Content Color Gamut] while sending
1812 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1813 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1814 */
1815 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1816 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1817
1818 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1819 }
1820
1821 /*
1822 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1823 *
1824 * Only intended to be used by intel_ddi_enable_transcoder_func() and
1825 * intel_ddi_config_transcoder_func().
1826 */
1827 static u32
intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state * crtc_state)1828 intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state)
1829 {
1830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1831 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1832 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1833 enum pipe pipe = crtc->pipe;
1834 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1835 enum port port = encoder->port;
1836 u32 temp;
1837
1838 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1839 temp = TRANS_DDI_FUNC_ENABLE;
1840 if (INTEL_GEN(dev_priv) >= 12)
1841 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1842 else
1843 temp |= TRANS_DDI_SELECT_PORT(port);
1844
1845 switch (crtc_state->pipe_bpp) {
1846 case 18:
1847 temp |= TRANS_DDI_BPC_6;
1848 break;
1849 case 24:
1850 temp |= TRANS_DDI_BPC_8;
1851 break;
1852 case 30:
1853 temp |= TRANS_DDI_BPC_10;
1854 break;
1855 case 36:
1856 temp |= TRANS_DDI_BPC_12;
1857 break;
1858 default:
1859 BUG();
1860 }
1861
1862 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1863 temp |= TRANS_DDI_PVSYNC;
1864 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1865 temp |= TRANS_DDI_PHSYNC;
1866
1867 if (cpu_transcoder == TRANSCODER_EDP) {
1868 switch (pipe) {
1869 case PIPE_A:
1870 /* On Haswell, can only use the always-on power well for
1871 * eDP when not using the panel fitter, and when not
1872 * using motion blur mitigation (which we don't
1873 * support). */
1874 if (crtc_state->pch_pfit.force_thru)
1875 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1876 else
1877 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1878 break;
1879 case PIPE_B:
1880 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1881 break;
1882 case PIPE_C:
1883 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1884 break;
1885 default:
1886 BUG();
1887 break;
1888 }
1889 }
1890
1891 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1892 if (crtc_state->has_hdmi_sink)
1893 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1894 else
1895 temp |= TRANS_DDI_MODE_SELECT_DVI;
1896
1897 if (crtc_state->hdmi_scrambling)
1898 temp |= TRANS_DDI_HDMI_SCRAMBLING;
1899 if (crtc_state->hdmi_high_tmds_clock_ratio)
1900 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1901 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1902 temp |= TRANS_DDI_MODE_SELECT_FDI;
1903 temp |= (crtc_state->fdi_lanes - 1) << 1;
1904 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1905 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1906 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1907
1908 if (INTEL_GEN(dev_priv) >= 12) {
1909 enum transcoder master;
1910
1911 master = crtc_state->mst_master_transcoder;
1912 WARN_ON(master == INVALID_TRANSCODER);
1913 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1914 }
1915 } else {
1916 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1917 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1918 }
1919
1920 return temp;
1921 }
1922
intel_ddi_enable_transcoder_func(const struct intel_crtc_state * crtc_state)1923 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1924 {
1925 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1926 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1927 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1928 u32 temp;
1929
1930 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1931 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
1932 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1933 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1934 }
1935
1936 /*
1937 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1938 * bit.
1939 */
1940 static void
intel_ddi_config_transcoder_func(const struct intel_crtc_state * crtc_state)1941 intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state)
1942 {
1943 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1944 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1945 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1946 u32 temp;
1947
1948 temp = intel_ddi_transcoder_func_reg_val_get(crtc_state);
1949 temp &= ~TRANS_DDI_FUNC_ENABLE;
1950 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1951 }
1952
intel_ddi_disable_transcoder_func(const struct intel_crtc_state * crtc_state)1953 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1954 {
1955 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1956 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1957 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1958 u32 val;
1959
1960 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1961 val &= ~TRANS_DDI_FUNC_ENABLE;
1962
1963 if (INTEL_GEN(dev_priv) >= 12) {
1964 if (!intel_dp_mst_is_master_trans(crtc_state))
1965 val &= ~TGL_TRANS_DDI_PORT_MASK;
1966 } else {
1967 val &= ~TRANS_DDI_PORT_MASK;
1968 }
1969 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), val);
1970
1971 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1972 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1973 DRM_DEBUG_KMS("Quirk Increase DDI disabled time\n");
1974 /* Quirk time at 100ms for reliable operation */
1975 msleep(100);
1976 }
1977 }
1978
intel_ddi_toggle_hdcp_signalling(struct intel_encoder * intel_encoder,bool enable)1979 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1980 bool enable)
1981 {
1982 struct drm_device *dev = intel_encoder->base.dev;
1983 struct drm_i915_private *dev_priv = to_i915(dev);
1984 intel_wakeref_t wakeref;
1985 enum pipe pipe = 0;
1986 int ret = 0;
1987 u32 tmp;
1988
1989 wakeref = intel_display_power_get_if_enabled(dev_priv,
1990 intel_encoder->power_domain);
1991 if (WARN_ON(!wakeref))
1992 return -ENXIO;
1993
1994 if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1995 ret = -EIO;
1996 goto out;
1997 }
1998
1999 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
2000 if (enable)
2001 tmp |= TRANS_DDI_HDCP_SIGNALLING;
2002 else
2003 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
2004 I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp);
2005 out:
2006 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
2007 return ret;
2008 }
2009
intel_ddi_connector_get_hw_state(struct intel_connector * intel_connector)2010 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
2011 {
2012 struct drm_device *dev = intel_connector->base.dev;
2013 struct drm_i915_private *dev_priv = to_i915(dev);
2014 struct intel_encoder *encoder = intel_connector->encoder;
2015 int type = intel_connector->base.connector_type;
2016 enum port port = encoder->port;
2017 enum transcoder cpu_transcoder;
2018 intel_wakeref_t wakeref;
2019 enum pipe pipe = 0;
2020 u32 tmp;
2021 bool ret;
2022
2023 wakeref = intel_display_power_get_if_enabled(dev_priv,
2024 encoder->power_domain);
2025 if (!wakeref)
2026 return false;
2027
2028 if (!encoder->get_hw_state(encoder, &pipe)) {
2029 ret = false;
2030 goto out;
2031 }
2032
2033 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
2034 cpu_transcoder = TRANSCODER_EDP;
2035 else
2036 cpu_transcoder = (enum transcoder) pipe;
2037
2038 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2039
2040 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
2041 case TRANS_DDI_MODE_SELECT_HDMI:
2042 case TRANS_DDI_MODE_SELECT_DVI:
2043 ret = type == DRM_MODE_CONNECTOR_HDMIA;
2044 break;
2045
2046 case TRANS_DDI_MODE_SELECT_DP_SST:
2047 ret = type == DRM_MODE_CONNECTOR_eDP ||
2048 type == DRM_MODE_CONNECTOR_DisplayPort;
2049 break;
2050
2051 case TRANS_DDI_MODE_SELECT_DP_MST:
2052 /* if the transcoder is in MST state then
2053 * connector isn't connected */
2054 ret = false;
2055 break;
2056
2057 case TRANS_DDI_MODE_SELECT_FDI:
2058 ret = type == DRM_MODE_CONNECTOR_VGA;
2059 break;
2060
2061 default:
2062 ret = false;
2063 break;
2064 }
2065
2066 out:
2067 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2068
2069 return ret;
2070 }
2071
intel_ddi_get_encoder_pipes(struct intel_encoder * encoder,u8 * pipe_mask,bool * is_dp_mst)2072 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
2073 u8 *pipe_mask, bool *is_dp_mst)
2074 {
2075 struct drm_device *dev = encoder->base.dev;
2076 struct drm_i915_private *dev_priv = to_i915(dev);
2077 enum port port = encoder->port;
2078 intel_wakeref_t wakeref;
2079 enum pipe p;
2080 u32 tmp;
2081 u8 mst_pipe_mask;
2082
2083 *pipe_mask = 0;
2084 *is_dp_mst = false;
2085
2086 wakeref = intel_display_power_get_if_enabled(dev_priv,
2087 encoder->power_domain);
2088 if (!wakeref)
2089 return;
2090
2091 tmp = I915_READ(DDI_BUF_CTL(port));
2092 if (!(tmp & DDI_BUF_CTL_ENABLE))
2093 goto out;
2094
2095 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) {
2096 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
2097
2098 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2099 default:
2100 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
2101 /* fallthrough */
2102 case TRANS_DDI_EDP_INPUT_A_ON:
2103 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2104 *pipe_mask = BIT(PIPE_A);
2105 break;
2106 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2107 *pipe_mask = BIT(PIPE_B);
2108 break;
2109 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2110 *pipe_mask = BIT(PIPE_C);
2111 break;
2112 }
2113
2114 goto out;
2115 }
2116
2117 mst_pipe_mask = 0;
2118 for_each_pipe(dev_priv, p) {
2119 enum transcoder cpu_transcoder = (enum transcoder)p;
2120 unsigned int port_mask, ddi_select;
2121 intel_wakeref_t trans_wakeref;
2122
2123 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
2124 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
2125 if (!trans_wakeref)
2126 continue;
2127
2128 if (INTEL_GEN(dev_priv) >= 12) {
2129 port_mask = TGL_TRANS_DDI_PORT_MASK;
2130 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2131 } else {
2132 port_mask = TRANS_DDI_PORT_MASK;
2133 ddi_select = TRANS_DDI_SELECT_PORT(port);
2134 }
2135
2136 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2137 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2138 trans_wakeref);
2139
2140 if ((tmp & port_mask) != ddi_select)
2141 continue;
2142
2143 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2144 TRANS_DDI_MODE_SELECT_DP_MST)
2145 mst_pipe_mask |= BIT(p);
2146
2147 *pipe_mask |= BIT(p);
2148 }
2149
2150 if (!*pipe_mask)
2151 DRM_DEBUG_KMS("No pipe for [ENCODER:%d:%s] found\n",
2152 encoder->base.base.id, encoder->base.name);
2153
2154 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2155 DRM_DEBUG_KMS("Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2156 encoder->base.base.id, encoder->base.name,
2157 *pipe_mask);
2158 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2159 }
2160
2161 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2162 DRM_DEBUG_KMS("Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2163 encoder->base.base.id, encoder->base.name,
2164 *pipe_mask, mst_pipe_mask);
2165 else
2166 *is_dp_mst = mst_pipe_mask;
2167
2168 out:
2169 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2170 tmp = I915_READ(BXT_PHY_CTL(port));
2171 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2172 BXT_PHY_LANE_POWERDOWN_ACK |
2173 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2174 DRM_ERROR("[ENCODER:%d:%s] enabled but PHY powered down? "
2175 "(PHY_CTL %08x)\n", encoder->base.base.id,
2176 encoder->base.name, tmp);
2177 }
2178
2179 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2180 }
2181
intel_ddi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)2182 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2183 enum pipe *pipe)
2184 {
2185 u8 pipe_mask;
2186 bool is_mst;
2187
2188 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2189
2190 if (is_mst || !pipe_mask)
2191 return false;
2192
2193 *pipe = ffs(pipe_mask) - 1;
2194
2195 return true;
2196 }
2197
2198 static inline enum intel_display_power_domain
intel_ddi_main_link_aux_domain(struct intel_digital_port * dig_port)2199 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2200 {
2201 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2202 * DC states enabled at the same time, while for driver initiated AUX
2203 * transfers we need the same AUX IOs to be powered but with DC states
2204 * disabled. Accordingly use the AUX power domain here which leaves DC
2205 * states enabled.
2206 * However, for non-A AUX ports the corresponding non-EDP transcoders
2207 * would have already enabled power well 2 and DC_OFF. This means we can
2208 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2209 * specific AUX_IO reference without powering up any extra wells.
2210 * Note that PSR is enabled only on Port A even though this function
2211 * returns the correct domain for other ports too.
2212 */
2213 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2214 intel_aux_power_domain(dig_port);
2215 }
2216
intel_ddi_get_power_domains(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)2217 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2218 struct intel_crtc_state *crtc_state)
2219 {
2220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2221 struct intel_digital_port *dig_port;
2222 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2223
2224 /*
2225 * TODO: Add support for MST encoders. Atm, the following should never
2226 * happen since fake-MST encoders don't set their get_power_domains()
2227 * hook.
2228 */
2229 if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2230 return;
2231
2232 dig_port = enc_to_dig_port(encoder);
2233 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
2234
2235 /*
2236 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2237 * ports.
2238 */
2239 if (intel_crtc_has_dp_encoder(crtc_state) ||
2240 intel_phy_is_tc(dev_priv, phy))
2241 intel_display_power_get(dev_priv,
2242 intel_ddi_main_link_aux_domain(dig_port));
2243
2244 /*
2245 * VDSC power is needed when DSC is enabled
2246 */
2247 if (crtc_state->dsc.compression_enable)
2248 intel_display_power_get(dev_priv,
2249 intel_dsc_power_domain(crtc_state));
2250 }
2251
intel_ddi_enable_pipe_clock(const struct intel_crtc_state * crtc_state)2252 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
2253 {
2254 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2255 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2256 struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
2257 enum port port = encoder->port;
2258 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2259
2260 if (cpu_transcoder != TRANSCODER_EDP) {
2261 if (INTEL_GEN(dev_priv) >= 12)
2262 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2263 TGL_TRANS_CLK_SEL_PORT(port));
2264 else
2265 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2266 TRANS_CLK_SEL_PORT(port));
2267 }
2268 }
2269
intel_ddi_disable_pipe_clock(const struct intel_crtc_state * crtc_state)2270 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2271 {
2272 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2273 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2274
2275 if (cpu_transcoder != TRANSCODER_EDP) {
2276 if (INTEL_GEN(dev_priv) >= 12)
2277 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2278 TGL_TRANS_CLK_SEL_DISABLED);
2279 else
2280 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2281 TRANS_CLK_SEL_DISABLED);
2282 }
2283 }
2284
_skl_ddi_set_iboost(struct drm_i915_private * dev_priv,enum port port,u8 iboost)2285 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2286 enum port port, u8 iboost)
2287 {
2288 u32 tmp;
2289
2290 tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
2291 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2292 if (iboost)
2293 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2294 else
2295 tmp |= BALANCE_LEG_DISABLE(port);
2296 I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
2297 }
2298
skl_ddi_set_iboost(struct intel_encoder * encoder,int level,enum intel_output_type type)2299 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2300 int level, enum intel_output_type type)
2301 {
2302 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2303 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2304 enum port port = encoder->port;
2305 u8 iboost;
2306
2307 if (type == INTEL_OUTPUT_HDMI)
2308 iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
2309 else
2310 iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
2311
2312 if (iboost == 0) {
2313 const struct ddi_buf_trans *ddi_translations;
2314 int n_entries;
2315
2316 if (type == INTEL_OUTPUT_HDMI)
2317 ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries);
2318 else if (type == INTEL_OUTPUT_EDP)
2319 ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2320 else
2321 ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2322
2323 if (WARN_ON_ONCE(!ddi_translations))
2324 return;
2325 if (WARN_ON_ONCE(level >= n_entries))
2326 level = n_entries - 1;
2327
2328 iboost = ddi_translations[level].i_boost;
2329 }
2330
2331 /* Make sure that the requested I_boost is valid */
2332 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2333 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2334 return;
2335 }
2336
2337 _skl_ddi_set_iboost(dev_priv, port, iboost);
2338
2339 if (port == PORT_A && intel_dig_port->max_lanes == 4)
2340 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2341 }
2342
bxt_ddi_vswing_sequence(struct intel_encoder * encoder,int level,enum intel_output_type type)2343 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2344 int level, enum intel_output_type type)
2345 {
2346 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2347 const struct bxt_ddi_buf_trans *ddi_translations;
2348 enum port port = encoder->port;
2349 int n_entries;
2350
2351 if (type == INTEL_OUTPUT_HDMI)
2352 ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries);
2353 else if (type == INTEL_OUTPUT_EDP)
2354 ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries);
2355 else
2356 ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries);
2357
2358 if (WARN_ON_ONCE(!ddi_translations))
2359 return;
2360 if (WARN_ON_ONCE(level >= n_entries))
2361 level = n_entries - 1;
2362
2363 bxt_ddi_phy_set_signal_level(dev_priv, port,
2364 ddi_translations[level].margin,
2365 ddi_translations[level].scale,
2366 ddi_translations[level].enable,
2367 ddi_translations[level].deemphasis);
2368 }
2369
intel_ddi_dp_voltage_max(struct intel_encoder * encoder)2370 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
2371 {
2372 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2373 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2374 enum port port = encoder->port;
2375 enum phy phy = intel_port_to_phy(dev_priv, port);
2376 int n_entries;
2377
2378 if (INTEL_GEN(dev_priv) >= 12) {
2379 if (intel_phy_is_combo(dev_priv, phy))
2380 icl_get_combo_buf_trans(dev_priv, encoder->type,
2381 intel_dp->link_rate, &n_entries);
2382 else
2383 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2384 } else if (INTEL_GEN(dev_priv) == 11) {
2385 if (intel_phy_is_combo(dev_priv, phy))
2386 icl_get_combo_buf_trans(dev_priv, encoder->type,
2387 intel_dp->link_rate, &n_entries);
2388 else
2389 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2390 } else if (IS_CANNONLAKE(dev_priv)) {
2391 if (encoder->type == INTEL_OUTPUT_EDP)
2392 cnl_get_buf_trans_edp(dev_priv, &n_entries);
2393 else
2394 cnl_get_buf_trans_dp(dev_priv, &n_entries);
2395 } else if (IS_GEN9_LP(dev_priv)) {
2396 if (encoder->type == INTEL_OUTPUT_EDP)
2397 bxt_get_buf_trans_edp(dev_priv, &n_entries);
2398 else
2399 bxt_get_buf_trans_dp(dev_priv, &n_entries);
2400 } else {
2401 if (encoder->type == INTEL_OUTPUT_EDP)
2402 intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries);
2403 else
2404 intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries);
2405 }
2406
2407 if (WARN_ON(n_entries < 1))
2408 n_entries = 1;
2409 if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2410 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2411
2412 return index_to_dp_signal_levels[n_entries - 1] &
2413 DP_TRAIN_VOLTAGE_SWING_MASK;
2414 }
2415
2416 /*
2417 * We assume that the full set of pre-emphasis values can be
2418 * used on all DDI platforms. Should that change we need to
2419 * rethink this code.
2420 */
intel_ddi_dp_pre_emphasis_max(struct intel_encoder * encoder,u8 voltage_swing)2421 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)
2422 {
2423 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2424 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2425 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2426 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2427 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2428 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2429 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2431 default:
2432 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2433 }
2434 }
2435
cnl_ddi_vswing_program(struct intel_encoder * encoder,int level,enum intel_output_type type)2436 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2437 int level, enum intel_output_type type)
2438 {
2439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2440 const struct cnl_ddi_buf_trans *ddi_translations;
2441 enum port port = encoder->port;
2442 int n_entries, ln;
2443 u32 val;
2444
2445 if (type == INTEL_OUTPUT_HDMI)
2446 ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries);
2447 else if (type == INTEL_OUTPUT_EDP)
2448 ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries);
2449 else
2450 ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries);
2451
2452 if (WARN_ON_ONCE(!ddi_translations))
2453 return;
2454 if (WARN_ON_ONCE(level >= n_entries))
2455 level = n_entries - 1;
2456
2457 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2458 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2459 val &= ~SCALING_MODE_SEL_MASK;
2460 val |= SCALING_MODE_SEL(2);
2461 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2462
2463 /* Program PORT_TX_DW2 */
2464 val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
2465 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2466 RCOMP_SCALAR_MASK);
2467 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2468 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2469 /* Rcomp scalar is fixed as 0x98 for every table entry */
2470 val |= RCOMP_SCALAR(0x98);
2471 I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);
2472
2473 /* Program PORT_TX_DW4 */
2474 /* We cannot write to GRP. It would overrite individual loadgen */
2475 for (ln = 0; ln < 4; ln++) {
2476 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2477 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2478 CURSOR_COEFF_MASK);
2479 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2480 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2481 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2482 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2483 }
2484
2485 /* Program PORT_TX_DW5 */
2486 /* All DW5 values are fixed for every table entry */
2487 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2488 val &= ~RTERM_SELECT_MASK;
2489 val |= RTERM_SELECT(6);
2490 val |= TAP3_DISABLE;
2491 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2492
2493 /* Program PORT_TX_DW7 */
2494 val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
2495 val &= ~N_SCALAR_MASK;
2496 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2497 I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
2498 }
2499
cnl_ddi_vswing_sequence(struct intel_encoder * encoder,int level,enum intel_output_type type)2500 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2501 int level, enum intel_output_type type)
2502 {
2503 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2504 enum port port = encoder->port;
2505 int width, rate, ln;
2506 u32 val;
2507
2508 if (type == INTEL_OUTPUT_HDMI) {
2509 width = 4;
2510 rate = 0; /* Rate is always < than 6GHz for HDMI */
2511 } else {
2512 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2513
2514 width = intel_dp->lane_count;
2515 rate = intel_dp->link_rate;
2516 }
2517
2518 /*
2519 * 1. If port type is eDP or DP,
2520 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2521 * else clear to 0b.
2522 */
2523 val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
2524 if (type != INTEL_OUTPUT_HDMI)
2525 val |= COMMON_KEEPER_EN;
2526 else
2527 val &= ~COMMON_KEEPER_EN;
2528 I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);
2529
2530 /* 2. Program loadgen select */
2531 /*
2532 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2533 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2534 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2535 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2536 */
2537 for (ln = 0; ln <= 3; ln++) {
2538 val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port));
2539 val &= ~LOADGEN_SELECT;
2540
2541 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2542 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2543 val |= LOADGEN_SELECT;
2544 }
2545 I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val);
2546 }
2547
2548 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2549 val = I915_READ(CNL_PORT_CL1CM_DW5);
2550 val |= SUS_CLOCK_CONFIG;
2551 I915_WRITE(CNL_PORT_CL1CM_DW5, val);
2552
2553 /* 4. Clear training enable to change swing values */
2554 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2555 val &= ~TX_TRAINING_EN;
2556 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2557
2558 /* 5. Program swing and de-emphasis */
2559 cnl_ddi_vswing_program(encoder, level, type);
2560
2561 /* 6. Set training enable to trigger update */
2562 val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
2563 val |= TX_TRAINING_EN;
2564 I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
2565 }
2566
icl_ddi_combo_vswing_program(struct drm_i915_private * dev_priv,u32 level,enum phy phy,int type,int rate)2567 static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2568 u32 level, enum phy phy, int type,
2569 int rate)
2570 {
2571 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2572 u32 n_entries, val;
2573 int ln;
2574
2575 ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2576 &n_entries);
2577 if (!ddi_translations)
2578 return;
2579
2580 if (level >= n_entries) {
2581 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
2582 level = n_entries - 1;
2583 }
2584
2585 /* Set PORT_TX_DW5 */
2586 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2587 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2588 TAP2_DISABLE | TAP3_DISABLE);
2589 val |= SCALING_MODE_SEL(0x2);
2590 val |= RTERM_SELECT(0x6);
2591 val |= TAP3_DISABLE;
2592 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2593
2594 /* Program PORT_TX_DW2 */
2595 val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2596 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2597 RCOMP_SCALAR_MASK);
2598 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2599 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2600 /* Program Rcomp scalar for every table entry */
2601 val |= RCOMP_SCALAR(0x98);
2602 I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2603
2604 /* Program PORT_TX_DW4 */
2605 /* We cannot write to GRP. It would overwrite individual loadgen. */
2606 for (ln = 0; ln <= 3; ln++) {
2607 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2608 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2609 CURSOR_COEFF_MASK);
2610 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2611 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2612 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2613 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2614 }
2615
2616 /* Program PORT_TX_DW7 */
2617 val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2618 val &= ~N_SCALAR_MASK;
2619 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2620 I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2621 }
2622
icl_combo_phy_ddi_vswing_sequence(struct intel_encoder * encoder,u32 level,enum intel_output_type type)2623 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2624 u32 level,
2625 enum intel_output_type type)
2626 {
2627 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2628 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2629 int width = 0;
2630 int rate = 0;
2631 u32 val;
2632 int ln = 0;
2633
2634 if (type == INTEL_OUTPUT_HDMI) {
2635 width = 4;
2636 /* Rate is always < than 6GHz for HDMI */
2637 } else {
2638 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2639
2640 width = intel_dp->lane_count;
2641 rate = intel_dp->link_rate;
2642 }
2643
2644 /*
2645 * 1. If port type is eDP or DP,
2646 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2647 * else clear to 0b.
2648 */
2649 val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2650 if (type == INTEL_OUTPUT_HDMI)
2651 val &= ~COMMON_KEEPER_EN;
2652 else
2653 val |= COMMON_KEEPER_EN;
2654 I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2655
2656 /* 2. Program loadgen select */
2657 /*
2658 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2659 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2660 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2661 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2662 */
2663 for (ln = 0; ln <= 3; ln++) {
2664 val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2665 val &= ~LOADGEN_SELECT;
2666
2667 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2668 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2669 val |= LOADGEN_SELECT;
2670 }
2671 I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2672 }
2673
2674 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2675 val = I915_READ(ICL_PORT_CL_DW5(phy));
2676 val |= SUS_CLOCK_CONFIG;
2677 I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2678
2679 /* 4. Clear training enable to change swing values */
2680 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2681 val &= ~TX_TRAINING_EN;
2682 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2683
2684 /* 5. Program swing and de-emphasis */
2685 icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2686
2687 /* 6. Set training enable to trigger update */
2688 val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2689 val |= TX_TRAINING_EN;
2690 I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2691 }
2692
icl_mg_phy_ddi_vswing_sequence(struct intel_encoder * encoder,int link_clock,u32 level)2693 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2694 int link_clock,
2695 u32 level)
2696 {
2697 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2698 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2699 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2700 u32 n_entries, val;
2701 int ln;
2702
2703 n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
2704 ddi_translations = icl_mg_phy_ddi_translations;
2705 /* The table does not have values for level 3 and level 9. */
2706 if (level >= n_entries || level == 3 || level == 9) {
2707 DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.",
2708 level, n_entries - 2);
2709 level = n_entries - 2;
2710 }
2711
2712 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2713 for (ln = 0; ln < 2; ln++) {
2714 val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port));
2715 val &= ~CRI_USE_FS32;
2716 I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val);
2717
2718 val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port));
2719 val &= ~CRI_USE_FS32;
2720 I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val);
2721 }
2722
2723 /* Program MG_TX_SWINGCTRL with values from vswing table */
2724 for (ln = 0; ln < 2; ln++) {
2725 val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port));
2726 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2727 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2728 ddi_translations[level].cri_txdeemph_override_17_12);
2729 I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val);
2730
2731 val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port));
2732 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2733 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2734 ddi_translations[level].cri_txdeemph_override_17_12);
2735 I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val);
2736 }
2737
2738 /* Program MG_TX_DRVCTRL with values from vswing table */
2739 for (ln = 0; ln < 2; ln++) {
2740 val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port));
2741 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2742 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2743 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2744 ddi_translations[level].cri_txdeemph_override_5_0) |
2745 CRI_TXDEEMPH_OVERRIDE_11_6(
2746 ddi_translations[level].cri_txdeemph_override_11_6) |
2747 CRI_TXDEEMPH_OVERRIDE_EN;
2748 I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val);
2749
2750 val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port));
2751 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2752 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2753 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2754 ddi_translations[level].cri_txdeemph_override_5_0) |
2755 CRI_TXDEEMPH_OVERRIDE_11_6(
2756 ddi_translations[level].cri_txdeemph_override_11_6) |
2757 CRI_TXDEEMPH_OVERRIDE_EN;
2758 I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val);
2759
2760 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2761 }
2762
2763 /*
2764 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2765 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2766 * values from table for which TX1 and TX2 enabled.
2767 */
2768 for (ln = 0; ln < 2; ln++) {
2769 val = I915_READ(MG_CLKHUB(ln, tc_port));
2770 if (link_clock < 300000)
2771 val |= CFG_LOW_RATE_LKREN_EN;
2772 else
2773 val &= ~CFG_LOW_RATE_LKREN_EN;
2774 I915_WRITE(MG_CLKHUB(ln, tc_port), val);
2775 }
2776
2777 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2778 for (ln = 0; ln < 2; ln++) {
2779 val = I915_READ(MG_TX1_DCC(ln, tc_port));
2780 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2781 if (link_clock <= 500000) {
2782 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2783 } else {
2784 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2785 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2786 }
2787 I915_WRITE(MG_TX1_DCC(ln, tc_port), val);
2788
2789 val = I915_READ(MG_TX2_DCC(ln, tc_port));
2790 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2791 if (link_clock <= 500000) {
2792 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2793 } else {
2794 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2795 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2796 }
2797 I915_WRITE(MG_TX2_DCC(ln, tc_port), val);
2798 }
2799
2800 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2801 for (ln = 0; ln < 2; ln++) {
2802 val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port));
2803 val |= CRI_CALCINIT;
2804 I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val);
2805
2806 val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port));
2807 val |= CRI_CALCINIT;
2808 I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val);
2809 }
2810 }
2811
icl_ddi_vswing_sequence(struct intel_encoder * encoder,int link_clock,u32 level,enum intel_output_type type)2812 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2813 int link_clock,
2814 u32 level,
2815 enum intel_output_type type)
2816 {
2817 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2818 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2819
2820 if (intel_phy_is_combo(dev_priv, phy))
2821 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2822 else
2823 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
2824 }
2825
2826 static void
tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder * encoder,int link_clock,u32 level)2827 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2828 u32 level)
2829 {
2830 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2831 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2832 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2833 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2834
2835 if (encoder->type == INTEL_OUTPUT_HDMI) {
2836 n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
2837 ddi_translations = tgl_dkl_phy_hdmi_ddi_trans;
2838 } else {
2839 n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
2840 ddi_translations = tgl_dkl_phy_dp_ddi_trans;
2841 }
2842
2843 if (level >= n_entries)
2844 level = n_entries - 1;
2845
2846 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2847 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2848 DKL_TX_VSWING_CONTROL_MASK);
2849 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2850 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2851 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2852
2853 for (ln = 0; ln < 2; ln++) {
2854 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
2855
2856 I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0);
2857
2858 /* All the registers are RMW */
2859 val = I915_READ(DKL_TX_DPCNTL0(tc_port));
2860 val &= ~dpcnt_mask;
2861 val |= dpcnt_val;
2862 I915_WRITE(DKL_TX_DPCNTL0(tc_port), val);
2863
2864 val = I915_READ(DKL_TX_DPCNTL1(tc_port));
2865 val &= ~dpcnt_mask;
2866 val |= dpcnt_val;
2867 I915_WRITE(DKL_TX_DPCNTL1(tc_port), val);
2868
2869 val = I915_READ(DKL_TX_DPCNTL2(tc_port));
2870 val &= ~DKL_TX_DP20BITMODE;
2871 I915_WRITE(DKL_TX_DPCNTL2(tc_port), val);
2872 }
2873 }
2874
tgl_ddi_vswing_sequence(struct intel_encoder * encoder,int link_clock,u32 level,enum intel_output_type type)2875 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2876 int link_clock,
2877 u32 level,
2878 enum intel_output_type type)
2879 {
2880 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2881 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2882
2883 if (intel_phy_is_combo(dev_priv, phy))
2884 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2885 else
2886 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level);
2887 }
2888
translate_signal_level(int signal_levels)2889 static u32 translate_signal_level(int signal_levels)
2890 {
2891 int i;
2892
2893 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2894 if (index_to_dp_signal_levels[i] == signal_levels)
2895 return i;
2896 }
2897
2898 WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2899 signal_levels);
2900
2901 return 0;
2902 }
2903
intel_ddi_dp_level(struct intel_dp * intel_dp)2904 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2905 {
2906 u8 train_set = intel_dp->train_set[0];
2907 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2908 DP_TRAIN_PRE_EMPHASIS_MASK);
2909
2910 return translate_signal_level(signal_levels);
2911 }
2912
bxt_signal_levels(struct intel_dp * intel_dp)2913 u32 bxt_signal_levels(struct intel_dp *intel_dp)
2914 {
2915 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2916 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2917 struct intel_encoder *encoder = &dport->base;
2918 int level = intel_ddi_dp_level(intel_dp);
2919
2920 if (INTEL_GEN(dev_priv) >= 12)
2921 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2922 level, encoder->type);
2923 else if (INTEL_GEN(dev_priv) >= 11)
2924 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2925 level, encoder->type);
2926 else if (IS_CANNONLAKE(dev_priv))
2927 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2928 else
2929 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2930
2931 return 0;
2932 }
2933
ddi_signal_levels(struct intel_dp * intel_dp)2934 u32 ddi_signal_levels(struct intel_dp *intel_dp)
2935 {
2936 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2937 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2938 struct intel_encoder *encoder = &dport->base;
2939 int level = intel_ddi_dp_level(intel_dp);
2940
2941 if (IS_GEN9_BC(dev_priv))
2942 skl_ddi_set_iboost(encoder, level, encoder->type);
2943
2944 return DDI_BUF_TRANS_SELECT(level);
2945 }
2946
2947 static inline
icl_dpclka_cfgcr0_clk_off(struct drm_i915_private * dev_priv,enum phy phy)2948 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2949 enum phy phy)
2950 {
2951 if (intel_phy_is_combo(dev_priv, phy)) {
2952 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2953 } else if (intel_phy_is_tc(dev_priv, phy)) {
2954 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2955 (enum port)phy);
2956
2957 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2958 }
2959
2960 return 0;
2961 }
2962
icl_map_plls_to_ports(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2963 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2964 const struct intel_crtc_state *crtc_state)
2965 {
2966 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2967 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2968 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2969 u32 val;
2970
2971 mutex_lock(&dev_priv->dpll_lock);
2972
2973 val = I915_READ(ICL_DPCLKA_CFGCR0);
2974 WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2975
2976 if (intel_phy_is_combo(dev_priv, phy)) {
2977 /*
2978 * Even though this register references DDIs, note that we
2979 * want to pass the PHY rather than the port (DDI). For
2980 * ICL, port=phy in all cases so it doesn't matter, but for
2981 * EHL the bspec notes the following:
2982 *
2983 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2984 * Clock Select chooses the PLL for both DDIA and DDID and
2985 * drives port A in all cases."
2986 */
2987 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2988 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2989 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2990 POSTING_READ(ICL_DPCLKA_CFGCR0);
2991 }
2992
2993 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2994 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2995
2996 mutex_unlock(&dev_priv->dpll_lock);
2997 }
2998
icl_unmap_plls_to_ports(struct intel_encoder * encoder)2999 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
3000 {
3001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3002 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3003 u32 val;
3004
3005 mutex_lock(&dev_priv->dpll_lock);
3006
3007 val = I915_READ(ICL_DPCLKA_CFGCR0);
3008 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3009 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
3010
3011 mutex_unlock(&dev_priv->dpll_lock);
3012 }
3013
icl_sanitize_port_clk_off(struct drm_i915_private * dev_priv,u32 port_mask,bool ddi_clk_needed)3014 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
3015 u32 port_mask, bool ddi_clk_needed)
3016 {
3017 enum port port;
3018 u32 val;
3019
3020 val = I915_READ(ICL_DPCLKA_CFGCR0);
3021 for_each_port_masked(port, port_mask) {
3022 enum phy phy = intel_port_to_phy(dev_priv, port);
3023 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
3024 phy);
3025
3026 if (ddi_clk_needed == !ddi_clk_off)
3027 continue;
3028
3029 /*
3030 * Punt on the case now where clock is gated, but it would
3031 * be needed by the port. Something else is really broken then.
3032 */
3033 if (WARN_ON(ddi_clk_needed))
3034 continue;
3035
3036 DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
3037 phy_name(phy));
3038 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
3039 I915_WRITE(ICL_DPCLKA_CFGCR0, val);
3040 }
3041 }
3042
icl_sanitize_encoder_pll_mapping(struct intel_encoder * encoder)3043 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
3044 {
3045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3046 u32 port_mask;
3047 bool ddi_clk_needed;
3048
3049 /*
3050 * In case of DP MST, we sanitize the primary encoder only, not the
3051 * virtual ones.
3052 */
3053 if (encoder->type == INTEL_OUTPUT_DP_MST)
3054 return;
3055
3056 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3057 u8 pipe_mask;
3058 bool is_mst;
3059
3060 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3061 /*
3062 * In the unlikely case that BIOS enables DP in MST mode, just
3063 * warn since our MST HW readout is incomplete.
3064 */
3065 if (WARN_ON(is_mst))
3066 return;
3067 }
3068
3069 port_mask = BIT(encoder->port);
3070 ddi_clk_needed = encoder->base.crtc;
3071
3072 if (encoder->type == INTEL_OUTPUT_DSI) {
3073 struct intel_encoder *other_encoder;
3074
3075 port_mask = intel_dsi_encoder_ports(encoder);
3076 /*
3077 * Sanity check that we haven't incorrectly registered another
3078 * encoder using any of the ports of this DSI encoder.
3079 */
3080 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3081 if (other_encoder == encoder)
3082 continue;
3083
3084 if (WARN_ON(port_mask & BIT(other_encoder->port)))
3085 return;
3086 }
3087 /*
3088 * For DSI we keep the ddi clocks gated
3089 * except during enable/disable sequence.
3090 */
3091 ddi_clk_needed = false;
3092 }
3093
3094 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
3095 }
3096
intel_ddi_clk_select(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3097 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3098 const struct intel_crtc_state *crtc_state)
3099 {
3100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3101 enum port port = encoder->port;
3102 enum phy phy = intel_port_to_phy(dev_priv, port);
3103 u32 val;
3104 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3105
3106 if (WARN_ON(!pll))
3107 return;
3108
3109 mutex_lock(&dev_priv->dpll_lock);
3110
3111 if (INTEL_GEN(dev_priv) >= 11) {
3112 if (!intel_phy_is_combo(dev_priv, phy))
3113 I915_WRITE(DDI_CLK_SEL(port),
3114 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3115 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3116 /*
3117 * MG does not exist but the programming is required
3118 * to ungate DDIC and DDID
3119 */
3120 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
3121 } else if (IS_CANNONLAKE(dev_priv)) {
3122 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3123 val = I915_READ(DPCLKA_CFGCR0);
3124 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3125 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3126 I915_WRITE(DPCLKA_CFGCR0, val);
3127
3128 /*
3129 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3130 * This step and the step before must be done with separate
3131 * register writes.
3132 */
3133 val = I915_READ(DPCLKA_CFGCR0);
3134 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3135 I915_WRITE(DPCLKA_CFGCR0, val);
3136 } else if (IS_GEN9_BC(dev_priv)) {
3137 /* DDI -> PLL mapping */
3138 val = I915_READ(DPLL_CTRL2);
3139
3140 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3141 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3142 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3143 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3144
3145 I915_WRITE(DPLL_CTRL2, val);
3146
3147 } else if (INTEL_GEN(dev_priv) < 9) {
3148 I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
3149 }
3150
3151 mutex_unlock(&dev_priv->dpll_lock);
3152 }
3153
intel_ddi_clk_disable(struct intel_encoder * encoder)3154 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3155 {
3156 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3157 enum port port = encoder->port;
3158 enum phy phy = intel_port_to_phy(dev_priv, port);
3159
3160 if (INTEL_GEN(dev_priv) >= 11) {
3161 if (!intel_phy_is_combo(dev_priv, phy) ||
3162 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3163 I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
3164 } else if (IS_CANNONLAKE(dev_priv)) {
3165 I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
3166 DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3167 } else if (IS_GEN9_BC(dev_priv)) {
3168 I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
3169 DPLL_CTRL2_DDI_CLK_OFF(port));
3170 } else if (INTEL_GEN(dev_priv) < 9) {
3171 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
3172 }
3173 }
3174
3175 static void
icl_program_mg_dp_mode(struct intel_digital_port * intel_dig_port,const struct intel_crtc_state * crtc_state)3176 icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port,
3177 const struct intel_crtc_state *crtc_state)
3178 {
3179 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3180 enum tc_port tc_port = intel_port_to_tc(dev_priv, intel_dig_port->base.port);
3181 u32 ln0, ln1, pin_assignment;
3182 u8 width;
3183
3184 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3185 return;
3186
3187 if (INTEL_GEN(dev_priv) >= 12) {
3188 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3189 ln0 = I915_READ(DKL_DP_MODE(tc_port));
3190 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3191 ln1 = I915_READ(DKL_DP_MODE(tc_port));
3192 } else {
3193 ln0 = I915_READ(MG_DP_MODE(0, tc_port));
3194 ln1 = I915_READ(MG_DP_MODE(1, tc_port));
3195 }
3196
3197 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE);
3198 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3199
3200 /* DPPATC */
3201 pin_assignment = intel_tc_port_get_pin_assignment_mask(intel_dig_port);
3202 width = crtc_state->lane_count;
3203
3204 switch (pin_assignment) {
3205 case 0x0:
3206 WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY);
3207 if (width == 1) {
3208 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3209 } else {
3210 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3211 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3212 }
3213 break;
3214 case 0x1:
3215 if (width == 4) {
3216 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3217 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3218 }
3219 break;
3220 case 0x2:
3221 if (width == 2) {
3222 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3223 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3224 }
3225 break;
3226 case 0x3:
3227 case 0x5:
3228 if (width == 1) {
3229 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3230 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3231 } else {
3232 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3233 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3234 }
3235 break;
3236 case 0x4:
3237 case 0x6:
3238 if (width == 1) {
3239 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3240 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3241 } else {
3242 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3243 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3244 }
3245 break;
3246 default:
3247 MISSING_CASE(pin_assignment);
3248 }
3249
3250 if (INTEL_GEN(dev_priv) >= 12) {
3251 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0));
3252 I915_WRITE(DKL_DP_MODE(tc_port), ln0);
3253 I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1));
3254 I915_WRITE(DKL_DP_MODE(tc_port), ln1);
3255 } else {
3256 I915_WRITE(MG_DP_MODE(0, tc_port), ln0);
3257 I915_WRITE(MG_DP_MODE(1, tc_port), ln1);
3258 }
3259 }
3260
intel_dp_sink_set_fec_ready(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3261 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3262 const struct intel_crtc_state *crtc_state)
3263 {
3264 if (!crtc_state->fec_enable)
3265 return;
3266
3267 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3268 DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n");
3269 }
3270
intel_ddi_enable_fec(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3271 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3272 const struct intel_crtc_state *crtc_state)
3273 {
3274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3275 struct intel_dp *intel_dp;
3276 u32 val;
3277
3278 if (!crtc_state->fec_enable)
3279 return;
3280
3281 intel_dp = enc_to_intel_dp(encoder);
3282 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3283 val |= DP_TP_CTL_FEC_ENABLE;
3284 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3285
3286 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3287 DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3288 DRM_ERROR("Timed out waiting for FEC Enable Status\n");
3289 }
3290
intel_ddi_disable_fec_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3291 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3292 const struct intel_crtc_state *crtc_state)
3293 {
3294 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3295 struct intel_dp *intel_dp;
3296 u32 val;
3297
3298 if (!crtc_state->fec_enable)
3299 return;
3300
3301 intel_dp = enc_to_intel_dp(encoder);
3302 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3303 val &= ~DP_TP_CTL_FEC_ENABLE;
3304 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3305 POSTING_READ(intel_dp->regs.dp_tp_ctl);
3306 }
3307
3308 static void
tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state * cstate)3309 tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3310 {
3311 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
3312 u32 val;
3313
3314 if (!cstate->dc3co_exitline)
3315 return;
3316
3317 val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3318 val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3319 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3320 }
3321
3322 static void
tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state * cstate)3323 tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
3324 {
3325 u32 val, exit_scanlines;
3326 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
3327
3328 if (!cstate->dc3co_exitline)
3329 return;
3330
3331 exit_scanlines = cstate->dc3co_exitline;
3332 exit_scanlines <<= EXITLINE_SHIFT;
3333 val = I915_READ(EXITLINE(cstate->cpu_transcoder));
3334 val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
3335 val |= exit_scanlines;
3336 val |= EXITLINE_ENABLE;
3337 I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
3338 }
3339
tgl_dc3co_exitline_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * cstate)3340 static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
3341 struct intel_crtc_state *cstate)
3342 {
3343 u32 exit_scanlines;
3344 struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev);
3345 u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay;
3346
3347 cstate->dc3co_exitline = 0;
3348
3349 if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
3350 return;
3351
3352 /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
3353 if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A ||
3354 encoder->port != PORT_A)
3355 return;
3356
3357 if (!cstate->has_psr2 || !cstate->hw.active)
3358 return;
3359
3360 /*
3361 * DC3CO Exit time 200us B.Spec 49196
3362 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
3363 */
3364 exit_scanlines =
3365 intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1;
3366
3367 if (WARN_ON(exit_scanlines > crtc_vdisplay))
3368 return;
3369
3370 cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines;
3371 DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline);
3372 }
3373
tgl_dc3co_exitline_get_config(struct intel_crtc_state * crtc_state)3374 static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
3375 {
3376 u32 val;
3377 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3378
3379 if (INTEL_GEN(dev_priv) < 12)
3380 return;
3381
3382 val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
3383
3384 if (val & EXITLINE_ENABLE)
3385 crtc_state->dc3co_exitline = val & EXITLINE_MASK;
3386 }
3387
tgl_ddi_pre_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3388 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
3389 const struct intel_crtc_state *crtc_state,
3390 const struct drm_connector_state *conn_state)
3391 {
3392 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3393 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3394 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3395 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3396 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3397 int level = intel_ddi_dp_level(intel_dp);
3398 enum transcoder transcoder = crtc_state->cpu_transcoder;
3399
3400 tgl_set_psr2_transcoder_exitline(crtc_state);
3401 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3402 crtc_state->lane_count, is_mst);
3403
3404 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3405 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3406
3407 /*
3408 * 1. Enable Power Wells
3409 *
3410 * This was handled at the beginning of intel_atomic_commit_tail(),
3411 * before we called down into this function.
3412 */
3413
3414 /* 2. Enable Panel Power if PPS is required */
3415 intel_edp_panel_on(intel_dp);
3416
3417 /*
3418 * 3. For non-TBT Type-C ports, set FIA lane count
3419 * (DFLEXDPSP.DPX4TXLATC)
3420 *
3421 * This was done before tgl_ddi_pre_enable_dp by
3422 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3423 */
3424
3425 /*
3426 * 4. Enable the port PLL.
3427 *
3428 * The PLL enabling itself was already done before this function by
3429 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
3430 * configure the PLL to port mapping here.
3431 */
3432 intel_ddi_clk_select(encoder, crtc_state);
3433
3434 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3435 if (!intel_phy_is_tc(dev_priv, phy) ||
3436 dig_port->tc_mode != TC_PORT_TBT_ALT)
3437 intel_display_power_get(dev_priv,
3438 dig_port->ddi_io_power_domain);
3439
3440 /* 6. Program DP_MODE */
3441 icl_program_mg_dp_mode(dig_port, crtc_state);
3442
3443 /*
3444 * 7. The rest of the below are substeps under the bspec's "Enable and
3445 * Train Display Port" step. Note that steps that are specific to
3446 * MST will be handled by intel_mst_pre_enable_dp() before/after it
3447 * calls into this function. Also intel_mst_pre_enable_dp() only calls
3448 * us when active_mst_links==0, so any steps designated for "single
3449 * stream or multi-stream master transcoder" can just be performed
3450 * unconditionally here.
3451 */
3452
3453 /*
3454 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3455 * Transcoder.
3456 */
3457 intel_ddi_enable_pipe_clock(crtc_state);
3458
3459 /*
3460 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3461 * Transport Select
3462 */
3463 intel_ddi_config_transcoder_func(crtc_state);
3464
3465 /*
3466 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3467 * selected
3468 *
3469 * This will be handled by the intel_dp_start_link_train() farther
3470 * down this function.
3471 */
3472
3473 /* 7.e Configure voltage swing and related IO settings */
3474 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3475 encoder->type);
3476
3477 /*
3478 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3479 * the used lanes of the DDI.
3480 */
3481 if (intel_phy_is_combo(dev_priv, phy)) {
3482 bool lane_reversal =
3483 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3484
3485 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3486 crtc_state->lane_count,
3487 lane_reversal);
3488 }
3489
3490 /*
3491 * 7.g Configure and enable DDI_BUF_CTL
3492 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3493 * after 500 us.
3494 *
3495 * We only configure what the register value will be here. Actual
3496 * enabling happens during link training farther down.
3497 */
3498 intel_ddi_init_dp_buf_reg(encoder);
3499
3500 if (!is_mst)
3501 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3502
3503 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3504 /*
3505 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3506 * in the FEC_CONFIGURATION register to 1 before initiating link
3507 * training
3508 */
3509 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3510
3511 /*
3512 * 7.i Follow DisplayPort specification training sequence (see notes for
3513 * failure handling)
3514 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3515 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3516 * (timeout after 800 us)
3517 */
3518 intel_dp_start_link_train(intel_dp);
3519
3520 /* 7.k Set DP_TP_CTL link training to Normal */
3521 if (!is_trans_port_sync_mode(crtc_state))
3522 intel_dp_stop_link_train(intel_dp);
3523
3524 /* 7.l Configure and enable FEC if needed */
3525 intel_ddi_enable_fec(encoder, crtc_state);
3526 intel_dsc_enable(encoder, crtc_state);
3527 }
3528
hsw_ddi_pre_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3529 static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
3530 const struct intel_crtc_state *crtc_state,
3531 const struct drm_connector_state *conn_state)
3532 {
3533 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3534 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3535 enum port port = encoder->port;
3536 enum phy phy = intel_port_to_phy(dev_priv, port);
3537 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3538 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3539 int level = intel_ddi_dp_level(intel_dp);
3540
3541 if (INTEL_GEN(dev_priv) < 11)
3542 WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
3543 else
3544 WARN_ON(is_mst && port == PORT_A);
3545
3546 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3547 crtc_state->lane_count, is_mst);
3548
3549 intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
3550 intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
3551
3552 intel_edp_panel_on(intel_dp);
3553
3554 intel_ddi_clk_select(encoder, crtc_state);
3555
3556 if (!intel_phy_is_tc(dev_priv, phy) ||
3557 dig_port->tc_mode != TC_PORT_TBT_ALT)
3558 intel_display_power_get(dev_priv,
3559 dig_port->ddi_io_power_domain);
3560
3561 icl_program_mg_dp_mode(dig_port, crtc_state);
3562
3563 if (INTEL_GEN(dev_priv) >= 11)
3564 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3565 level, encoder->type);
3566 else if (IS_CANNONLAKE(dev_priv))
3567 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3568 else if (IS_GEN9_LP(dev_priv))
3569 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3570 else
3571 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3572
3573 if (intel_phy_is_combo(dev_priv, phy)) {
3574 bool lane_reversal =
3575 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3576
3577 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3578 crtc_state->lane_count,
3579 lane_reversal);
3580 }
3581
3582 intel_ddi_init_dp_buf_reg(encoder);
3583 if (!is_mst)
3584 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3585 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3586 true);
3587 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3588 intel_dp_start_link_train(intel_dp);
3589 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3590 !is_trans_port_sync_mode(crtc_state))
3591 intel_dp_stop_link_train(intel_dp);
3592
3593 intel_ddi_enable_fec(encoder, crtc_state);
3594
3595 if (!is_mst)
3596 intel_ddi_enable_pipe_clock(crtc_state);
3597
3598 intel_dsc_enable(encoder, crtc_state);
3599 }
3600
intel_ddi_pre_enable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3601 static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
3602 const struct intel_crtc_state *crtc_state,
3603 const struct drm_connector_state *conn_state)
3604 {
3605 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3606
3607 if (INTEL_GEN(dev_priv) >= 12)
3608 tgl_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3609 else
3610 hsw_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3611
3612 /* MST will call a setting of MSA after an allocating of Virtual Channel
3613 * from MST encoder pre_enable callback.
3614 */
3615 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
3616 intel_ddi_set_dp_msa(crtc_state, conn_state);
3617 }
3618
intel_ddi_pre_enable_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3619 static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
3620 const struct intel_crtc_state *crtc_state,
3621 const struct drm_connector_state *conn_state)
3622 {
3623 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3624 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3625 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3626 enum port port = encoder->port;
3627 int level = intel_ddi_hdmi_level(dev_priv, port);
3628 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3629
3630 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3631 intel_ddi_clk_select(encoder, crtc_state);
3632
3633 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3634
3635 icl_program_mg_dp_mode(dig_port, crtc_state);
3636
3637 if (INTEL_GEN(dev_priv) >= 12)
3638 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3639 level, INTEL_OUTPUT_HDMI);
3640 else if (INTEL_GEN(dev_priv) == 11)
3641 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3642 level, INTEL_OUTPUT_HDMI);
3643 else if (IS_CANNONLAKE(dev_priv))
3644 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3645 else if (IS_GEN9_LP(dev_priv))
3646 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3647 else
3648 intel_prepare_hdmi_ddi_buffers(encoder, level);
3649
3650 if (IS_GEN9_BC(dev_priv))
3651 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3652
3653 intel_ddi_enable_pipe_clock(crtc_state);
3654
3655 intel_dig_port->set_infoframes(encoder,
3656 crtc_state->has_infoframe,
3657 crtc_state, conn_state);
3658 }
3659
intel_ddi_pre_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3660 static void intel_ddi_pre_enable(struct intel_encoder *encoder,
3661 const struct intel_crtc_state *crtc_state,
3662 const struct drm_connector_state *conn_state)
3663 {
3664 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3665 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3666 enum pipe pipe = crtc->pipe;
3667
3668 /*
3669 * When called from DP MST code:
3670 * - conn_state will be NULL
3671 * - encoder will be the main encoder (ie. mst->primary)
3672 * - the main connector associated with this port
3673 * won't be active or linked to a crtc
3674 * - crtc_state will be the state of the first stream to
3675 * be activated on this port, and it may not be the same
3676 * stream that will be deactivated last, but each stream
3677 * should have a state that is identical when it comes to
3678 * the DP link parameteres
3679 */
3680
3681 WARN_ON(crtc_state->has_pch_encoder);
3682
3683 if (INTEL_GEN(dev_priv) >= 11)
3684 icl_map_plls_to_ports(encoder, crtc_state);
3685
3686 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3687
3688 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3689 intel_ddi_pre_enable_hdmi(encoder, crtc_state, conn_state);
3690 } else {
3691 struct intel_lspcon *lspcon =
3692 enc_to_intel_lspcon(encoder);
3693
3694 intel_ddi_pre_enable_dp(encoder, crtc_state, conn_state);
3695 if (lspcon->active) {
3696 struct intel_digital_port *dig_port =
3697 enc_to_dig_port(encoder);
3698
3699 dig_port->set_infoframes(encoder,
3700 crtc_state->has_infoframe,
3701 crtc_state, conn_state);
3702 }
3703 }
3704 }
3705
intel_disable_ddi_buf(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3706 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3707 const struct intel_crtc_state *crtc_state)
3708 {
3709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3710 enum port port = encoder->port;
3711 bool wait = false;
3712 u32 val;
3713
3714 val = I915_READ(DDI_BUF_CTL(port));
3715 if (val & DDI_BUF_CTL_ENABLE) {
3716 val &= ~DDI_BUF_CTL_ENABLE;
3717 I915_WRITE(DDI_BUF_CTL(port), val);
3718 wait = true;
3719 }
3720
3721 if (intel_crtc_has_dp_encoder(crtc_state)) {
3722 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3723
3724 val = I915_READ(intel_dp->regs.dp_tp_ctl);
3725 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3726 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3727 I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
3728 }
3729
3730 /* Disable FEC in DP Sink */
3731 intel_ddi_disable_fec_state(encoder, crtc_state);
3732
3733 if (wait)
3734 intel_wait_ddi_buf_idle(dev_priv, port);
3735 }
3736
intel_ddi_post_disable_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3737 static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
3738 const struct intel_crtc_state *old_crtc_state,
3739 const struct drm_connector_state *old_conn_state)
3740 {
3741 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3742 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3743 struct intel_dp *intel_dp = &dig_port->dp;
3744 bool is_mst = intel_crtc_has_type(old_crtc_state,
3745 INTEL_OUTPUT_DP_MST);
3746 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3747
3748 /*
3749 * Power down sink before disabling the port, otherwise we end
3750 * up getting interrupts from the sink on detecting link loss.
3751 */
3752 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3753
3754 if (INTEL_GEN(dev_priv) >= 12) {
3755 if (is_mst) {
3756 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3757 u32 val;
3758
3759 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
3760 val &= ~TGL_TRANS_DDI_PORT_MASK;
3761 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), val);
3762 }
3763 } else {
3764 if (!is_mst)
3765 intel_ddi_disable_pipe_clock(old_crtc_state);
3766 }
3767
3768 intel_disable_ddi_buf(encoder, old_crtc_state);
3769
3770 /*
3771 * From TGL spec: "If single stream or multi-stream master transcoder:
3772 * Configure Transcoder Clock select to direct no clock to the
3773 * transcoder"
3774 */
3775 if (INTEL_GEN(dev_priv) >= 12)
3776 intel_ddi_disable_pipe_clock(old_crtc_state);
3777
3778 intel_edp_panel_vdd_on(intel_dp);
3779 intel_edp_panel_off(intel_dp);
3780
3781 if (!intel_phy_is_tc(dev_priv, phy) ||
3782 dig_port->tc_mode != TC_PORT_TBT_ALT)
3783 intel_display_power_put_unchecked(dev_priv,
3784 dig_port->ddi_io_power_domain);
3785
3786 intel_ddi_clk_disable(encoder);
3787 tgl_clear_psr2_transcoder_exitline(old_crtc_state);
3788 }
3789
intel_ddi_post_disable_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3790 static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
3791 const struct intel_crtc_state *old_crtc_state,
3792 const struct drm_connector_state *old_conn_state)
3793 {
3794 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3795 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3796 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3797
3798 dig_port->set_infoframes(encoder, false,
3799 old_crtc_state, old_conn_state);
3800
3801 intel_ddi_disable_pipe_clock(old_crtc_state);
3802
3803 intel_disable_ddi_buf(encoder, old_crtc_state);
3804
3805 intel_display_power_put_unchecked(dev_priv,
3806 dig_port->ddi_io_power_domain);
3807
3808 intel_ddi_clk_disable(encoder);
3809
3810 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3811 }
3812
icl_disable_transcoder_port_sync(const struct intel_crtc_state * old_crtc_state)3813 static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_crtc_state)
3814 {
3815 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3816 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3817
3818 if (old_crtc_state->master_transcoder == INVALID_TRANSCODER)
3819 return;
3820
3821 DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n",
3822 transcoder_name(old_crtc_state->cpu_transcoder));
3823
3824 I915_WRITE(TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0);
3825 }
3826
intel_ddi_post_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3827 static void intel_ddi_post_disable(struct intel_encoder *encoder,
3828 const struct intel_crtc_state *old_crtc_state,
3829 const struct drm_connector_state *old_conn_state)
3830 {
3831 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3832 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3833 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3834 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3835
3836 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3837 intel_crtc_vblank_off(old_crtc_state);
3838
3839 intel_disable_pipe(old_crtc_state);
3840
3841 if (INTEL_GEN(dev_priv) >= 11)
3842 icl_disable_transcoder_port_sync(old_crtc_state);
3843
3844 intel_ddi_disable_transcoder_func(old_crtc_state);
3845
3846 intel_dsc_disable(old_crtc_state);
3847
3848 if (INTEL_GEN(dev_priv) >= 9)
3849 skl_scaler_disable(old_crtc_state);
3850 else
3851 ilk_pfit_disable(old_crtc_state);
3852 }
3853
3854 /*
3855 * When called from DP MST code:
3856 * - old_conn_state will be NULL
3857 * - encoder will be the main encoder (ie. mst->primary)
3858 * - the main connector associated with this port
3859 * won't be active or linked to a crtc
3860 * - old_crtc_state will be the state of the last stream to
3861 * be deactivated on this port, and it may not be the same
3862 * stream that was activated last, but each stream
3863 * should have a state that is identical when it comes to
3864 * the DP link parameteres
3865 */
3866
3867 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3868 intel_ddi_post_disable_hdmi(encoder,
3869 old_crtc_state, old_conn_state);
3870 else
3871 intel_ddi_post_disable_dp(encoder,
3872 old_crtc_state, old_conn_state);
3873
3874 if (INTEL_GEN(dev_priv) >= 11)
3875 icl_unmap_plls_to_ports(encoder);
3876
3877 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3878 intel_display_power_put_unchecked(dev_priv,
3879 intel_ddi_main_link_aux_domain(dig_port));
3880
3881 if (is_tc_port)
3882 intel_tc_port_put_link(dig_port);
3883 }
3884
intel_ddi_fdi_post_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3885 void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
3886 const struct intel_crtc_state *old_crtc_state,
3887 const struct drm_connector_state *old_conn_state)
3888 {
3889 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3890 u32 val;
3891
3892 /*
3893 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3894 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3895 * step 13 is the correct place for it. Step 18 is where it was
3896 * originally before the BUN.
3897 */
3898 val = I915_READ(FDI_RX_CTL(PIPE_A));
3899 val &= ~FDI_RX_ENABLE;
3900 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3901
3902 intel_disable_ddi_buf(encoder, old_crtc_state);
3903 intel_ddi_clk_disable(encoder);
3904
3905 val = I915_READ(FDI_RX_MISC(PIPE_A));
3906 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3907 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3908 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
3909
3910 val = I915_READ(FDI_RX_CTL(PIPE_A));
3911 val &= ~FDI_PCDCLK;
3912 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3913
3914 val = I915_READ(FDI_RX_CTL(PIPE_A));
3915 val &= ~FDI_RX_PLL_ENABLE;
3916 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3917 }
3918
intel_enable_ddi_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3919 static void intel_enable_ddi_dp(struct intel_encoder *encoder,
3920 const struct intel_crtc_state *crtc_state,
3921 const struct drm_connector_state *conn_state)
3922 {
3923 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3924 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3925 enum port port = encoder->port;
3926
3927 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3928 intel_dp_stop_link_train(intel_dp);
3929
3930 intel_edp_backlight_on(crtc_state, conn_state);
3931 intel_psr_enable(intel_dp, crtc_state);
3932 intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
3933 intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
3934 intel_edp_drrs_enable(intel_dp, crtc_state);
3935
3936 if (crtc_state->has_audio)
3937 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3938 }
3939
3940 static i915_reg_t
gen9_chicken_trans_reg_by_port(struct drm_i915_private * dev_priv,enum port port)3941 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3942 enum port port)
3943 {
3944 static const enum transcoder trans[] = {
3945 [PORT_A] = TRANSCODER_EDP,
3946 [PORT_B] = TRANSCODER_A,
3947 [PORT_C] = TRANSCODER_B,
3948 [PORT_D] = TRANSCODER_C,
3949 [PORT_E] = TRANSCODER_A,
3950 };
3951
3952 WARN_ON(INTEL_GEN(dev_priv) < 9);
3953
3954 if (WARN_ON(port < PORT_A || port > PORT_E))
3955 port = PORT_A;
3956
3957 return CHICKEN_TRANS(trans[port]);
3958 }
3959
intel_enable_ddi_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3960 static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
3961 const struct intel_crtc_state *crtc_state,
3962 const struct drm_connector_state *conn_state)
3963 {
3964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3965 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3966 struct drm_connector *connector = conn_state->connector;
3967 enum port port = encoder->port;
3968
3969 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3970 crtc_state->hdmi_high_tmds_clock_ratio,
3971 crtc_state->hdmi_scrambling))
3972 DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3973 connector->base.id, connector->name);
3974
3975 /* Display WA #1143: skl,kbl,cfl */
3976 if (IS_GEN9_BC(dev_priv)) {
3977 /*
3978 * For some reason these chicken bits have been
3979 * stuffed into a transcoder register, event though
3980 * the bits affect a specific DDI port rather than
3981 * a specific transcoder.
3982 */
3983 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3984 u32 val;
3985
3986 val = I915_READ(reg);
3987
3988 if (port == PORT_E)
3989 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3990 DDIE_TRAINING_OVERRIDE_VALUE;
3991 else
3992 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3993 DDI_TRAINING_OVERRIDE_VALUE;
3994
3995 I915_WRITE(reg, val);
3996 POSTING_READ(reg);
3997
3998 udelay(1);
3999
4000 if (port == PORT_E)
4001 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
4002 DDIE_TRAINING_OVERRIDE_VALUE);
4003 else
4004 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
4005 DDI_TRAINING_OVERRIDE_VALUE);
4006
4007 I915_WRITE(reg, val);
4008 }
4009
4010 /* In HDMI/DVI mode, the port width, and swing/emphasis values
4011 * are ignored so nothing special needs to be done besides
4012 * enabling the port.
4013 */
4014 I915_WRITE(DDI_BUF_CTL(port),
4015 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
4016
4017 if (crtc_state->has_audio)
4018 intel_audio_codec_enable(encoder, crtc_state, conn_state);
4019 }
4020
intel_enable_ddi(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4021 static void intel_enable_ddi(struct intel_encoder *encoder,
4022 const struct intel_crtc_state *crtc_state,
4023 const struct drm_connector_state *conn_state)
4024 {
4025 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4026 intel_enable_ddi_hdmi(encoder, crtc_state, conn_state);
4027 else
4028 intel_enable_ddi_dp(encoder, crtc_state, conn_state);
4029
4030 /* Enable hdcp if it's desired */
4031 if (conn_state->content_protection ==
4032 DRM_MODE_CONTENT_PROTECTION_DESIRED)
4033 intel_hdcp_enable(to_intel_connector(conn_state->connector),
4034 crtc_state->cpu_transcoder,
4035 (u8)conn_state->hdcp_content_type);
4036 }
4037
intel_disable_ddi_dp(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)4038 static void intel_disable_ddi_dp(struct intel_encoder *encoder,
4039 const struct intel_crtc_state *old_crtc_state,
4040 const struct drm_connector_state *old_conn_state)
4041 {
4042 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4043
4044 intel_dp->link_trained = false;
4045
4046 if (old_crtc_state->has_audio)
4047 intel_audio_codec_disable(encoder,
4048 old_crtc_state, old_conn_state);
4049
4050 intel_edp_drrs_disable(intel_dp, old_crtc_state);
4051 intel_psr_disable(intel_dp, old_crtc_state);
4052 intel_edp_backlight_off(old_conn_state);
4053 /* Disable the decompression in DP Sink */
4054 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
4055 false);
4056 }
4057
intel_disable_ddi_hdmi(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)4058 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
4059 const struct intel_crtc_state *old_crtc_state,
4060 const struct drm_connector_state *old_conn_state)
4061 {
4062 struct drm_connector *connector = old_conn_state->connector;
4063
4064 if (old_crtc_state->has_audio)
4065 intel_audio_codec_disable(encoder,
4066 old_crtc_state, old_conn_state);
4067
4068 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4069 false, false))
4070 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4071 connector->base.id, connector->name);
4072 }
4073
intel_disable_ddi(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)4074 static void intel_disable_ddi(struct intel_encoder *encoder,
4075 const struct intel_crtc_state *old_crtc_state,
4076 const struct drm_connector_state *old_conn_state)
4077 {
4078 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4079
4080 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4081 intel_disable_ddi_hdmi(encoder, old_crtc_state, old_conn_state);
4082 else
4083 intel_disable_ddi_dp(encoder, old_crtc_state, old_conn_state);
4084 }
4085
intel_ddi_update_pipe_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4086 static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
4087 const struct intel_crtc_state *crtc_state,
4088 const struct drm_connector_state *conn_state)
4089 {
4090 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4091
4092 intel_ddi_set_dp_msa(crtc_state, conn_state);
4093
4094 intel_psr_update(intel_dp, crtc_state);
4095 intel_edp_drrs_enable(intel_dp, crtc_state);
4096
4097 intel_panel_update_backlight(encoder, crtc_state, conn_state);
4098 }
4099
intel_ddi_update_pipe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4100 static void intel_ddi_update_pipe(struct intel_encoder *encoder,
4101 const struct intel_crtc_state *crtc_state,
4102 const struct drm_connector_state *conn_state)
4103 {
4104 struct intel_connector *connector =
4105 to_intel_connector(conn_state->connector);
4106 struct intel_hdcp *hdcp = &connector->hdcp;
4107 bool content_protection_type_changed =
4108 (conn_state->hdcp_content_type != hdcp->content_type &&
4109 conn_state->content_protection !=
4110 DRM_MODE_CONTENT_PROTECTION_UNDESIRED);
4111
4112 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4113 intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state);
4114
4115 /*
4116 * During the HDCP encryption session if Type change is requested,
4117 * disable the HDCP and reenable it with new TYPE value.
4118 */
4119 if (conn_state->content_protection ==
4120 DRM_MODE_CONTENT_PROTECTION_UNDESIRED ||
4121 content_protection_type_changed)
4122 intel_hdcp_disable(connector);
4123
4124 /*
4125 * Mark the hdcp state as DESIRED after the hdcp disable of type
4126 * change procedure.
4127 */
4128 if (content_protection_type_changed) {
4129 mutex_lock(&hdcp->mutex);
4130 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED;
4131 schedule_work(&hdcp->prop_work);
4132 mutex_unlock(&hdcp->mutex);
4133 }
4134
4135 if (conn_state->content_protection ==
4136 DRM_MODE_CONTENT_PROTECTION_DESIRED ||
4137 content_protection_type_changed)
4138 intel_hdcp_enable(connector,
4139 crtc_state->cpu_transcoder,
4140 (u8)conn_state->hdcp_content_type);
4141 }
4142
4143 static void
intel_ddi_update_prepare(struct intel_atomic_state * state,struct intel_encoder * encoder,struct intel_crtc * crtc)4144 intel_ddi_update_prepare(struct intel_atomic_state *state,
4145 struct intel_encoder *encoder,
4146 struct intel_crtc *crtc)
4147 {
4148 struct intel_crtc_state *crtc_state =
4149 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4150 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4151
4152 WARN_ON(crtc && crtc->active);
4153
4154 intel_tc_port_get_link(enc_to_dig_port(encoder),
4155 required_lanes);
4156 if (crtc_state && crtc_state->hw.active)
4157 intel_update_active_dpll(state, crtc, encoder);
4158 }
4159
4160 static void
intel_ddi_update_complete(struct intel_atomic_state * state,struct intel_encoder * encoder,struct intel_crtc * crtc)4161 intel_ddi_update_complete(struct intel_atomic_state *state,
4162 struct intel_encoder *encoder,
4163 struct intel_crtc *crtc)
4164 {
4165 intel_tc_port_put_link(enc_to_dig_port(encoder));
4166 }
4167
4168 static void
intel_ddi_pre_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4169 intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
4170 const struct intel_crtc_state *crtc_state,
4171 const struct drm_connector_state *conn_state)
4172 {
4173 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4174 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4175 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4176 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4177
4178 if (is_tc_port)
4179 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4180
4181 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4182 intel_display_power_get(dev_priv,
4183 intel_ddi_main_link_aux_domain(dig_port));
4184
4185 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4186 /*
4187 * Program the lane count for static/dynamic connections on
4188 * Type-C ports. Skip this step for TBT.
4189 */
4190 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4191 else if (IS_GEN9_LP(dev_priv))
4192 bxt_ddi_phy_set_lane_optim_mask(encoder,
4193 crtc_state->lane_lat_optim_mask);
4194 }
4195
intel_ddi_prepare_link_retrain(struct intel_dp * intel_dp)4196 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4197 {
4198 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4199 struct drm_i915_private *dev_priv =
4200 to_i915(intel_dig_port->base.base.dev);
4201 enum port port = intel_dig_port->base.port;
4202 u32 dp_tp_ctl, ddi_buf_ctl;
4203 bool wait = false;
4204
4205 dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl);
4206
4207 if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4208 ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port));
4209 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4210 I915_WRITE(DDI_BUF_CTL(port),
4211 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
4212 wait = true;
4213 }
4214
4215 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4216 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4217 I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4218 POSTING_READ(intel_dp->regs.dp_tp_ctl);
4219
4220 if (wait)
4221 intel_wait_ddi_buf_idle(dev_priv, port);
4222 }
4223
4224 dp_tp_ctl = DP_TP_CTL_ENABLE |
4225 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
4226 if (intel_dp->link_mst)
4227 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
4228 else {
4229 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
4230 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4231 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4232 }
4233 I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4234 POSTING_READ(intel_dp->regs.dp_tp_ctl);
4235
4236 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4237 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
4238 POSTING_READ(DDI_BUF_CTL(port));
4239
4240 udelay(600);
4241 }
4242
intel_ddi_is_audio_enabled(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)4243 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4244 enum transcoder cpu_transcoder)
4245 {
4246 if (cpu_transcoder == TRANSCODER_EDP)
4247 return false;
4248
4249 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4250 return false;
4251
4252 return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) &
4253 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4254 }
4255
intel_ddi_compute_min_voltage_level(struct drm_i915_private * dev_priv,struct intel_crtc_state * crtc_state)4256 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4257 struct intel_crtc_state *crtc_state)
4258 {
4259 if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
4260 crtc_state->min_voltage_level = 3;
4261 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4262 crtc_state->min_voltage_level = 1;
4263 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4264 crtc_state->min_voltage_level = 2;
4265 }
4266
intel_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)4267 void intel_ddi_get_config(struct intel_encoder *encoder,
4268 struct intel_crtc_state *pipe_config)
4269 {
4270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4271 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4272 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4273 u32 temp, flags = 0;
4274
4275 /* XXX: DSI transcoder paranoia */
4276 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
4277 return;
4278
4279 intel_dsc_get_config(encoder, pipe_config);
4280
4281 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
4282 if (temp & TRANS_DDI_PHSYNC)
4283 flags |= DRM_MODE_FLAG_PHSYNC;
4284 else
4285 flags |= DRM_MODE_FLAG_NHSYNC;
4286 if (temp & TRANS_DDI_PVSYNC)
4287 flags |= DRM_MODE_FLAG_PVSYNC;
4288 else
4289 flags |= DRM_MODE_FLAG_NVSYNC;
4290
4291 pipe_config->hw.adjusted_mode.flags |= flags;
4292
4293 switch (temp & TRANS_DDI_BPC_MASK) {
4294 case TRANS_DDI_BPC_6:
4295 pipe_config->pipe_bpp = 18;
4296 break;
4297 case TRANS_DDI_BPC_8:
4298 pipe_config->pipe_bpp = 24;
4299 break;
4300 case TRANS_DDI_BPC_10:
4301 pipe_config->pipe_bpp = 30;
4302 break;
4303 case TRANS_DDI_BPC_12:
4304 pipe_config->pipe_bpp = 36;
4305 break;
4306 default:
4307 break;
4308 }
4309
4310 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4311 case TRANS_DDI_MODE_SELECT_HDMI:
4312 pipe_config->has_hdmi_sink = true;
4313
4314 pipe_config->infoframes.enable |=
4315 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4316
4317 if (pipe_config->infoframes.enable)
4318 pipe_config->has_infoframe = true;
4319
4320 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4321 pipe_config->hdmi_scrambling = true;
4322 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4323 pipe_config->hdmi_high_tmds_clock_ratio = true;
4324 /* fall through */
4325 case TRANS_DDI_MODE_SELECT_DVI:
4326 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4327 pipe_config->lane_count = 4;
4328 break;
4329 case TRANS_DDI_MODE_SELECT_FDI:
4330 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4331 break;
4332 case TRANS_DDI_MODE_SELECT_DP_SST:
4333 if (encoder->type == INTEL_OUTPUT_EDP)
4334 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4335 else
4336 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4337 pipe_config->lane_count =
4338 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4339 intel_dp_get_m_n(intel_crtc, pipe_config);
4340
4341 if (INTEL_GEN(dev_priv) >= 11) {
4342 i915_reg_t dp_tp_ctl;
4343
4344 if (IS_GEN(dev_priv, 11))
4345 dp_tp_ctl = DP_TP_CTL(encoder->port);
4346 else
4347 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4348
4349 pipe_config->fec_enable =
4350 I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4351
4352 DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n",
4353 encoder->base.base.id, encoder->base.name,
4354 pipe_config->fec_enable);
4355 }
4356
4357 break;
4358 case TRANS_DDI_MODE_SELECT_DP_MST:
4359 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4360 pipe_config->lane_count =
4361 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4362
4363 if (INTEL_GEN(dev_priv) >= 12)
4364 pipe_config->mst_master_transcoder =
4365 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4366
4367 intel_dp_get_m_n(intel_crtc, pipe_config);
4368 break;
4369 default:
4370 break;
4371 }
4372
4373 if (encoder->type == INTEL_OUTPUT_EDP)
4374 tgl_dc3co_exitline_get_config(pipe_config);
4375
4376 pipe_config->has_audio =
4377 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4378
4379 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4380 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4381 /*
4382 * This is a big fat ugly hack.
4383 *
4384 * Some machines in UEFI boot mode provide us a VBT that has 18
4385 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4386 * unknown we fail to light up. Yet the same BIOS boots up with
4387 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4388 * max, not what it tells us to use.
4389 *
4390 * Note: This will still be broken if the eDP panel is not lit
4391 * up by the BIOS, and thus we can't get the mode at module
4392 * load.
4393 */
4394 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4395 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4396 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4397 }
4398
4399 intel_ddi_clock_get(encoder, pipe_config);
4400
4401 if (IS_GEN9_LP(dev_priv))
4402 pipe_config->lane_lat_optim_mask =
4403 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4404
4405 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4406
4407 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4408
4409 intel_read_infoframe(encoder, pipe_config,
4410 HDMI_INFOFRAME_TYPE_AVI,
4411 &pipe_config->infoframes.avi);
4412 intel_read_infoframe(encoder, pipe_config,
4413 HDMI_INFOFRAME_TYPE_SPD,
4414 &pipe_config->infoframes.spd);
4415 intel_read_infoframe(encoder, pipe_config,
4416 HDMI_INFOFRAME_TYPE_VENDOR,
4417 &pipe_config->infoframes.hdmi);
4418 intel_read_infoframe(encoder, pipe_config,
4419 HDMI_INFOFRAME_TYPE_DRM,
4420 &pipe_config->infoframes.drm);
4421 }
4422
4423 static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)4424 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4425 struct intel_crtc_state *crtc_state,
4426 struct drm_connector_state *conn_state)
4427 {
4428 switch (conn_state->connector->connector_type) {
4429 case DRM_MODE_CONNECTOR_HDMIA:
4430 return INTEL_OUTPUT_HDMI;
4431 case DRM_MODE_CONNECTOR_eDP:
4432 return INTEL_OUTPUT_EDP;
4433 case DRM_MODE_CONNECTOR_DisplayPort:
4434 return INTEL_OUTPUT_DP;
4435 default:
4436 MISSING_CASE(conn_state->connector->connector_type);
4437 return INTEL_OUTPUT_UNUSED;
4438 }
4439 }
4440
intel_ddi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)4441 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4442 struct intel_crtc_state *pipe_config,
4443 struct drm_connector_state *conn_state)
4444 {
4445 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4446 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4447 enum port port = encoder->port;
4448 int ret;
4449
4450 if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A)
4451 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4452
4453 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4454 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4455 } else {
4456 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4457 tgl_dc3co_exitline_compute_config(encoder, pipe_config);
4458 }
4459
4460 if (ret)
4461 return ret;
4462
4463 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4464 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4465 pipe_config->pch_pfit.force_thru =
4466 pipe_config->pch_pfit.enabled ||
4467 pipe_config->crc_enabled;
4468
4469 if (IS_GEN9_LP(dev_priv))
4470 pipe_config->lane_lat_optim_mask =
4471 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4472
4473 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4474
4475 return 0;
4476 }
4477
intel_ddi_encoder_destroy(struct drm_encoder * encoder)4478 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4479 {
4480 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4481
4482 intel_dp_encoder_flush_work(encoder);
4483
4484 drm_encoder_cleanup(encoder);
4485 kfree(dig_port);
4486 }
4487
4488 static const struct drm_encoder_funcs intel_ddi_funcs = {
4489 .reset = intel_dp_encoder_reset,
4490 .destroy = intel_ddi_encoder_destroy,
4491 };
4492
4493 static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port * intel_dig_port)4494 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
4495 {
4496 struct intel_connector *connector;
4497 enum port port = intel_dig_port->base.port;
4498
4499 connector = intel_connector_alloc();
4500 if (!connector)
4501 return NULL;
4502
4503 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
4504 intel_dig_port->dp.prepare_link_retrain =
4505 intel_ddi_prepare_link_retrain;
4506
4507 if (!intel_dp_init_connector(intel_dig_port, connector)) {
4508 kfree(connector);
4509 return NULL;
4510 }
4511
4512 return connector;
4513 }
4514
modeset_pipe(struct drm_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)4515 static int modeset_pipe(struct drm_crtc *crtc,
4516 struct drm_modeset_acquire_ctx *ctx)
4517 {
4518 struct drm_atomic_state *state;
4519 struct drm_crtc_state *crtc_state;
4520 int ret;
4521
4522 state = drm_atomic_state_alloc(crtc->dev);
4523 if (!state)
4524 return -ENOMEM;
4525
4526 state->acquire_ctx = ctx;
4527
4528 crtc_state = drm_atomic_get_crtc_state(state, crtc);
4529 if (IS_ERR(crtc_state)) {
4530 ret = PTR_ERR(crtc_state);
4531 goto out;
4532 }
4533
4534 crtc_state->connectors_changed = true;
4535
4536 ret = drm_atomic_commit(state);
4537 out:
4538 drm_atomic_state_put(state);
4539
4540 return ret;
4541 }
4542
intel_hdmi_reset_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)4543 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4544 struct drm_modeset_acquire_ctx *ctx)
4545 {
4546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4547 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4548 struct intel_connector *connector = hdmi->attached_connector;
4549 struct i2c_adapter *adapter =
4550 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4551 struct drm_connector_state *conn_state;
4552 struct intel_crtc_state *crtc_state;
4553 struct intel_crtc *crtc;
4554 u8 config;
4555 int ret;
4556
4557 if (!connector || connector->base.status != connector_status_connected)
4558 return 0;
4559
4560 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4561 ctx);
4562 if (ret)
4563 return ret;
4564
4565 conn_state = connector->base.state;
4566
4567 crtc = to_intel_crtc(conn_state->crtc);
4568 if (!crtc)
4569 return 0;
4570
4571 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4572 if (ret)
4573 return ret;
4574
4575 crtc_state = to_intel_crtc_state(crtc->base.state);
4576
4577 WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4578
4579 if (!crtc_state->hw.active)
4580 return 0;
4581
4582 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4583 !crtc_state->hdmi_scrambling)
4584 return 0;
4585
4586 if (conn_state->commit &&
4587 !try_wait_for_completion(&conn_state->commit->hw_done))
4588 return 0;
4589
4590 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4591 if (ret < 0) {
4592 DRM_ERROR("Failed to read TMDS config: %d\n", ret);
4593 return 0;
4594 }
4595
4596 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4597 crtc_state->hdmi_high_tmds_clock_ratio &&
4598 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4599 crtc_state->hdmi_scrambling)
4600 return 0;
4601
4602 /*
4603 * HDMI 2.0 says that one should not send scrambled data
4604 * prior to configuring the sink scrambling, and that
4605 * TMDS clock/data transmission should be suspended when
4606 * changing the TMDS clock rate in the sink. So let's
4607 * just do a full modeset here, even though some sinks
4608 * would be perfectly happy if were to just reconfigure
4609 * the SCDC settings on the fly.
4610 */
4611 return modeset_pipe(&crtc->base, ctx);
4612 }
4613
4614 static enum intel_hotplug_state
intel_ddi_hotplug(struct intel_encoder * encoder,struct intel_connector * connector,bool irq_received)4615 intel_ddi_hotplug(struct intel_encoder *encoder,
4616 struct intel_connector *connector,
4617 bool irq_received)
4618 {
4619 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4620 struct drm_modeset_acquire_ctx ctx;
4621 enum intel_hotplug_state state;
4622 int ret;
4623
4624 state = intel_encoder_hotplug(encoder, connector, irq_received);
4625
4626 drm_modeset_acquire_init(&ctx, 0);
4627
4628 for (;;) {
4629 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4630 ret = intel_hdmi_reset_link(encoder, &ctx);
4631 else
4632 ret = intel_dp_retrain_link(encoder, &ctx);
4633
4634 if (ret == -EDEADLK) {
4635 drm_modeset_backoff(&ctx);
4636 continue;
4637 }
4638
4639 break;
4640 }
4641
4642 drm_modeset_drop_locks(&ctx);
4643 drm_modeset_acquire_fini(&ctx);
4644 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4645
4646 /*
4647 * Unpowered type-c dongles can take some time to boot and be
4648 * responsible, so here giving some time to those dongles to power up
4649 * and then retrying the probe.
4650 *
4651 * On many platforms the HDMI live state signal is known to be
4652 * unreliable, so we can't use it to detect if a sink is connected or
4653 * not. Instead we detect if it's connected based on whether we can
4654 * read the EDID or not. That in turn has a problem during disconnect,
4655 * since the HPD interrupt may be raised before the DDC lines get
4656 * disconnected (due to how the required length of DDC vs. HPD
4657 * connector pins are specified) and so we'll still be able to get a
4658 * valid EDID. To solve this schedule another detection cycle if this
4659 * time around we didn't detect any change in the sink's connection
4660 * status.
4661 */
4662 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
4663 !dig_port->dp.is_mst)
4664 state = INTEL_HOTPLUG_RETRY;
4665
4666 return state;
4667 }
4668
4669 static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port * intel_dig_port)4670 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
4671 {
4672 struct intel_connector *connector;
4673 enum port port = intel_dig_port->base.port;
4674
4675 connector = intel_connector_alloc();
4676 if (!connector)
4677 return NULL;
4678
4679 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4680 intel_hdmi_init_connector(intel_dig_port, connector);
4681
4682 return connector;
4683 }
4684
intel_ddi_a_force_4_lanes(struct intel_digital_port * dport)4685 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
4686 {
4687 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
4688
4689 if (dport->base.port != PORT_A)
4690 return false;
4691
4692 if (dport->saved_port_bits & DDI_A_4_LANES)
4693 return false;
4694
4695 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4696 * supported configuration
4697 */
4698 if (IS_GEN9_LP(dev_priv))
4699 return true;
4700
4701 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4702 * one who does also have a full A/E split called
4703 * DDI_F what makes DDI_E useless. However for this
4704 * case let's trust VBT info.
4705 */
4706 if (IS_CANNONLAKE(dev_priv) &&
4707 !intel_bios_is_port_present(dev_priv, PORT_E))
4708 return true;
4709
4710 return false;
4711 }
4712
4713 static int
intel_ddi_max_lanes(struct intel_digital_port * intel_dport)4714 intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
4715 {
4716 struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
4717 enum port port = intel_dport->base.port;
4718 int max_lanes = 4;
4719
4720 if (INTEL_GEN(dev_priv) >= 11)
4721 return max_lanes;
4722
4723 if (port == PORT_A || port == PORT_E) {
4724 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4725 max_lanes = port == PORT_A ? 4 : 0;
4726 else
4727 /* Both A and E share 2 lanes */
4728 max_lanes = 2;
4729 }
4730
4731 /*
4732 * Some BIOS might fail to set this bit on port A if eDP
4733 * wasn't lit up at boot. Force this bit set when needed
4734 * so we use the proper lane count for our calculations.
4735 */
4736 if (intel_ddi_a_force_4_lanes(intel_dport)) {
4737 DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
4738 intel_dport->saved_port_bits |= DDI_A_4_LANES;
4739 max_lanes = 4;
4740 }
4741
4742 return max_lanes;
4743 }
4744
intel_ddi_init(struct drm_i915_private * dev_priv,enum port port)4745 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4746 {
4747 struct ddi_vbt_port_info *port_info =
4748 &dev_priv->vbt.ddi_port_info[port];
4749 struct intel_digital_port *intel_dig_port;
4750 struct intel_encoder *encoder;
4751 bool init_hdmi, init_dp, init_lspcon = false;
4752 enum phy phy = intel_port_to_phy(dev_priv, port);
4753
4754 init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
4755 init_dp = port_info->supports_dp;
4756
4757 if (intel_bios_is_lspcon_present(dev_priv, port)) {
4758 /*
4759 * Lspcon device needs to be driven with DP connector
4760 * with special detection sequence. So make sure DP
4761 * is initialized before lspcon.
4762 */
4763 init_dp = true;
4764 init_lspcon = true;
4765 init_hdmi = false;
4766 DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
4767 }
4768
4769 if (!init_dp && !init_hdmi) {
4770 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4771 port_name(port));
4772 return;
4773 }
4774
4775 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4776 if (!intel_dig_port)
4777 return;
4778
4779 encoder = &intel_dig_port->base;
4780
4781 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4782 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
4783
4784 encoder->hotplug = intel_ddi_hotplug;
4785 encoder->compute_output_type = intel_ddi_compute_output_type;
4786 encoder->compute_config = intel_ddi_compute_config;
4787 encoder->enable = intel_enable_ddi;
4788 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4789 encoder->pre_enable = intel_ddi_pre_enable;
4790 encoder->disable = intel_disable_ddi;
4791 encoder->post_disable = intel_ddi_post_disable;
4792 encoder->update_pipe = intel_ddi_update_pipe;
4793 encoder->get_hw_state = intel_ddi_get_hw_state;
4794 encoder->get_config = intel_ddi_get_config;
4795 encoder->suspend = intel_dp_encoder_suspend;
4796 encoder->get_power_domains = intel_ddi_get_power_domains;
4797
4798 encoder->type = INTEL_OUTPUT_DDI;
4799 encoder->power_domain = intel_port_to_power_domain(port);
4800 encoder->port = port;
4801 encoder->cloneable = 0;
4802 encoder->pipe_mask = ~0;
4803
4804 if (INTEL_GEN(dev_priv) >= 11)
4805 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4806 DDI_BUF_PORT_REVERSAL;
4807 else
4808 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
4809 (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4810
4811 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
4812 intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4813 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4814
4815 if (intel_phy_is_tc(dev_priv, phy)) {
4816 bool is_legacy = !port_info->supports_typec_usb &&
4817 !port_info->supports_tbt;
4818
4819 intel_tc_port_init(intel_dig_port, is_legacy);
4820
4821 encoder->update_prepare = intel_ddi_update_prepare;
4822 encoder->update_complete = intel_ddi_update_complete;
4823 }
4824
4825 WARN_ON(port > PORT_I);
4826 intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
4827 port - PORT_A;
4828
4829 if (init_dp) {
4830 if (!intel_ddi_init_dp_connector(intel_dig_port))
4831 goto err;
4832
4833 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4834 }
4835
4836 /* In theory we don't need the encoder->type check, but leave it just in
4837 * case we have some really bad VBTs... */
4838 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4839 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
4840 goto err;
4841 }
4842
4843 if (init_lspcon) {
4844 if (lspcon_init(intel_dig_port))
4845 /* TODO: handle hdmi info frame part */
4846 DRM_DEBUG_KMS("LSPCON init success on port %c\n",
4847 port_name(port));
4848 else
4849 /*
4850 * LSPCON init faied, but DP init was success, so
4851 * lets try to drive as DP++ port.
4852 */
4853 DRM_ERROR("LSPCON init failed on port %c\n",
4854 port_name(port));
4855 }
4856
4857 intel_infoframe_init(intel_dig_port);
4858
4859 return;
4860
4861 err:
4862 drm_encoder_cleanup(&encoder->base);
4863 kfree(intel_dig_port);
4864 }
4865