1 /* $NetBSD: igc_mac.c,v 1.2 2023/10/04 07:35:27 rin Exp $ */
2 /* $OpenBSD: igc_mac.c,v 1.1 2021/10/31 14:52:57 patrick Exp $ */
3 /*-
4 * Copyright 2021 Intel Corp
5 * Copyright 2021 Rubicon Communications, LLC (Netgate)
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <sys/cdefs.h>
10 __KERNEL_RCSID(0, "$NetBSD: igc_mac.c,v 1.2 2023/10/04 07:35:27 rin Exp $");
11
12 #include <dev/pci/igc/igc_api.h>
13 #include <dev/mii/mii.h>
14
15 /**
16 * igc_init_mac_ops_generic - Initialize MAC function pointers
17 * @hw: pointer to the HW structure
18 *
19 * Setups up the function pointers to no-op functions
20 **/
21 void
igc_init_mac_ops_generic(struct igc_hw * hw)22 igc_init_mac_ops_generic(struct igc_hw *hw)
23 {
24 struct igc_mac_info *mac = &hw->mac;
25 DEBUGFUNC("igc_init_mac_ops_generic");
26
27 /* General Setup */
28 mac->ops.init_params = igc_null_ops_generic;
29 mac->ops.config_collision_dist = igc_config_collision_dist_generic;
30 mac->ops.rar_set = igc_rar_set_generic;
31 }
32
33 /**
34 * igc_null_ops_generic - No-op function, returns 0
35 * @hw: pointer to the HW structure
36 **/
37 int
igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG * hw)38 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw)
39 {
40 DEBUGFUNC("igc_null_ops_generic");
41 return IGC_SUCCESS;
42 }
43
44 /**
45 * igc_write_vfta_generic - Write value to VLAN filter table
46 * @hw: pointer to the HW structure
47 * @offset: register offset in VLAN filter table
48 * @value: register value written to VLAN filter table
49 *
50 * Writes value at the given offset in the register array which stores
51 * the VLAN filter table.
52 **/
53 void
igc_write_vfta_generic(struct igc_hw * hw,uint32_t offset,uint32_t value)54 igc_write_vfta_generic(struct igc_hw *hw, uint32_t offset, uint32_t value)
55 {
56 DEBUGFUNC("igc_write_vfta_generic");
57
58 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);
59 IGC_WRITE_FLUSH(hw);
60 }
61
62 /**
63 * igc_init_rx_addrs_generic - Initialize receive address's
64 * @hw: pointer to the HW structure
65 * @rar_count: receive address registers
66 *
67 * Setup the receive address registers by setting the base receive address
68 * register to the devices MAC address and clearing all the other receive
69 * address registers to 0.
70 **/
71 void
igc_init_rx_addrs_generic(struct igc_hw * hw,uint16_t rar_count)72 igc_init_rx_addrs_generic(struct igc_hw *hw, uint16_t rar_count)
73 {
74 uint32_t i;
75 uint8_t mac_addr[ETHER_ADDR_LEN] = {0};
76
77 DEBUGFUNC("igc_init_rx_addrs_generic");
78
79 /* Setup the receive address */
80 DEBUGOUT("Programming MAC Address into RAR[0]\n");
81
82 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
83
84 /* Zero out the other (rar_entry_count - 1) receive addresses */
85 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
86 for (i = 1; i < rar_count; i++)
87 hw->mac.ops.rar_set(hw, mac_addr, i);
88 }
89
90 /**
91 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr
92 * @hw: pointer to the HW structure
93 *
94 * Checks the nvm for an alternate MAC address. An alternate MAC address
95 * can be setup by pre-boot software and must be treated like a permanent
96 * address and must override the actual permanent MAC address. If an
97 * alternate MAC address is found it is programmed into RAR0, replacing
98 * the permanent address that was installed into RAR0 by the Si on reset.
99 * This function will return SUCCESS unless it encounters an error while
100 * reading the EEPROM.
101 **/
102 int
igc_check_alt_mac_addr_generic(struct igc_hw * hw)103 igc_check_alt_mac_addr_generic(struct igc_hw *hw)
104 {
105 uint32_t i;
106 int ret_val;
107 uint16_t offset, nvm_alt_mac_addr_offset, nvm_data;
108 uint8_t alt_mac_addr[ETHER_ADDR_LEN];
109
110 DEBUGFUNC("igc_check_alt_mac_addr_generic");
111
112 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
113 if (ret_val)
114 return ret_val;
115
116 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
117 &nvm_alt_mac_addr_offset);
118 if (ret_val) {
119 DEBUGOUT("NVM Read Error\n");
120 return ret_val;
121 }
122
123 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
124 (nvm_alt_mac_addr_offset == 0x0000))
125 /* There is no Alternate MAC Address */
126 return IGC_SUCCESS;
127
128 if (hw->bus.func == IGC_FUNC_1)
129 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1;
130 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
131 offset = nvm_alt_mac_addr_offset + (i >> 1);
132 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
133 if (ret_val) {
134 DEBUGOUT("NVM Read Error\n");
135 return ret_val;
136 }
137
138 alt_mac_addr[i] = (uint8_t)(nvm_data & 0xFF);
139 alt_mac_addr[i + 1] = (uint8_t)(nvm_data >> 8);
140 }
141
142 /* if multicast bit is set, the alternate address will not be used */
143 if (alt_mac_addr[0] & 0x01) {
144 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
145 return IGC_SUCCESS;
146 }
147
148 /* We have a valid alternate MAC address, and we want to treat it the
149 * same as the normal permanent MAC address stored by the HW into the
150 * RAR. Do this by mapping this address into RAR0.
151 */
152 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
153
154 return IGC_SUCCESS;
155 }
156
157 /**
158 * igc_rar_set_generic - Set receive address register
159 * @hw: pointer to the HW structure
160 * @addr: pointer to the receive address
161 * @index: receive address array register
162 *
163 * Sets the receive address array register at index to the address passed
164 * in by addr.
165 **/
166 int
igc_rar_set_generic(struct igc_hw * hw,uint8_t * addr,uint32_t index)167 igc_rar_set_generic(struct igc_hw *hw, uint8_t *addr, uint32_t index)
168 {
169 uint32_t rar_low, rar_high;
170
171 DEBUGFUNC("igc_rar_set_generic");
172
173 /* HW expects these in little endian so we reverse the byte order
174 * from network order (big endian) to little endian
175 */
176 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) |
177 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
178
179 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
180
181 /* If MAC address zero, no need to set the AV bit */
182 if (rar_low || rar_high)
183 rar_high |= IGC_RAH_AV;
184
185 /* Some bridges will combine consecutive 32-bit writes into
186 * a single burst write, which will malfunction on some parts.
187 * The flushes avoid this.
188 */
189 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
190 IGC_WRITE_FLUSH(hw);
191 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
192 IGC_WRITE_FLUSH(hw);
193
194 return IGC_SUCCESS;
195 }
196
197 /**
198 * igc_hash_mc_addr_generic - Generate a multicast hash value
199 * @hw: pointer to the HW structure
200 * @mc_addr: pointer to a multicast address
201 *
202 * Generates a multicast address hash value which is used to determine
203 * the multicast filter table array address and new table value.
204 **/
205 int
igc_hash_mc_addr_generic(struct igc_hw * hw,uint8_t * mc_addr)206 igc_hash_mc_addr_generic(struct igc_hw *hw, uint8_t *mc_addr)
207 {
208 uint32_t hash_value, hash_mask;
209 uint8_t bit_shift = 0;
210
211 DEBUGFUNC("igc_hash_mc_addr_generic");
212
213 /* Register count multiplied by bits per register */
214 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
215
216 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
217 * where 0xFF would still fall within the hash mask.
218 */
219 while (hash_mask >> bit_shift != 0xFF)
220 bit_shift++;
221
222 /* The portion of the address that is used for the hash table
223 * is determined by the mc_filter_type setting.
224 * The algorithm is such that there is a total of 8 bits of shifting.
225 * The bit_shift for a mc_filter_type of 0 represents the number of
226 * left-shifts where the MSB of mc_addr[5] would still fall within
227 * the hash_mask. Case 0 does this exactly. Since there are a total
228 * of 8 bits of shifting, then mc_addr[4] will shift right the
229 * remaining number of bits. Thus 8 - bit_shift. The rest of the
230 * cases are a variation of this algorithm...essentially raising the
231 * number of bits to shift mc_addr[5] left, while still keeping the
232 * 8-bit shifting total.
233 *
234 * For example, given the following Destination MAC Address and an
235 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
236 * we can see that the bit_shift for case 0 is 4. These are the hash
237 * values resulting from each mc_filter_type...
238 * [0] [1] [2] [3] [4] [5]
239 * 01 AA 00 12 34 56
240 * LSB MSB
241 *
242 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
243 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
244 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
245 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
246 */
247 switch (hw->mac.mc_filter_type) {
248 default:
249 case 0:
250 break;
251 case 1:
252 bit_shift += 1;
253 break;
254 case 2:
255 bit_shift += 2;
256 break;
257 case 3:
258 bit_shift += 4;
259 break;
260 }
261
262 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
263 (((uint16_t) mc_addr[5]) << bit_shift)));
264
265 return hash_value;
266 }
267
268 /**
269 * igc_update_mc_addr_list_generic - Update Multicast addresses
270 * @hw: pointer to the HW structure
271 * @mc_addr_list: array of multicast addresses to program
272 * @mc_addr_count: number of multicast addresses to program
273 *
274 * Updates entire Multicast Table Array.
275 * The caller must have a packed mc_addr_list of multicast addresses.
276 **/
277 void
igc_update_mc_addr_list_generic(struct igc_hw * hw,uint8_t * mc_addr_list,uint32_t mc_addr_count)278 igc_update_mc_addr_list_generic(struct igc_hw *hw, uint8_t *mc_addr_list,
279 uint32_t mc_addr_count)
280 {
281 uint32_t hash_value, hash_bit, hash_reg;
282 int i;
283
284 DEBUGFUNC("igc_update_mc_addr_list_generic");
285
286 /* clear mta_shadow */
287 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
288
289 /* update mta_shadow from mc_addr_list */
290 for (i = 0; (uint32_t)i < mc_addr_count; i++) {
291 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);
292
293 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
294 hash_bit = hash_value & 0x1F;
295
296 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
297 mc_addr_list += (ETHER_ADDR_LEN);
298 }
299
300 /* replace the entire MTA table */
301 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
302 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);
303 IGC_WRITE_FLUSH(hw);
304 }
305
306 /**
307 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters
308 * @hw: pointer to the HW structure
309 *
310 * Clears the base hardware counters by reading the counter registers.
311 **/
312 void
igc_clear_hw_cntrs_base_generic(struct igc_hw * hw)313 igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)
314 {
315 DEBUGFUNC("igc_clear_hw_cntrs_base_generic");
316
317 IGC_READ_REG(hw, IGC_CRCERRS);
318 IGC_READ_REG(hw, IGC_ALGNERRC);
319 IGC_READ_REG(hw, IGC_MPC);
320 IGC_READ_REG(hw, IGC_SCC);
321 IGC_READ_REG(hw, IGC_ECOL);
322 IGC_READ_REG(hw, IGC_MCC);
323 IGC_READ_REG(hw, IGC_LATECOL);
324 IGC_READ_REG(hw, IGC_COLC);
325 IGC_READ_REG(hw, IGC_RERC);
326 IGC_READ_REG(hw, IGC_DC);
327 IGC_READ_REG(hw, IGC_TNCRS);
328 IGC_READ_REG(hw, IGC_HTDPMC);
329 IGC_READ_REG(hw, IGC_RLEC);
330 IGC_READ_REG(hw, IGC_XONRXC);
331 IGC_READ_REG(hw, IGC_XONTXC);
332 IGC_READ_REG(hw, IGC_XOFFRXC);
333 IGC_READ_REG(hw, IGC_XOFFTXC);
334 IGC_READ_REG(hw, IGC_FCRUC);
335 IGC_READ_REG(hw, IGC_PRC64);
336 IGC_READ_REG(hw, IGC_PRC127);
337 IGC_READ_REG(hw, IGC_PRC255);
338 IGC_READ_REG(hw, IGC_PRC511);
339 IGC_READ_REG(hw, IGC_PRC1023);
340 IGC_READ_REG(hw, IGC_PRC1522);
341 IGC_READ_REG(hw, IGC_GPRC);
342 IGC_READ_REG(hw, IGC_BPRC);
343 IGC_READ_REG(hw, IGC_MPRC);
344 IGC_READ_REG(hw, IGC_GPTC);
345 IGC_READ_REG(hw, IGC_GORCL);
346 IGC_READ_REG(hw, IGC_GORCH);
347 IGC_READ_REG(hw, IGC_GOTCL);
348 IGC_READ_REG(hw, IGC_GOTCH);
349 IGC_READ_REG(hw, IGC_RNBC);
350 IGC_READ_REG(hw, IGC_RUC);
351 IGC_READ_REG(hw, IGC_RFC);
352 IGC_READ_REG(hw, IGC_ROC);
353 IGC_READ_REG(hw, IGC_RJC);
354 IGC_READ_REG(hw, IGC_MGTPRC);
355 IGC_READ_REG(hw, IGC_MGTPDC);
356 IGC_READ_REG(hw, IGC_MGTPTC);
357 IGC_READ_REG(hw, IGC_TORL);
358 IGC_READ_REG(hw, IGC_TORH);
359 IGC_READ_REG(hw, IGC_TOTL);
360 IGC_READ_REG(hw, IGC_TOTH);
361 IGC_READ_REG(hw, IGC_TPR);
362 IGC_READ_REG(hw, IGC_TPT);
363 IGC_READ_REG(hw, IGC_PTC64);
364 IGC_READ_REG(hw, IGC_PTC127);
365 IGC_READ_REG(hw, IGC_PTC255);
366 IGC_READ_REG(hw, IGC_PTC511);
367 IGC_READ_REG(hw, IGC_PTC1023);
368 IGC_READ_REG(hw, IGC_PTC1522);
369 IGC_READ_REG(hw, IGC_MPTC);
370 IGC_READ_REG(hw, IGC_BPTC);
371 IGC_READ_REG(hw, IGC_TSCTC);
372 IGC_READ_REG(hw, IGC_IAC);
373 IGC_READ_REG(hw, IGC_RXDMTC);
374 IGC_READ_REG(hw, IGC_HGORCL);
375 IGC_READ_REG(hw, IGC_HGORCH);
376 IGC_READ_REG(hw, IGC_HGOTCL);
377 IGC_READ_REG(hw, IGC_HGOTCH);
378 IGC_READ_REG(hw, IGC_LENERRS);
379 IGC_READ_REG(hw, IGC_TLPIC);
380 IGC_READ_REG(hw, IGC_RLPIC);
381 }
382
383 /**
384 * igc_setup_link_generic - Setup flow control and link settings
385 * @hw: pointer to the HW structure
386 *
387 * Determines which flow control settings to use, then configures flow
388 * control. Calls the appropriate media-specific link configuration
389 * function. Assuming the adapter has a valid link partner, a valid link
390 * should be established. Assumes the hardware has previously been reset
391 * and the transmitter and receiver are not enabled.
392 **/
393 int
igc_setup_link_generic(struct igc_hw * hw)394 igc_setup_link_generic(struct igc_hw *hw)
395 {
396 int ret_val;
397
398 DEBUGFUNC("igc_setup_link_generic");
399
400 /* In the case of the phy reset being blocked, we already have a link.
401 * We do not need to set it up again.
402 */
403 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
404 return IGC_SUCCESS;
405
406 /* If requested flow control is set to default, set flow control
407 * for both 'rx' and 'tx' pause frames.
408 */
409 if (hw->fc.requested_mode == igc_fc_default) {
410 hw->fc.requested_mode = igc_fc_full;
411 }
412
413 /* Save off the requested flow control mode for use later. Depending
414 * on the link partner's capabilities, we may or may not use this mode.
415 */
416 hw->fc.current_mode = hw->fc.requested_mode;
417
418 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
419 hw->fc.current_mode);
420
421 /* Call the necessary media_type subroutine to configure the link. */
422 ret_val = hw->mac.ops.setup_physical_interface(hw);
423 if (ret_val)
424 return ret_val;
425
426 /* Initialize the flow control address, type, and PAUSE timer
427 * registers to their default values. This is done even if flow
428 * control is disabled, because it does not hurt anything to
429 * initialize these registers.
430 */
431 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);
432 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
433 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
434
435 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);
436
437 return igc_set_fc_watermarks_generic(hw);
438 }
439
440 /**
441 * igc_config_collision_dist_generic - Configure collision distance
442 * @hw: pointer to the HW structure
443 *
444 * Configures the collision distance to the default value and is used
445 * during link setup.
446 **/
447 void
igc_config_collision_dist_generic(struct igc_hw * hw)448 igc_config_collision_dist_generic(struct igc_hw *hw)
449 {
450 uint32_t tctl;
451
452 DEBUGFUNC("igc_config_collision_dist_generic");
453
454 tctl = IGC_READ_REG(hw, IGC_TCTL);
455
456 tctl &= ~IGC_TCTL_COLD;
457 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
458
459 IGC_WRITE_REG(hw, IGC_TCTL, tctl);
460 IGC_WRITE_FLUSH(hw);
461 }
462
463 /**
464 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks
465 * @hw: pointer to the HW structure
466 *
467 * Sets the flow control high/low threshold (watermark) registers. If
468 * flow control XON frame transmission is enabled, then set XON frame
469 * transmission as well.
470 **/
471 int
igc_set_fc_watermarks_generic(struct igc_hw * hw)472 igc_set_fc_watermarks_generic(struct igc_hw *hw)
473 {
474 uint32_t fcrtl = 0, fcrth = 0;
475
476 DEBUGFUNC("igc_set_fc_watermarks_generic");
477
478 /* Set the flow control receive threshold registers. Normally,
479 * these registers will be set to a default threshold that may be
480 * adjusted later by the driver's runtime code. However, if the
481 * ability to transmit pause frames is not enabled, then these
482 * registers will be set to 0.
483 */
484 if (hw->fc.current_mode & igc_fc_tx_pause) {
485 /* We need to set up the Receive Threshold high and low water
486 * marks as well as (optionally) enabling the transmission of
487 * XON frames.
488 */
489 fcrtl = hw->fc.low_water;
490 if (hw->fc.send_xon)
491 fcrtl |= IGC_FCRTL_XONE;
492
493 fcrth = hw->fc.high_water;
494 }
495 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);
496 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth);
497
498 return IGC_SUCCESS;
499 }
500
501 /**
502 * igc_force_mac_fc_generic - Force the MAC's flow control settings
503 * @hw: pointer to the HW structure
504 *
505 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
506 * device control register to reflect the adapter settings. TFCE and RFCE
507 * need to be explicitly set by software when a copper PHY is used because
508 * autonegotiation is managed by the PHY rather than the MAC. Software must
509 * also configure these bits when link is forced on a fiber connection.
510 **/
511 int
igc_force_mac_fc_generic(struct igc_hw * hw)512 igc_force_mac_fc_generic(struct igc_hw *hw)
513 {
514 uint32_t ctrl;
515
516 DEBUGFUNC("igc_force_mac_fc_generic");
517
518 ctrl = IGC_READ_REG(hw, IGC_CTRL);
519
520 /* Because we didn't get link via the internal auto-negotiation
521 * mechanism (we either forced link or we got link via PHY
522 * auto-neg), we have to manually enable/disable transmit an
523 * receive flow control.
524 *
525 * The "Case" statement below enables/disable flow control
526 * according to the "hw->fc.current_mode" parameter.
527 *
528 * The possible values of the "fc" parameter are:
529 * 0: Flow control is completely disabled
530 * 1: Rx flow control is enabled (we can receive pause
531 * frames but not send pause frames).
532 * 2: Tx flow control is enabled (we can send pause frames
533 * frames but we do not receive pause frames).
534 * 3: Both Rx and Tx flow control (symmetric) is enabled.
535 * other: No other values should be possible at this point.
536 */
537 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
538
539 switch (hw->fc.current_mode) {
540 case igc_fc_none:
541 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
542 break;
543 case igc_fc_rx_pause:
544 ctrl &= (~IGC_CTRL_TFCE);
545 ctrl |= IGC_CTRL_RFCE;
546 break;
547 case igc_fc_tx_pause:
548 ctrl &= (~IGC_CTRL_RFCE);
549 ctrl |= IGC_CTRL_TFCE;
550 break;
551 case igc_fc_full:
552 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
553 break;
554 default:
555 DEBUGOUT("Flow control param set incorrectly\n");
556 return -IGC_ERR_CONFIG;
557 }
558
559 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
560
561 return IGC_SUCCESS;
562 }
563
564 /**
565 * igc_config_fc_after_link_up_generic - Configures flow control after link
566 * @hw: pointer to the HW structure
567 *
568 * Checks the status of auto-negotiation after link up to ensure that the
569 * speed and duplex were not forced. If the link needed to be forced, then
570 * flow control needs to be forced also. If auto-negotiation is enabled
571 * and did not fail, then we configure flow control based on our link
572 * partner.
573 **/
574 int
igc_config_fc_after_link_up_generic(struct igc_hw * hw)575 igc_config_fc_after_link_up_generic(struct igc_hw *hw)
576 {
577 struct igc_mac_info *mac = &hw->mac;
578 uint16_t mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
579 uint16_t speed, duplex;
580 int ret_val = IGC_SUCCESS;
581
582 DEBUGFUNC("igc_config_fc_after_link_up_generic");
583
584 if (ret_val) {
585 DEBUGOUT("Error forcing flow control settings\n");
586 return ret_val;
587 }
588
589 /* Check for the case where we have copper media and auto-neg is
590 * enabled. In this case, we need to check and see if Auto-Neg
591 * has completed, and if so, how the PHY and link partner has
592 * flow control configured.
593 */
594 if (mac->autoneg) {
595 /* Read the MII Status Register and check to see if AutoNeg
596 * has completed. We read this twice because this reg has
597 * some "sticky" (latched) bits.
598 */
599 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &mii_status_reg);
600 if (ret_val)
601 return ret_val;
602 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &mii_status_reg);
603 if (ret_val)
604 return ret_val;
605
606 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE))
607 return ret_val;
608
609 /* The AutoNeg process has completed, so we now need to
610 * read both the Auto Negotiation Advertisement
611 * Register (Address 4) and the Auto_Negotiation Base
612 * Page Ability Register (Address 5) to determine how
613 * flow control was negotiated.
614 */
615 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
616 &mii_nway_adv_reg);
617 if (ret_val)
618 return ret_val;
619 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
620 &mii_nway_lp_ability_reg);
621 if (ret_val)
622 return ret_val;
623
624 /* Two bits in the Auto Negotiation Advertisement Register
625 * (Address 4) and two bits in the Auto Negotiation Base
626 * Page Ability Register (Address 5) determine flow control
627 * for both the PHY and the link partner. The following
628 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
629 * 1999, describes these PAUSE resolution bits and how flow
630 * control is determined based upon these settings.
631 * NOTE: DC = Don't Care
632 *
633 * LOCAL DEVICE | LINK PARTNER
634 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
635 *-------|---------|-------|---------|--------------------
636 * 0 | 0 | DC | DC | igc_fc_none
637 * 0 | 1 | 0 | DC | igc_fc_none
638 * 0 | 1 | 1 | 0 | igc_fc_none
639 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
640 * 1 | 0 | 0 | DC | igc_fc_none
641 * 1 | DC | 1 | DC | igc_fc_full
642 * 1 | 1 | 0 | 0 | igc_fc_none
643 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
644 *
645 * Are both PAUSE bits set to 1? If so, this implies
646 * Symmetric Flow Control is enabled at both ends. The
647 * ASM_DIR bits are irrelevant per the spec.
648 *
649 * For Symmetric Flow Control:
650 *
651 * LOCAL DEVICE | LINK PARTNER
652 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
653 *-------|---------|-------|---------|--------------------
654 * 1 | DC | 1 | DC | IGC_fc_full
655 *
656 */
657 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
658 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
659 /* Now we need to check if the user selected Rx ONLY
660 * of pause frames. In this case, we had to advertise
661 * FULL flow control because we could not advertise Rx
662 * ONLY. Hence, we must now check to see if we need to
663 * turn OFF the TRANSMISSION of PAUSE frames.
664 */
665 if (hw->fc.requested_mode == igc_fc_full)
666 hw->fc.current_mode = igc_fc_full;
667 else
668 hw->fc.current_mode = igc_fc_rx_pause;
669 }
670 /* For receiving PAUSE frames ONLY.
671 *
672 * LOCAL DEVICE | LINK PARTNER
673 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
674 *-------|---------|-------|---------|--------------------
675 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
676 */
677 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
678 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
679 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
680 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
681 hw->fc.current_mode = igc_fc_tx_pause;
682 }
683 /* For transmitting PAUSE frames ONLY.
684 *
685 * LOCAL DEVICE | LINK PARTNER
686 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
687 *-------|---------|-------|---------|--------------------
688 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
689 */
690 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
691 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
692 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
693 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
694 hw->fc.current_mode = igc_fc_rx_pause;
695 } else {
696 /* Per the IEEE spec, at this point flow control
697 * should be disabled.
698 */
699 hw->fc.current_mode = igc_fc_none;
700 DEBUGOUT("Flow Control = NONE.\n");
701 }
702
703 /* Now we need to do one last check... If we auto-
704 * negotiated to HALF DUPLEX, flow control should not be
705 * enabled per IEEE 802.3 spec.
706 */
707 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
708 if (ret_val) {
709 DEBUGOUT("Error getting link speed and duplex\n");
710 return ret_val;
711 }
712
713 if (duplex == HALF_DUPLEX)
714 hw->fc.current_mode = igc_fc_none;
715
716 /* Now we call a subroutine to actually force the MAC
717 * controller to use the correct flow control settings.
718 */
719 ret_val = igc_force_mac_fc_generic(hw);
720 if (ret_val) {
721 DEBUGOUT("Error forcing flow control settings\n");
722 return ret_val;
723 }
724 }
725
726 return IGC_SUCCESS;
727 }
728
729 /**
730 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
731 * @hw: pointer to the HW structure
732 * @speed: stores the current speed
733 * @duplex: stores the current duplex
734 *
735 * Read the status register for the current speed/duplex and store the current
736 * speed and duplex for copper connections.
737 **/
738 int
igc_get_speed_and_duplex_copper_generic(struct igc_hw * hw,uint16_t * speed,uint16_t * duplex)739 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, uint16_t *speed,
740 uint16_t *duplex)
741 {
742 uint32_t status;
743
744 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic");
745
746 status = IGC_READ_REG(hw, IGC_STATUS);
747 if (status & IGC_STATUS_SPEED_1000) {
748 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
749 * and 2.5 Gbps link modes. An additional bit is used
750 * to differentiate between 1 Gbps and 2.5 Gbps.
751 */
752 if ((hw->mac.type == igc_i225) &&
753 (status & IGC_STATUS_SPEED_2500)) {
754 *speed = SPEED_2500;
755 DEBUGOUT("2500 Mbs, ");
756 } else {
757 *speed = SPEED_1000;
758 DEBUGOUT("1000 Mbs, ");
759 }
760 } else if (status & IGC_STATUS_SPEED_100) {
761 *speed = SPEED_100;
762 DEBUGOUT("100 Mbs, ");
763 } else {
764 *speed = SPEED_10;
765 DEBUGOUT("10 Mbs, ");
766 }
767
768 if (status & IGC_STATUS_FD) {
769 *duplex = FULL_DUPLEX;
770 DEBUGOUT("Full Duplex\n");
771 } else {
772 *duplex = HALF_DUPLEX;
773 DEBUGOUT("Half Duplex\n");
774 }
775
776 return IGC_SUCCESS;
777 }
778
779 /**
780 * igc_put_hw_semaphore_generic - Release hardware semaphore
781 * @hw: pointer to the HW structure
782 *
783 * Release hardware semaphore used to access the PHY or NVM
784 **/
785 void
igc_put_hw_semaphore_generic(struct igc_hw * hw)786 igc_put_hw_semaphore_generic(struct igc_hw *hw)
787 {
788 uint32_t swsm;
789
790 DEBUGFUNC("igc_put_hw_semaphore_generic");
791
792 swsm = IGC_READ_REG(hw, IGC_SWSM);
793 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
794
795 IGC_WRITE_REG(hw, IGC_SWSM, swsm);
796 }
797
798 /**
799 * igc_get_auto_rd_done_generic - Check for auto read completion
800 * @hw: pointer to the HW structure
801 *
802 * Check EEPROM for Auto Read done bit.
803 **/
804 int
igc_get_auto_rd_done_generic(struct igc_hw * hw)805 igc_get_auto_rd_done_generic(struct igc_hw *hw)
806 {
807 int i = 0;
808
809 DEBUGFUNC("igc_get_auto_rd_done_generic");
810
811 while (i < AUTO_READ_DONE_TIMEOUT) {
812 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)
813 break;
814 msec_delay(1);
815 i++;
816 }
817
818 if (i == AUTO_READ_DONE_TIMEOUT) {
819 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
820 return -IGC_ERR_RESET;
821 }
822
823 return IGC_SUCCESS;
824 }
825
826 /**
827 * igc_disable_pcie_master_generic - Disables PCI-express master access
828 * @hw: pointer to the HW structure
829 *
830 * Returns IGC_SUCCESS if successful, else returns -10
831 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
832 * the master requests to be disabled.
833 *
834 * Disables PCI-Express master access and verifies there are no pending
835 * requests.
836 **/
837 int
igc_disable_pcie_master_generic(struct igc_hw * hw)838 igc_disable_pcie_master_generic(struct igc_hw *hw)
839 {
840 uint32_t ctrl;
841 int timeout = MASTER_DISABLE_TIMEOUT;
842
843 DEBUGFUNC("igc_disable_pcie_master_generic");
844
845 ctrl = IGC_READ_REG(hw, IGC_CTRL);
846 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
847 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
848
849 while (timeout) {
850 if (!(IGC_READ_REG(hw, IGC_STATUS) &
851 IGC_STATUS_GIO_MASTER_ENABLE))
852 break;
853 DELAY(100);
854 timeout--;
855 }
856
857 if (!timeout) {
858 DEBUGOUT("Master requests are pending.\n");
859 return -IGC_ERR_MASTER_REQUESTS_PENDING;
860 }
861
862 return IGC_SUCCESS;
863 }
864