xref: /netbsd-src/sys/arch/evbarm/ifpga/ifpga_pci.c (revision 7433666e375b3ac4cc764df5a6726be98bc1cdd5)
1 /*	$NetBSD: ifpga_pci.c,v 1.26 2023/12/20 13:55:17 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 2001 ARM Ltd
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. The name of the company may not be used to endorse or promote
16  *    products derived from this software without specific prior written
17  *    permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  *
31  * Copyright (c) 1997,1998 Mark Brinicombe.
32  * Copyright (c) 1997,1998 Causality Limited
33  * All rights reserved.
34  *
35  * Redistribution and use in source and binary forms, with or without
36  * modification, are permitted provided that the following conditions
37  * are met:
38  * 1. Redistributions of source code must retain the above copyright
39  *    notice, this list of conditions and the following disclaimer.
40  * 2. Redistributions in binary form must reproduce the above copyright
41  *    notice, this list of conditions and the following disclaimer in the
42  *    documentation and/or other materials provided with the distribution.
43  * 3. All advertising materials mentioning features or use of this software
44  *    must display the following acknowledgement:
45  *	This product includes software developed by Mark Brinicombe
46  *	for the NetBSD Project.
47  * 4. The name of the company nor the name of the author may be used to
48  *    endorse or promote products derived from this software without specific
49  *    prior written permission.
50  *
51  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
52  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
53  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
54  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
55  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
57  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
59  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
60  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
61  * SUCH DAMAGE.
62  */
63 
64 #define _ARM32_BUS_DMA_PRIVATE
65 
66 #include <sys/cdefs.h>
67 __KERNEL_RCSID(0, "$NetBSD: ifpga_pci.c,v 1.26 2023/12/20 13:55:17 thorpej Exp $");
68 
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/conf.h>
72 #include <sys/device.h>
73 
74 #include <evbarm/integrator/int_bus_dma.h>
75 
76 #include <machine/intr.h>
77 
78 #include <dev/pci/pcireg.h>
79 #include <dev/pci/pcivar.h>
80 
81 #include <evbarm/ifpga/ifpgareg.h>
82 #include <evbarm/ifpga/ifpgamem.h>
83 #include <evbarm/ifpga/ifpga_pcivar.h>
84 #include <evbarm/dev/v360reg.h>
85 
86 
87 void		ifpga_pci_attach_hook (device_t, device_t,
88 		    struct pcibus_attach_args *);
89 int		ifpga_pci_bus_maxdevs (void *, int);
90 pcitag_t	ifpga_pci_make_tag (void *, int, int, int);
91 void		ifpga_pci_decompose_tag (void *, pcitag_t, int *, int *,
92 		    int *);
93 pcireg_t	ifpga_pci_conf_read (void *, pcitag_t, int);
94 void		ifpga_pci_conf_write (void *, pcitag_t, int, pcireg_t);
95 int		ifpga_pci_intr_map (const struct pci_attach_args *,
96 		    pci_intr_handle_t *);
97 const char	*ifpga_pci_intr_string (void *, pci_intr_handle_t, char *, size_t);
98 const struct evcnt *ifpga_pci_intr_evcnt (void *, pci_intr_handle_t);
99 void		*ifpga_pci_intr_establish (void *, pci_intr_handle_t, int,
100 		    int (*)(void *), void *, const char *);
101 void		ifpga_pci_intr_disestablish (void *, void *);
102 
103 struct arm32_pci_chipset ifpga_pci_chipset = {
104 	.pc_attach_hook = ifpga_pci_attach_hook,
105 	.pc_bus_maxdevs = ifpga_pci_bus_maxdevs,
106 	.pc_make_tag = ifpga_pci_make_tag,
107 	.pc_decompose_tag = ifpga_pci_decompose_tag,
108 	.pc_conf_read = ifpga_pci_conf_read,
109 	.pc_conf_write = ifpga_pci_conf_write,
110 	.pc_intr_map = ifpga_pci_intr_map,
111 	.pc_intr_string = ifpga_pci_intr_string,
112 	.pc_intr_evcnt = ifpga_pci_intr_evcnt,
113 	.pc_intr_establish = ifpga_pci_intr_establish,
114 	.pc_intr_disestablish = ifpga_pci_intr_disestablish,
115 	.pc_conf_interrupt = ifpga_pci_conf_interrupt,
116 };
117 
118 /*
119  * Use the integrator-specific bus_dma routines.
120  */
121 struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag = {
122 	0,
123 	0,
124 	NULL,
125 	_bus_dmamap_create,
126 	_bus_dmamap_destroy,
127 	_bus_dmamap_load,
128 	_bus_dmamap_load_mbuf,
129 	_bus_dmamap_load_uio,
130 	_bus_dmamap_load_raw,
131 	_bus_dmamap_unload,
132 	_bus_dmamap_sync,	/* pre */
133 	NULL,			/* post */
134 	_bus_dmamem_alloc,
135 	_bus_dmamem_free,
136 	_bus_dmamem_map,
137 	_bus_dmamem_unmap,
138 	_bus_dmamem_mmap,
139 };
140 
141 /*
142  * Currently we only support 12 devices as we select directly in the
143  * type 0 config cycle
144  * (See conf_{read,write} for more detail
145  */
146 #define MAX_PCI_DEVICES	21
147 
148 /*static int
149 pci_intr(void *arg)
150 {
151 	printf("pci int %x\n", (int)arg);
152 	return 0;
153 }*/
154 
155 
156 void
ifpga_pci_attach_hook(device_t parent,device_t self,struct pcibus_attach_args * pba)157 ifpga_pci_attach_hook(device_t parent, device_t self,
158     struct pcibus_attach_args *pba)
159 {
160 #ifdef PCI_DEBUG
161 	printf("ifpga_pci_attach_hook()\n");
162 #endif
163 }
164 
165 int
ifpga_pci_bus_maxdevs(void * pcv,int busno)166 ifpga_pci_bus_maxdevs(void *pcv, int busno)
167 {
168 #ifdef PCI_DEBUG
169 	printf("ifpga_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno);
170 #endif
171 	return MAX_PCI_DEVICES;
172 }
173 
174 pcitag_t
ifpga_pci_make_tag(void * pcv,int bus,int device,int function)175 ifpga_pci_make_tag(void *pcv, int bus, int device, int function)
176 {
177 #ifdef PCI_DEBUG
178 	printf("ifpga_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n",
179 	    pcv, bus, device, function);
180 #endif
181 	return (bus << 16) | (device << 11) | (function << 8);
182 }
183 
184 void
ifpga_pci_decompose_tag(void * pcv,pcitag_t tag,int * busp,int * devicep,int * functionp)185 ifpga_pci_decompose_tag(void *pcv, pcitag_t tag, int *busp, int *devicep,
186     int *functionp)
187 {
188 #ifdef PCI_DEBUG
189 	printf("ifpga_pci_decompose_tag(pcv=%p, tag=0x%08lx, bp=%p, dp=%p, "
190 	    "fp=%p)\n", pcv, tag, busp, devicep, functionp);
191 #endif
192 
193 	if (busp != NULL)
194 		*busp = (tag >> 16) & 0xff;
195 	if (devicep != NULL)
196 		*devicep = (tag >> 11) & 0x1f;
197 	if (functionp != NULL)
198 		*functionp = (tag >> 8) & 0x7;
199 }
200 
201 pcireg_t
ifpga_pci_conf_read(void * pcv,pcitag_t tag,int reg)202 ifpga_pci_conf_read(void *pcv, pcitag_t tag, int reg)
203 {
204 	pcireg_t data;
205 	struct ifpga_pci_softc *sc = (struct ifpga_pci_softc *)pcv;
206 	int bus, device, function;
207 	u_int address;
208 
209 	if ((unsigned int)reg >= PCI_CONF_SIZE)
210 		return (pcireg_t) -1;
211 
212 	ifpga_pci_decompose_tag(pcv, tag, &bus, &device, &function);
213 
214 	/* Reset the appertures so that we can talk to the register space.  */
215 	bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0,
216 	    IFPGA_PCI_APP0_512MB_BASE);
217 	bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1,
218 	    IFPGA_PCI_APP1_CONF_BASE);
219 
220 	if (bus == 0) {
221 		address = (1 << (device + 11)) | reg;
222 		bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
223 		    IFPGA_PCI_APP1_CONF_T0_MAP | ((address >> 16) & 0xff00));
224 
225 		/* Read the value from the bus...  */
226 		data = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh,
227 		    address & 0x00ffffff);
228 
229 	} else {
230 		bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
231 		    IFPGA_PCI_APP1_CONF_T1_MAP);
232 
233 		/* Read the value from the bus... */
234 		data = bus_space_read_4(sc->sc_iot, sc->sc_conf_ioh,
235 		    tag | reg);
236 	}
237 	/* ... and put the memory spaces back again.  */
238 
239 	bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1,
240 	    IFPGA_PCI_APP1_256MB_BASE);
241 	bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
242 	    IFPGA_PCI_APP1_256MB_MAP);
243 	bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0,
244 	    IFPGA_PCI_APP0_256MB_BASE);
245 #ifdef PCI_DEBUG
246 	printf("ifpga_pci_conf_read(pcv=%p tag=0x%08lx reg=0x%02x)=0x%08x\n",
247 	    pcv, tag, reg, data);
248 #endif
249 	return data;
250 }
251 
252 void
ifpga_pci_conf_write(void * pcv,pcitag_t tag,int reg,pcireg_t data)253 ifpga_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data)
254 {
255 	struct ifpga_pci_softc *sc = (struct ifpga_pci_softc *)pcv;
256 	int bus, device, function;
257 	u_int address;
258 
259 #ifdef PCI_DEBUG
260 	printf("ifpga_pci_conf_write(pcv=%p tag=0x%08lx reg=0x%02x, 0x%08x)\n",
261 	    pcv, tag, reg, data);
262 #endif
263 
264 	if ((unsigned int)reg >= PCI_CONF_SIZE)
265 		return;
266 
267 	ifpga_pci_decompose_tag(pcv, tag, &bus, &device, &function);
268 
269 	/* Reset the appertures so that we can talk to the register space.  */
270 	bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0,
271 	    IFPGA_PCI_APP0_512MB_BASE);
272 	bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1,
273 	    IFPGA_PCI_APP1_CONF_BASE);
274 
275 	if (bus == 0) {
276 		address = (1 << (device + 11)) | reg;
277 		bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
278 		    IFPGA_PCI_APP1_CONF_T0_MAP | ((address >> 16) & 0xff00));
279 
280 		/* Write the value to the bus...  */
281 		bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh,
282 		    address & 0x00ffffff, data);
283 
284 	} else {
285 		bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
286 		    IFPGA_PCI_APP1_CONF_T1_MAP);
287 
288 		/* Write the value to the bus... */
289 		bus_space_write_4(sc->sc_iot, sc->sc_conf_ioh, tag | reg,
290 		    data);
291 	}
292 	/* ... and put the memory spaces back again.  */
293 
294 	bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE1,
295 	    IFPGA_PCI_APP1_256MB_BASE);
296 	bus_space_write_2(sc->sc_memt, sc->sc_reg_ioh, V360_LB_MAP1,
297 	    IFPGA_PCI_APP1_256MB_MAP);
298 	bus_space_write_4(sc->sc_memt, sc->sc_reg_ioh, V360_LB_BASE0,
299 	    IFPGA_PCI_APP0_256MB_BASE);
300 }
301 
302 int
ifpga_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)303 ifpga_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
304 {
305 	int line = pa->pa_intrline;
306 
307 #ifdef PCI_DEBUG
308 	int pin = pa->pa_intrpin;
309 	void *pcv = pa->pa_pc;
310 	pcitag_t intrtag = pa->pa_intrtag;
311 	int bus, device, function;
312 
313 	ifpga_pci_decompose_tag(pcv, intrtag, &bus, &device, &function);
314 	printf("ifpga_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d "
315 	    "dev=%d\n", pcv, intrtag, pin, line, device);
316 #endif
317 
318 
319 #ifdef PCI_DEBUG
320 	printf("pin %d, line %d mapped to int %d\n", pin, line, line);
321 #endif
322 
323 	*ihp = line;
324 	return 0;
325 }
326 
327 const char *
ifpga_pci_intr_string(void * pcv,pci_intr_handle_t ih,char * buf,size_t len)328 ifpga_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len)
329 {
330 #ifdef PCI_DEBUG
331 	printf("ifpga_pci_intr_string(pcv=%p, ih=0x%" PRIu64 ")\n", pcv, ih);
332 #endif
333 	if (ih == 0)
334 		panic("ifpga_pci_intr_string: bogus handle 0x%" PRIu64, ih);
335 
336 	snprintf(buf, len, "pciint%" PRIu64, ih - IFPGA_INTRNUM_PCIINT0);
337 	return buf;
338 }
339 
340 const struct evcnt *
ifpga_pci_intr_evcnt(void * pcv,pci_intr_handle_t ih)341 ifpga_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih)
342 {
343 
344 	/* XXX for now, no evcnt parent reported */
345 	return NULL;
346 }
347 
348 void *
ifpga_pci_intr_establish(void * pcv,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg,const char * xname)349 ifpga_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level,
350     int (*func) (void *), void *arg, const char *xname)
351 {
352 	void *intr;
353 
354 #ifdef PCI_DEBUG
355 	printf("ifpga_pci_intr_establish(pcv=%p, ih=0x%" PRIu64 ", level=%d, "
356 	    "func=%p, arg=%p, xname=%s)\n", pcv, ih, level, func, arg, xname);
357 #endif
358 
359 	intr = ifpga_intr_establish(ih, level, func, arg);
360 
361 	return intr;
362 }
363 
364 void
ifpga_pci_intr_disestablish(void * pcv,void * cookie)365 ifpga_pci_intr_disestablish(void *pcv, void *cookie)
366 {
367 #ifdef PCI_DEBUG
368 	printf("ifpga_pci_intr_disestablish(pcv=%p, cookie=%p)\n",
369 	    pcv, cookie);
370 #endif
371 	ifpga_intr_disestablish(cookie);
372 }
373