1 /* $OpenBSD: if_urtw.c,v 1.74 2024/09/01 03:09:00 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Martynas Venckus <martynas@openbsd.org> 5 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "bpfilter.h" 21 22 #include <sys/param.h> 23 #include <sys/sockio.h> 24 #include <sys/mbuf.h> 25 #include <sys/systm.h> 26 #include <sys/timeout.h> 27 #include <sys/device.h> 28 #include <sys/endian.h> 29 30 #if NBPFILTER > 0 31 #include <net/bpf.h> 32 #endif 33 #include <net/if.h> 34 #include <net/if_dl.h> 35 #include <net/if_media.h> 36 37 #include <netinet/in.h> 38 #include <netinet/if_ether.h> 39 40 #include <net80211/ieee80211_var.h> 41 #include <net80211/ieee80211_radiotap.h> 42 43 #include <dev/usb/usb.h> 44 #include <dev/usb/usbdi.h> 45 #include <dev/usb/usbdi_util.h> 46 #include <dev/usb/usbdevs.h> 47 48 #include <dev/usb/if_urtwreg.h> 49 50 #ifdef URTW_DEBUG 51 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 52 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 53 int urtw_debug = 0; 54 #else 55 #define DPRINTF(x) 56 #define DPRINTFN(n, x) 57 #endif 58 59 /* 60 * Recognized device vendors/products. 61 */ 62 static const struct urtw_type { 63 struct usb_devno dev; 64 uint8_t rev; 65 } urtw_devs[] = { 66 #define URTW_DEV_RTL8187(v, p) \ 67 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 68 #define URTW_DEV_RTL8187B(v, p) \ 69 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 70 /* Realtek RTL8187 devices. */ 71 URTW_DEV_RTL8187(ASUS, P5B_WIFI), 72 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 73 URTW_DEV_RTL8187(LINKSYS4, WUSB54GCV2), 74 URTW_DEV_RTL8187(LOGITEC, RTL8187), 75 URTW_DEV_RTL8187(NETGEAR, WG111V2), 76 URTW_DEV_RTL8187(REALTEK, RTL8187), 77 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 78 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 79 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 80 /* Realtek RTL8187B devices. */ 81 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 82 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 83 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 84 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 85 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 86 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 87 #undef URTW_DEV_RTL8187 88 #undef URTW_DEV_RTL8187B 89 }; 90 #define urtw_lookup(v, p) \ 91 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 92 93 /* 94 * Helper read/write macros. 95 */ 96 #define urtw_read8_m(sc, val, data) do { \ 97 error = urtw_read8_c(sc, val, data, 0); \ 98 if (error != 0) \ 99 goto fail; \ 100 } while (0) 101 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 102 error = urtw_read8_c(sc, val, data, idx); \ 103 if (error != 0) \ 104 goto fail; \ 105 } while (0) 106 #define urtw_write8_m(sc, val, data) do { \ 107 error = urtw_write8_c(sc, val, data, 0); \ 108 if (error != 0) \ 109 goto fail; \ 110 } while (0) 111 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 112 error = urtw_write8_c(sc, val, data, idx); \ 113 if (error != 0) \ 114 goto fail; \ 115 } while (0) 116 #define urtw_read16_m(sc, val, data) do { \ 117 error = urtw_read16_c(sc, val, data, 0); \ 118 if (error != 0) \ 119 goto fail; \ 120 } while (0) 121 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 122 error = urtw_read16_c(sc, val, data, idx); \ 123 if (error != 0) \ 124 goto fail; \ 125 } while (0) 126 #define urtw_write16_m(sc, val, data) do { \ 127 error = urtw_write16_c(sc, val, data, 0); \ 128 if (error != 0) \ 129 goto fail; \ 130 } while (0) 131 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 132 error = urtw_write16_c(sc, val, data, idx); \ 133 if (error != 0) \ 134 goto fail; \ 135 } while (0) 136 #define urtw_read32_m(sc, val, data) do { \ 137 error = urtw_read32_c(sc, val, data, 0); \ 138 if (error != 0) \ 139 goto fail; \ 140 } while (0) 141 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 142 error = urtw_read32_c(sc, val, data, idx); \ 143 if (error != 0) \ 144 goto fail; \ 145 } while (0) 146 #define urtw_write32_m(sc, val, data) do { \ 147 error = urtw_write32_c(sc, val, data, 0); \ 148 if (error != 0) \ 149 goto fail; \ 150 } while (0) 151 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 152 error = urtw_write32_c(sc, val, data, idx); \ 153 if (error != 0) \ 154 goto fail; \ 155 } while (0) 156 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 157 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 158 if (error != 0) \ 159 goto fail; \ 160 } while (0) 161 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 162 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 163 if (error != 0) \ 164 goto fail; \ 165 } while (0) 166 #define urtw_8225_write(sc, val, data) do { \ 167 error = urtw_8225_write_c(sc, val, data); \ 168 if (error != 0) \ 169 goto fail; \ 170 } while (0) 171 172 struct urtw_pair { 173 uint32_t reg; 174 uint32_t val; 175 }; 176 177 struct urtw_pair_idx { 178 uint8_t reg; 179 uint8_t val; 180 uint8_t idx; 181 }; 182 183 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 184 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 185 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 186 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 187 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 188 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 189 { 0xff, 0x00, 0 }, 190 191 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 192 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 193 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 194 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 195 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 196 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 197 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 198 { 0xf8, 0x08, 1 }, 199 200 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 201 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 202 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 203 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 204 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 205 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 206 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 207 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 208 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 209 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 210 211 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 212 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 213 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 214 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 215 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 216 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 217 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 218 219 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 220 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 221 }; 222 223 static uint8_t urtw_8225_agc[] = { 224 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 225 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 226 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 227 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 228 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 229 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 230 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 231 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 232 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 233 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 234 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 235 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 236 }; 237 238 static uint32_t urtw_8225_channel[] = { 239 0x0000, /* dummy channel 0 */ 240 0x085c, /* 1 */ 241 0x08dc, /* 2 */ 242 0x095c, /* 3 */ 243 0x09dc, /* 4 */ 244 0x0a5c, /* 5 */ 245 0x0adc, /* 6 */ 246 0x0b5c, /* 7 */ 247 0x0bdc, /* 8 */ 248 0x0c5c, /* 9 */ 249 0x0cdc, /* 10 */ 250 0x0d5c, /* 11 */ 251 0x0ddc, /* 12 */ 252 0x0e5c, /* 13 */ 253 0x0f72, /* 14 */ 254 }; 255 256 static uint8_t urtw_8225_gain[] = { 257 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 258 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 259 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 260 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 261 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 262 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 263 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 264 }; 265 266 static struct urtw_pair urtw_8225_rf_part1[] = { 267 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 268 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 269 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 270 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 271 }; 272 273 static struct urtw_pair urtw_8225_rf_part2[] = { 274 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 275 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 276 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 277 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 278 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 279 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 280 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 281 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 282 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 283 { 0x27, 0x88 } 284 }; 285 286 static struct urtw_pair urtw_8225_rf_part3[] = { 287 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 288 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 289 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 290 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 291 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 292 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 293 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 294 }; 295 296 static uint16_t urtw_8225_rxgain[] = { 297 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 298 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 299 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 300 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 301 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 302 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 303 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 304 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 305 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 306 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 307 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 308 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 309 }; 310 311 static uint8_t urtw_8225_threshold[] = { 312 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 313 }; 314 315 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 316 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 317 }; 318 319 static uint8_t urtw_8225_txpwr_cck[] = { 320 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 321 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 322 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 323 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 324 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 325 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 326 }; 327 328 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 329 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 330 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 331 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 332 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 333 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 334 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 335 }; 336 337 static uint8_t urtw_8225_txpwr_ofdm[] = { 338 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 339 }; 340 341 static uint8_t urtw_8225v2_agc[] = { 342 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 343 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 344 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 345 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 346 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 347 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 348 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 349 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 350 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 351 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 352 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 353 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 354 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 355 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 356 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 357 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 358 }; 359 360 static uint8_t urtw_8225v2_ofdm[] = { 361 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 362 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 363 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 364 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 365 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 366 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 367 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 368 0x6d, 0x3c, 0xfb, 0x07 369 }; 370 371 static uint8_t urtw_8225v2_gain_bg[] = { 372 0x23, 0x15, 0xa5, /* -82-1dbm */ 373 0x23, 0x15, 0xb5, /* -82-2dbm */ 374 0x23, 0x15, 0xc5, /* -82-3dbm */ 375 0x33, 0x15, 0xc5, /* -78dbm */ 376 0x43, 0x15, 0xc5, /* -74dbm */ 377 0x53, 0x15, 0xc5, /* -70dbm */ 378 0x63, 0x15, 0xc5, /* -66dbm */ 379 }; 380 381 static struct urtw_pair urtw_8225v2_rf_part1[] = { 382 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 383 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 384 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 385 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 386 }; 387 388 static struct urtw_pair urtw_8225v2_rf_part2[] = { 389 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 390 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 391 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 392 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 393 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 394 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 395 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 396 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 397 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 398 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 399 }; 400 401 static struct urtw_pair urtw_8225v2_rf_part3[] = { 402 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 403 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 404 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 405 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 406 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 407 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 408 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 409 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 410 }; 411 412 static uint16_t urtw_8225v2_rxgain[] = { 413 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 414 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 415 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 416 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 417 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 418 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 419 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 420 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 421 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 422 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 423 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 424 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 425 }; 426 427 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 428 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 429 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 430 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 431 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 432 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 433 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 434 }; 435 436 static uint8_t urtw_8225v2_txpwr_cck[] = { 437 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 438 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 439 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 440 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 441 }; 442 443 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 444 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 445 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 446 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 447 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 448 }; 449 450 static struct urtw_pair urtw_8225v2_b_rf[] = { 451 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 452 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 453 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 454 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 455 { 0x00, 0x01b7 } 456 }; 457 458 static struct urtw_pair urtw_ratetable[] = { 459 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 460 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 461 { 96, 10 }, { 108, 11 } 462 }; 463 464 int urtw_init(struct ifnet *); 465 void urtw_stop(struct ifnet *, int); 466 int urtw_ioctl(struct ifnet *, u_long, caddr_t); 467 void urtw_start(struct ifnet *); 468 int urtw_alloc_rx_data_list(struct urtw_softc *); 469 void urtw_free_rx_data_list(struct urtw_softc *); 470 int urtw_alloc_tx_data_list(struct urtw_softc *); 471 void urtw_free_tx_data_list(struct urtw_softc *); 472 void urtw_rxeof(struct usbd_xfer *, void *, 473 usbd_status); 474 int urtw_tx_start(struct urtw_softc *, 475 struct ieee80211_node *, struct mbuf *, int); 476 void urtw_txeof_low(struct usbd_xfer *, void *, 477 usbd_status); 478 void urtw_txeof_normal(struct usbd_xfer *, void *, 479 usbd_status); 480 void urtw_next_scan(void *); 481 void urtw_task(void *); 482 void urtw_ledusbtask(void *); 483 void urtw_ledtask(void *); 484 int urtw_media_change(struct ifnet *); 485 int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 486 void urtw_watchdog(struct ifnet *); 487 void urtw_set_multi(struct urtw_softc *); 488 void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 489 int urtw_isbmode(uint16_t); 490 uint16_t urtw_rate2rtl(int rate); 491 uint16_t urtw_rtl2rate(int); 492 usbd_status urtw_set_rate(struct urtw_softc *); 493 usbd_status urtw_update_msr(struct urtw_softc *); 494 usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 495 usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 496 usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 497 usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 498 usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 499 usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 500 usbd_status urtw_eprom_cs(struct urtw_softc *, int); 501 usbd_status urtw_eprom_ck(struct urtw_softc *); 502 usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 503 int); 504 usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 505 uint32_t *); 506 usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 507 usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 508 usbd_status urtw_get_macaddr(struct urtw_softc *); 509 usbd_status urtw_get_txpwr(struct urtw_softc *); 510 usbd_status urtw_get_rfchip(struct urtw_softc *); 511 usbd_status urtw_led_init(struct urtw_softc *); 512 usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 513 usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 514 usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 515 usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 516 uint32_t); 517 usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 518 uint32_t); 519 usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 520 usbd_status urtw_8225_usb_init(struct urtw_softc *); 521 usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 522 usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 523 uint16_t); 524 usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 525 usbd_status urtw_8225_rf_init(struct urtw_rf *); 526 usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 527 usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 528 usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 529 usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 530 usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 531 usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 532 usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 533 usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 534 usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 535 usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 536 usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 537 usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 538 usbd_status urtw_open_pipes(struct urtw_softc *); 539 usbd_status urtw_close_pipes(struct urtw_softc *); 540 usbd_status urtw_intr_enable(struct urtw_softc *); 541 usbd_status urtw_intr_disable(struct urtw_softc *); 542 usbd_status urtw_reset(struct urtw_softc *); 543 usbd_status urtw_led_on(struct urtw_softc *, int); 544 usbd_status urtw_led_ctl(struct urtw_softc *, int); 545 usbd_status urtw_led_blink(struct urtw_softc *); 546 usbd_status urtw_led_mode0(struct urtw_softc *, int); 547 usbd_status urtw_led_mode1(struct urtw_softc *, int); 548 usbd_status urtw_led_mode2(struct urtw_softc *, int); 549 usbd_status urtw_led_mode3(struct urtw_softc *, int); 550 usbd_status urtw_rx_setconf(struct urtw_softc *); 551 usbd_status urtw_rx_enable(struct urtw_softc *); 552 usbd_status urtw_tx_enable(struct urtw_softc *); 553 usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 554 usbd_status urtw_8187b_reset(struct urtw_softc *); 555 int urtw_8187b_init(struct ifnet *); 556 usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 557 usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 558 usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 559 usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 560 usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 561 usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 562 int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 563 int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 564 565 int urtw_match(struct device *, void *, void *); 566 void urtw_attach(struct device *, struct device *, void *); 567 int urtw_detach(struct device *, int); 568 569 struct cfdriver urtw_cd = { 570 NULL, "urtw", DV_IFNET 571 }; 572 573 const struct cfattach urtw_ca = { 574 sizeof(struct urtw_softc), urtw_match, urtw_attach, urtw_detach 575 }; 576 577 int 578 urtw_match(struct device *parent, void *match, void *aux) 579 { 580 struct usb_attach_arg *uaa = aux; 581 582 if (uaa->iface == NULL || uaa->configno != 1) 583 return (UMATCH_NONE); 584 585 return ((urtw_lookup(uaa->vendor, uaa->product) != NULL) ? 586 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 587 } 588 589 void 590 urtw_attach(struct device *parent, struct device *self, void *aux) 591 { 592 struct urtw_softc *sc = (struct urtw_softc *)self; 593 struct usb_attach_arg *uaa = aux; 594 struct ieee80211com *ic = &sc->sc_ic; 595 struct ifnet *ifp = &ic->ic_if; 596 usbd_status error; 597 uint8_t data8; 598 uint32_t data; 599 int i; 600 601 sc->sc_udev = uaa->device; 602 sc->sc_iface = uaa->iface; 603 sc->sc_hwrev = urtw_lookup(uaa->vendor, uaa->product)->rev; 604 605 printf("%s: ", sc->sc_dev.dv_xname); 606 607 if (sc->sc_hwrev & URTW_HWREV_8187) { 608 urtw_read32_m(sc, URTW_TX_CONF, &data); 609 data &= URTW_TX_HWREV_MASK; 610 switch (data) { 611 case URTW_TX_HWREV_8187_D: 612 sc->sc_hwrev |= URTW_HWREV_8187_D; 613 printf("RTL8187 rev D"); 614 break; 615 case URTW_TX_HWREV_8187B_D: 616 /* 617 * Detect Realtek RTL8187B devices that use 618 * USB IDs of RTL8187. 619 */ 620 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 621 printf("RTL8187B rev B (early)"); 622 break; 623 default: 624 sc->sc_hwrev |= URTW_HWREV_8187_B; 625 printf("RTL8187 rev 0x%02x", data >> 25); 626 break; 627 } 628 } else { 629 /* RTL8187B hwrev register. */ 630 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 631 switch (data8) { 632 case URTW_8187B_HWREV_8187B_B: 633 sc->sc_hwrev |= URTW_HWREV_8187B_B; 634 printf("RTL8187B rev B"); 635 break; 636 case URTW_8187B_HWREV_8187B_D: 637 sc->sc_hwrev |= URTW_HWREV_8187B_D; 638 printf("RTL8187B rev D"); 639 break; 640 case URTW_8187B_HWREV_8187B_E: 641 sc->sc_hwrev |= URTW_HWREV_8187B_E; 642 printf("RTL8187B rev E"); 643 break; 644 default: 645 sc->sc_hwrev |= URTW_HWREV_8187B_B; 646 printf("RTL8187B rev 0x%02x", data8); 647 break; 648 } 649 } 650 651 urtw_read32_m(sc, URTW_RX, &data); 652 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 653 URTW_EEPROM_93C46; 654 655 error = urtw_get_rfchip(sc); 656 if (error != 0) 657 goto fail; 658 error = urtw_get_macaddr(sc); 659 if (error != 0) 660 goto fail; 661 error = urtw_get_txpwr(sc); 662 if (error != 0) 663 goto fail; 664 error = urtw_led_init(sc); /* XXX incomplete */ 665 if (error != 0) 666 goto fail; 667 668 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 669 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 670 sc->sc_currate = 3; 671 /* XXX for what? */ 672 sc->sc_preamble_mode = 2; 673 674 usb_init_task(&sc->sc_task, urtw_task, sc, USB_TASK_TYPE_GENERIC); 675 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc, 676 USB_TASK_TYPE_GENERIC); 677 timeout_set(&sc->scan_to, urtw_next_scan, sc); 678 timeout_set(&sc->sc_led_ch, urtw_ledtask, sc); 679 680 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 681 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 682 ic->ic_state = IEEE80211_S_INIT; 683 684 /* set device capabilities */ 685 ic->ic_caps = 686 IEEE80211_C_MONITOR | /* monitor mode supported */ 687 IEEE80211_C_TXPMGT | /* tx power management */ 688 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 689 IEEE80211_C_SHSLOT | /* short slot time supported */ 690 IEEE80211_C_WEP | /* s/w WEP */ 691 IEEE80211_C_RSN; /* WPA/RSN */ 692 693 /* set supported .11b and .11g rates */ 694 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 695 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 696 697 /* set supported .11b and .11g channels (1 through 14) */ 698 for (i = 1; i <= 14; i++) { 699 ic->ic_channels[i].ic_freq = 700 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 701 ic->ic_channels[i].ic_flags = 702 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 703 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 704 } 705 706 ifp->if_softc = sc; 707 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 708 if (sc->sc_hwrev & URTW_HWREV_8187) { 709 sc->sc_init = urtw_init; 710 } else { 711 sc->sc_init = urtw_8187b_init; 712 } 713 ifp->if_ioctl = urtw_ioctl; 714 ifp->if_start = urtw_start; 715 ifp->if_watchdog = urtw_watchdog; 716 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 717 718 if_attach(ifp); 719 ieee80211_ifattach(ifp); 720 721 /* override state transition machine */ 722 sc->sc_newstate = ic->ic_newstate; 723 ic->ic_newstate = urtw_newstate; 724 ieee80211_media_init(ifp, urtw_media_change, ieee80211_media_status); 725 726 #if NBPFILTER > 0 727 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 728 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 729 730 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 731 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 732 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 733 734 sc->sc_txtap_len = sizeof sc->sc_txtapu; 735 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 736 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 737 #endif 738 739 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 740 741 return; 742 fail: 743 printf(": %s failed!\n", __func__); 744 } 745 746 int 747 urtw_detach(struct device *self, int flags) 748 { 749 struct urtw_softc *sc = (struct urtw_softc *)self; 750 struct ifnet *ifp = &sc->sc_ic.ic_if; 751 int s; 752 753 s = splusb(); 754 755 if (timeout_initialized(&sc->scan_to)) 756 timeout_del(&sc->scan_to); 757 if (timeout_initialized(&sc->sc_led_ch)) 758 timeout_del(&sc->sc_led_ch); 759 760 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 761 usb_rem_wait_task(sc->sc_udev, &sc->sc_ledtask); 762 763 usbd_ref_wait(sc->sc_udev); 764 765 if (ifp->if_softc != NULL) { 766 ieee80211_ifdetach(ifp); /* free all nodes */ 767 if_detach(ifp); 768 } 769 770 /* abort and free xfers */ 771 urtw_free_tx_data_list(sc); 772 urtw_free_rx_data_list(sc); 773 urtw_close_pipes(sc); 774 775 splx(s); 776 777 return (0); 778 } 779 780 usbd_status 781 urtw_close_pipes(struct urtw_softc *sc) 782 { 783 usbd_status error = 0; 784 785 if (sc->sc_rxpipe != NULL) { 786 error = usbd_close_pipe(sc->sc_rxpipe); 787 if (error != 0) 788 goto fail; 789 sc->sc_rxpipe = NULL; 790 } 791 if (sc->sc_txpipe_low != NULL) { 792 error = usbd_close_pipe(sc->sc_txpipe_low); 793 if (error != 0) 794 goto fail; 795 sc->sc_txpipe_low = NULL; 796 } 797 if (sc->sc_txpipe_normal != NULL) { 798 error = usbd_close_pipe(sc->sc_txpipe_normal); 799 if (error != 0) 800 goto fail; 801 sc->sc_txpipe_normal = NULL; 802 } 803 fail: 804 return (error); 805 } 806 807 usbd_status 808 urtw_open_pipes(struct urtw_softc *sc) 809 { 810 usbd_status error; 811 812 /* 813 * NB: there is no way to distinguish each pipes so we need to hardcode 814 * pipe numbers 815 */ 816 817 /* tx pipe - low priority packets */ 818 if (sc->sc_hwrev & URTW_HWREV_8187) 819 error = usbd_open_pipe(sc->sc_iface, 0x2, 820 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 821 else 822 error = usbd_open_pipe(sc->sc_iface, 0x6, 823 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 824 if (error != 0) { 825 printf("%s: could not open Tx low pipe: %s\n", 826 sc->sc_dev.dv_xname, usbd_errstr(error)); 827 goto fail; 828 } 829 /* tx pipe - normal priority packets */ 830 if (sc->sc_hwrev & URTW_HWREV_8187) 831 error = usbd_open_pipe(sc->sc_iface, 0x3, 832 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 833 else 834 error = usbd_open_pipe(sc->sc_iface, 0x7, 835 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 836 if (error != 0) { 837 printf("%s: could not open Tx normal pipe: %s\n", 838 sc->sc_dev.dv_xname, usbd_errstr(error)); 839 goto fail; 840 } 841 /* rx pipe */ 842 if (sc->sc_hwrev & URTW_HWREV_8187) 843 error = usbd_open_pipe(sc->sc_iface, 0x81, 844 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 845 else 846 error = usbd_open_pipe(sc->sc_iface, 0x83, 847 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 848 if (error != 0) { 849 printf("%s: could not open Rx pipe: %s\n", 850 sc->sc_dev.dv_xname, usbd_errstr(error)); 851 goto fail; 852 } 853 854 return (0); 855 fail: 856 (void)urtw_close_pipes(sc); 857 return (error); 858 } 859 860 int 861 urtw_alloc_rx_data_list(struct urtw_softc *sc) 862 { 863 int i, error; 864 865 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 866 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 867 868 data->sc = sc; 869 870 data->xfer = usbd_alloc_xfer(sc->sc_udev); 871 if (data->xfer == NULL) { 872 printf("%s: could not allocate rx xfer\n", 873 sc->sc_dev.dv_xname); 874 error = ENOMEM; 875 goto fail; 876 } 877 878 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) { 879 printf("%s: could not allocate rx buffer\n", 880 sc->sc_dev.dv_xname); 881 error = ENOMEM; 882 goto fail; 883 } 884 885 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 886 if (data->m == NULL) { 887 printf("%s: could not allocate rx mbuf\n", 888 sc->sc_dev.dv_xname); 889 error = ENOMEM; 890 goto fail; 891 } 892 MCLGET(data->m, M_DONTWAIT); 893 if (!(data->m->m_flags & M_EXT)) { 894 printf("%s: could not allocate rx mbuf cluster\n", 895 sc->sc_dev.dv_xname); 896 error = ENOMEM; 897 goto fail; 898 } 899 data->buf = mtod(data->m, uint8_t *); 900 } 901 902 return (0); 903 904 fail: 905 urtw_free_rx_data_list(sc); 906 return (error); 907 } 908 909 void 910 urtw_free_rx_data_list(struct urtw_softc *sc) 911 { 912 int i; 913 914 /* Make sure no transfers are pending. */ 915 if (sc->sc_rxpipe != NULL) 916 usbd_abort_pipe(sc->sc_rxpipe); 917 918 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 919 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 920 921 if (data->xfer != NULL) { 922 usbd_free_xfer(data->xfer); 923 data->xfer = NULL; 924 } 925 if (data->m != NULL) { 926 m_freem(data->m); 927 data->m = NULL; 928 } 929 } 930 } 931 932 int 933 urtw_alloc_tx_data_list(struct urtw_softc *sc) 934 { 935 int i, error; 936 937 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 938 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 939 940 data->sc = sc; 941 data->ni = NULL; 942 943 data->xfer = usbd_alloc_xfer(sc->sc_udev); 944 if (data->xfer == NULL) { 945 printf("%s: could not allocate tx xfer\n", 946 sc->sc_dev.dv_xname); 947 error = ENOMEM; 948 goto fail; 949 } 950 951 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE); 952 if (data->buf == NULL) { 953 printf("%s: could not allocate tx buffer\n", 954 sc->sc_dev.dv_xname); 955 error = ENOMEM; 956 goto fail; 957 } 958 959 if (((unsigned long)data->buf) % 4) 960 printf("%s: warn: unaligned buffer %p\n", 961 sc->sc_dev.dv_xname, data->buf); 962 } 963 964 return (0); 965 966 fail: 967 urtw_free_tx_data_list(sc); 968 return (error); 969 } 970 971 void 972 urtw_free_tx_data_list(struct urtw_softc *sc) 973 { 974 struct ieee80211com *ic = &sc->sc_ic; 975 int i; 976 977 /* Make sure no transfers are pending. */ 978 if (sc->sc_txpipe_low != NULL) 979 usbd_abort_pipe(sc->sc_txpipe_low); 980 if (sc->sc_txpipe_normal != NULL) 981 usbd_abort_pipe(sc->sc_txpipe_normal); 982 983 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 984 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 985 986 if (data->xfer != NULL) { 987 usbd_free_xfer(data->xfer); 988 data->xfer = NULL; 989 } 990 if (data->ni != NULL) { 991 ieee80211_release_node(ic, data->ni); 992 data->ni = NULL; 993 } 994 } 995 } 996 997 int 998 urtw_media_change(struct ifnet *ifp) 999 { 1000 struct urtw_softc *sc = ifp->if_softc; 1001 int error; 1002 1003 error = ieee80211_media_change(ifp); 1004 if (error != ENETRESET) 1005 return (error); 1006 1007 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) 1008 error = sc->sc_init(ifp); 1009 1010 return (error); 1011 } 1012 1013 int 1014 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1015 { 1016 struct urtw_softc *sc = ic->ic_if.if_softc; 1017 1018 usb_rem_task(sc->sc_udev, &sc->sc_task); 1019 timeout_del(&sc->scan_to); 1020 1021 /* do it in a process context */ 1022 sc->sc_state = nstate; 1023 sc->sc_arg = arg; 1024 usb_add_task(sc->sc_udev, &sc->sc_task); 1025 1026 return (0); 1027 } 1028 1029 usbd_status 1030 urtw_led_init(struct urtw_softc *sc) 1031 { 1032 uint32_t rev; 1033 usbd_status error; 1034 1035 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1036 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1037 if (error != 0) 1038 goto fail; 1039 1040 switch (rev & URTW_EPROM_CID_MASK) { 1041 case URTW_EPROM_CID_ALPHA0: 1042 sc->sc_strategy = URTW_SW_LED_MODE1; 1043 break; 1044 case URTW_EPROM_CID_SERCOMM_PS: 1045 sc->sc_strategy = URTW_SW_LED_MODE3; 1046 break; 1047 case URTW_EPROM_CID_HW_LED: 1048 sc->sc_strategy = URTW_HW_LED; 1049 break; 1050 case URTW_EPROM_CID_RSVD0: 1051 case URTW_EPROM_CID_RSVD1: 1052 default: 1053 sc->sc_strategy = URTW_SW_LED_MODE0; 1054 break; 1055 } 1056 1057 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1058 1059 fail: 1060 return (error); 1061 } 1062 1063 usbd_status 1064 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1065 uint16_t data) 1066 { 1067 usb_device_request_t req; 1068 1069 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1070 req.bRequest = URTW_8187_SETREGS_REQ; 1071 USETW(req.wValue, addr); 1072 USETW(req.wIndex, index); 1073 USETW(req.wLength, sizeof(uint16_t)); 1074 1075 data = htole16(data); 1076 return (usbd_do_request(sc->sc_udev, &req, &data)); 1077 } 1078 1079 usbd_status 1080 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1081 { 1082 int i; 1083 int16_t bit; 1084 uint8_t rlen = 12, wlen = 6; 1085 uint16_t o1, o2, o3, tmp; 1086 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1087 uint32_t mask = 0x80000000, value = 0; 1088 usbd_status error; 1089 1090 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1091 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1092 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1093 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1094 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1095 o1 &= ~0xf; 1096 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1097 DELAY(5); 1098 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1099 DELAY(5); 1100 1101 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1102 bit = ((d2w & mask) != 0) ? 1 : 0; 1103 1104 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1105 DELAY(2); 1106 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1107 URTW_BB_HOST_BANG_CLK); 1108 DELAY(2); 1109 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1110 URTW_BB_HOST_BANG_CLK); 1111 DELAY(2); 1112 mask = mask >> 1; 1113 if (i == 2) 1114 break; 1115 bit = ((d2w & mask) != 0) ? 1 : 0; 1116 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1117 URTW_BB_HOST_BANG_CLK); 1118 DELAY(2); 1119 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1120 URTW_BB_HOST_BANG_CLK); 1121 DELAY(2); 1122 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1123 DELAY(1); 1124 } 1125 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1126 URTW_BB_HOST_BANG_CLK); 1127 DELAY(2); 1128 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1129 DELAY(2); 1130 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1131 DELAY(2); 1132 1133 mask = 0x800; 1134 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1135 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1136 o1 | URTW_BB_HOST_BANG_RW); 1137 DELAY(2); 1138 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1139 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1140 DELAY(2); 1141 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1142 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1143 DELAY(2); 1144 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1145 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1146 DELAY(2); 1147 1148 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1149 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1150 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1151 o1 | URTW_BB_HOST_BANG_RW); 1152 DELAY(2); 1153 } 1154 1155 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1156 URTW_BB_HOST_BANG_RW); 1157 DELAY(2); 1158 1159 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1160 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1161 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1162 1163 if (data != NULL) 1164 *data = value; 1165 fail: 1166 return (error); 1167 } 1168 1169 usbd_status 1170 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1171 { 1172 uint16_t d80, d82, d84; 1173 usbd_status error; 1174 1175 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1176 d80 &= 0xfff3; 1177 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1178 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1179 d84 &= 0xfff0; 1180 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1181 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1182 DELAY(10); 1183 1184 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1185 DELAY(2); 1186 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1187 DELAY(10); 1188 1189 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1190 if (error != 0) 1191 goto fail; 1192 1193 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1194 DELAY(10); 1195 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1196 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1197 usbd_delay_ms(sc->sc_udev, 2); 1198 fail: 1199 return (error); 1200 } 1201 1202 usbd_status 1203 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1204 { 1205 uint32_t data; 1206 usbd_status error; 1207 1208 *ret = 1; 1209 1210 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1211 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1212 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1213 usbd_delay_ms(sc->sc_udev, 500); 1214 1215 urtw_8225_write(sc, 0x0, 0x1b7); 1216 1217 error = urtw_8225_read(sc, 0x8, &data); 1218 if (error != 0) 1219 goto fail; 1220 if (data != 0x588) 1221 *ret = 0; 1222 else { 1223 error = urtw_8225_read(sc, 0x9, &data); 1224 if (error != 0) 1225 goto fail; 1226 if (data != 0x700) 1227 *ret = 0; 1228 } 1229 1230 urtw_8225_write(sc, 0x0, 0xb7); 1231 fail: 1232 return (error); 1233 } 1234 1235 usbd_status 1236 urtw_get_rfchip(struct urtw_softc *sc) 1237 { 1238 struct urtw_rf *rf = &sc->sc_rf; 1239 int ret; 1240 uint32_t data; 1241 usbd_status error; 1242 1243 rf->rf_sc = sc; 1244 1245 if (sc->sc_hwrev & URTW_HWREV_8187) { 1246 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1247 if (error != 0) 1248 goto fail; 1249 switch (data & 0xff) { 1250 case URTW_EPROM_RFCHIPID_RTL8225U: 1251 error = urtw_8225_isv2(sc, &ret); 1252 if (error != 0) 1253 goto fail; 1254 if (ret == 0) { 1255 rf->init = urtw_8225_rf_init; 1256 rf->set_chan = urtw_8225_rf_set_chan; 1257 rf->set_sens = urtw_8225_rf_set_sens; 1258 printf(", RFv1"); 1259 } else { 1260 rf->init = urtw_8225v2_rf_init; 1261 rf->set_chan = urtw_8225v2_rf_set_chan; 1262 rf->set_sens = NULL; 1263 printf(", RFv2"); 1264 } 1265 break; 1266 default: 1267 goto fail; 1268 } 1269 } else { 1270 rf->init = urtw_8225v2_b_rf_init; 1271 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1272 rf->set_sens = NULL; 1273 } 1274 1275 rf->max_sens = URTW_8225_RF_MAX_SENS; 1276 rf->sens = URTW_8225_RF_DEF_SENS; 1277 1278 return (0); 1279 1280 fail: 1281 printf("unsupported RF chip %d", data & 0xff); 1282 return (error); 1283 } 1284 1285 usbd_status 1286 urtw_get_txpwr(struct urtw_softc *sc) 1287 { 1288 int i, j; 1289 uint32_t data; 1290 usbd_status error; 1291 1292 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1293 if (error != 0) 1294 goto fail; 1295 sc->sc_txpwr_cck_base = data & 0xf; 1296 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1297 1298 for (i = 1, j = 0; i < 6; i += 2, j++) { 1299 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1300 if (error != 0) 1301 goto fail; 1302 sc->sc_txpwr_cck[i] = data & 0xf; 1303 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1304 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1305 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1306 } 1307 for (i = 1, j = 0; i < 4; i += 2, j++) { 1308 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1309 if (error != 0) 1310 goto fail; 1311 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1312 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1313 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1314 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1315 } 1316 if (sc->sc_hwrev & URTW_HWREV_8187) { 1317 for (i = 1, j = 0; i < 4; i += 2, j++) { 1318 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1319 &data); 1320 if (error != 0) 1321 goto fail; 1322 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1323 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1324 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1325 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1326 (data & 0xf000) >> 12; 1327 } 1328 } else { 1329 /* Channel 11. */ 1330 error = urtw_eprom_read32(sc, 0x1b, &data); 1331 if (error != 0) 1332 goto fail; 1333 sc->sc_txpwr_cck[11] = data & 0xf; 1334 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1335 1336 /* Channel 12. */ 1337 error = urtw_eprom_read32(sc, 0xa, &data); 1338 if (error != 0) 1339 goto fail; 1340 sc->sc_txpwr_cck[12] = data & 0xf; 1341 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1342 1343 /* Channel 13, 14. */ 1344 error = urtw_eprom_read32(sc, 0x1c, &data); 1345 if (error != 0) 1346 goto fail; 1347 sc->sc_txpwr_cck[13] = data & 0xf; 1348 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1349 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1350 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1351 } 1352 fail: 1353 return (error); 1354 } 1355 1356 usbd_status 1357 urtw_get_macaddr(struct urtw_softc *sc) 1358 { 1359 struct ieee80211com *ic = &sc->sc_ic; 1360 usbd_status error; 1361 uint32_t data; 1362 1363 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1364 if (error != 0) 1365 goto fail; 1366 ic->ic_myaddr[0] = data & 0xff; 1367 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1368 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1369 if (error != 0) 1370 goto fail; 1371 ic->ic_myaddr[2] = data & 0xff; 1372 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1373 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1374 if (error != 0) 1375 goto fail; 1376 ic->ic_myaddr[4] = data & 0xff; 1377 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1378 fail: 1379 return (error); 1380 } 1381 1382 usbd_status 1383 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1384 { 1385 #define URTW_READCMD_LEN 3 1386 int addrlen, i; 1387 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1388 usbd_status error; 1389 1390 /* NB: make sure the buffer is initialized */ 1391 *data = 0; 1392 1393 /* enable EPROM programming */ 1394 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1395 DELAY(URTW_EPROM_DELAY); 1396 1397 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1398 if (error != 0) 1399 goto fail; 1400 error = urtw_eprom_ck(sc); 1401 if (error != 0) 1402 goto fail; 1403 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1404 if (error != 0) 1405 goto fail; 1406 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1407 addrlen = 8; 1408 addrstr[0] = addr & (1 << 7); 1409 addrstr[1] = addr & (1 << 6); 1410 addrstr[2] = addr & (1 << 5); 1411 addrstr[3] = addr & (1 << 4); 1412 addrstr[4] = addr & (1 << 3); 1413 addrstr[5] = addr & (1 << 2); 1414 addrstr[6] = addr & (1 << 1); 1415 addrstr[7] = addr & (1 << 0); 1416 } else { 1417 addrlen=6; 1418 addrstr[0] = addr & (1 << 5); 1419 addrstr[1] = addr & (1 << 4); 1420 addrstr[2] = addr & (1 << 3); 1421 addrstr[3] = addr & (1 << 2); 1422 addrstr[4] = addr & (1 << 1); 1423 addrstr[5] = addr & (1 << 0); 1424 } 1425 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1426 if (error != 0) 1427 goto fail; 1428 1429 error = urtw_eprom_writebit(sc, 0); 1430 if (error != 0) 1431 goto fail; 1432 1433 for (i = 0; i < 16; i++) { 1434 error = urtw_eprom_ck(sc); 1435 if (error != 0) 1436 goto fail; 1437 error = urtw_eprom_readbit(sc, &data16); 1438 if (error != 0) 1439 goto fail; 1440 1441 (*data) |= (data16 << (15 - i)); 1442 } 1443 1444 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1445 if (error != 0) 1446 goto fail; 1447 error = urtw_eprom_ck(sc); 1448 if (error != 0) 1449 goto fail; 1450 1451 /* now disable EPROM programming */ 1452 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1453 fail: 1454 return (error); 1455 #undef URTW_READCMD_LEN 1456 } 1457 1458 usbd_status 1459 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1460 { 1461 uint8_t data8; 1462 usbd_status error; 1463 1464 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1465 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1466 DELAY(URTW_EPROM_DELAY); 1467 1468 fail: 1469 return (error); 1470 } 1471 1472 usbd_status 1473 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1474 { 1475 int i = 0; 1476 usbd_status error = 0; 1477 1478 for (i = 0; i < buflen; i++) { 1479 error = urtw_eprom_writebit(sc, buf[i]); 1480 if (error != 0) 1481 goto fail; 1482 error = urtw_eprom_ck(sc); 1483 if (error != 0) 1484 goto fail; 1485 } 1486 fail: 1487 return (error); 1488 } 1489 1490 usbd_status 1491 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1492 { 1493 uint8_t data; 1494 usbd_status error; 1495 1496 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1497 if (bit != 0) 1498 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1499 else 1500 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1501 DELAY(URTW_EPROM_DELAY); 1502 fail: 1503 return (error); 1504 } 1505 1506 usbd_status 1507 urtw_eprom_ck(struct urtw_softc *sc) 1508 { 1509 uint8_t data; 1510 usbd_status error; 1511 1512 /* masking */ 1513 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1514 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1515 DELAY(URTW_EPROM_DELAY); 1516 /* unmasking */ 1517 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1518 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1519 DELAY(URTW_EPROM_DELAY); 1520 fail: 1521 return (error); 1522 } 1523 1524 usbd_status 1525 urtw_eprom_cs(struct urtw_softc *sc, int able) 1526 { 1527 uint8_t data; 1528 usbd_status error; 1529 1530 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1531 if (able == URTW_EPROM_ENABLE) 1532 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1533 else 1534 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1535 DELAY(URTW_EPROM_DELAY); 1536 fail: 1537 return (error); 1538 } 1539 1540 usbd_status 1541 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1542 { 1543 usb_device_request_t req; 1544 usbd_status error; 1545 1546 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1547 req.bRequest = URTW_8187_GETREGS_REQ; 1548 USETW(req.wValue, val | 0xff00); 1549 USETW(req.wIndex, idx & 0x03); 1550 USETW(req.wLength, sizeof(uint8_t)); 1551 1552 error = usbd_do_request(sc->sc_udev, &req, data); 1553 return (error); 1554 } 1555 1556 usbd_status 1557 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1558 { 1559 usb_device_request_t req; 1560 usbd_status error; 1561 1562 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1563 req.bRequest = URTW_8187_GETREGS_REQ; 1564 USETW(req.wValue, val | 0xfe00); 1565 USETW(req.wIndex, 0); 1566 USETW(req.wLength, sizeof(uint8_t)); 1567 1568 error = usbd_do_request(sc->sc_udev, &req, data); 1569 return (error); 1570 } 1571 1572 usbd_status 1573 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1574 { 1575 usb_device_request_t req; 1576 usbd_status error; 1577 1578 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1579 req.bRequest = URTW_8187_GETREGS_REQ; 1580 USETW(req.wValue, val | 0xff00); 1581 USETW(req.wIndex, idx & 0x03); 1582 USETW(req.wLength, sizeof(uint16_t)); 1583 1584 error = usbd_do_request(sc->sc_udev, &req, data); 1585 *data = letoh16(*data); 1586 return (error); 1587 } 1588 1589 usbd_status 1590 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1591 { 1592 usb_device_request_t req; 1593 usbd_status error; 1594 1595 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1596 req.bRequest = URTW_8187_GETREGS_REQ; 1597 USETW(req.wValue, val | 0xff00); 1598 USETW(req.wIndex, idx & 0x03); 1599 USETW(req.wLength, sizeof(uint32_t)); 1600 1601 error = usbd_do_request(sc->sc_udev, &req, data); 1602 *data = letoh32(*data); 1603 return (error); 1604 } 1605 1606 usbd_status 1607 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1608 { 1609 usb_device_request_t req; 1610 1611 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1612 req.bRequest = URTW_8187_SETREGS_REQ; 1613 USETW(req.wValue, val | 0xff00); 1614 USETW(req.wIndex, idx & 0x03); 1615 USETW(req.wLength, sizeof(uint8_t)); 1616 1617 return (usbd_do_request(sc->sc_udev, &req, &data)); 1618 } 1619 1620 usbd_status 1621 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1622 { 1623 usb_device_request_t req; 1624 1625 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1626 req.bRequest = URTW_8187_SETREGS_REQ; 1627 USETW(req.wValue, val | 0xfe00); 1628 USETW(req.wIndex, 0); 1629 USETW(req.wLength, sizeof(uint8_t)); 1630 1631 return (usbd_do_request(sc->sc_udev, &req, &data)); 1632 } 1633 1634 usbd_status 1635 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1636 { 1637 usb_device_request_t req; 1638 1639 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1640 req.bRequest = URTW_8187_SETREGS_REQ; 1641 USETW(req.wValue, val | 0xff00); 1642 USETW(req.wIndex, idx & 0x03); 1643 USETW(req.wLength, sizeof(uint16_t)); 1644 1645 data = htole16(data); 1646 return (usbd_do_request(sc->sc_udev, &req, &data)); 1647 } 1648 1649 usbd_status 1650 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1651 { 1652 usb_device_request_t req; 1653 1654 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1655 req.bRequest = URTW_8187_SETREGS_REQ; 1656 USETW(req.wValue, val | 0xff00); 1657 USETW(req.wIndex, idx & 0x03); 1658 USETW(req.wLength, sizeof(uint32_t)); 1659 1660 data = htole32(data); 1661 return (usbd_do_request(sc->sc_udev, &req, &data)); 1662 } 1663 1664 static usbd_status 1665 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1666 { 1667 uint8_t data; 1668 usbd_status error; 1669 1670 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1671 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1672 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1673 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1674 fail: 1675 return (error); 1676 } 1677 1678 usbd_status 1679 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1680 { 1681 uint8_t data; 1682 usbd_status error; 1683 1684 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1685 if (error) 1686 goto fail; 1687 1688 urtw_read8_m(sc, URTW_CONFIG3, &data); 1689 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1690 urtw_write32_m(sc, URTW_ANAPARAM, val); 1691 urtw_read8_m(sc, URTW_CONFIG3, &data); 1692 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1693 1694 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1695 if (error) 1696 goto fail; 1697 fail: 1698 return (error); 1699 } 1700 1701 usbd_status 1702 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1703 { 1704 uint8_t data; 1705 usbd_status error; 1706 1707 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1708 if (error) 1709 goto fail; 1710 1711 urtw_read8_m(sc, URTW_CONFIG3, &data); 1712 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1713 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1714 urtw_read8_m(sc, URTW_CONFIG3, &data); 1715 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1716 1717 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1718 if (error) 1719 goto fail; 1720 fail: 1721 return (error); 1722 } 1723 1724 usbd_status 1725 urtw_intr_disable(struct urtw_softc *sc) 1726 { 1727 usbd_status error; 1728 1729 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1730 fail: 1731 return (error); 1732 } 1733 1734 usbd_status 1735 urtw_reset(struct urtw_softc *sc) 1736 { 1737 uint8_t data; 1738 usbd_status error; 1739 1740 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1741 if (error) 1742 goto fail; 1743 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1744 if (error) 1745 goto fail; 1746 1747 error = urtw_intr_disable(sc); 1748 if (error) 1749 goto fail; 1750 usbd_delay_ms(sc->sc_udev, 100); 1751 1752 error = urtw_write8e(sc, 0x18, 0x10); 1753 if (error != 0) 1754 goto fail; 1755 error = urtw_write8e(sc, 0x18, 0x11); 1756 if (error != 0) 1757 goto fail; 1758 error = urtw_write8e(sc, 0x18, 0x00); 1759 if (error != 0) 1760 goto fail; 1761 usbd_delay_ms(sc->sc_udev, 100); 1762 1763 urtw_read8_m(sc, URTW_CMD, &data); 1764 data = (data & 2) | URTW_CMD_RST; 1765 urtw_write8_m(sc, URTW_CMD, data); 1766 usbd_delay_ms(sc->sc_udev, 100); 1767 1768 urtw_read8_m(sc, URTW_CMD, &data); 1769 if (data & URTW_CMD_RST) { 1770 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 1771 goto fail; 1772 } 1773 1774 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1775 if (error) 1776 goto fail; 1777 usbd_delay_ms(sc->sc_udev, 100); 1778 1779 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1780 if (error) 1781 goto fail; 1782 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1783 if (error) 1784 goto fail; 1785 fail: 1786 return (error); 1787 } 1788 1789 usbd_status 1790 urtw_led_on(struct urtw_softc *sc, int type) 1791 { 1792 usbd_status error = 0; 1793 1794 if (type == URTW_LED_GPIO) { 1795 switch (sc->sc_gpio_ledpin) { 1796 case URTW_LED_PIN_GPIO0: 1797 urtw_write8_m(sc, URTW_GPIO, 0x01); 1798 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1799 break; 1800 default: 1801 break; 1802 } 1803 } 1804 1805 sc->sc_gpio_ledon = 1; 1806 fail: 1807 return (error); 1808 } 1809 1810 static usbd_status 1811 urtw_led_off(struct urtw_softc *sc, int type) 1812 { 1813 usbd_status error = 0; 1814 1815 if (type == URTW_LED_GPIO) { 1816 switch (sc->sc_gpio_ledpin) { 1817 case URTW_LED_PIN_GPIO0: 1818 urtw_write8_m(sc, URTW_GPIO, 0x01); 1819 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1820 break; 1821 default: 1822 break; 1823 } 1824 } 1825 1826 sc->sc_gpio_ledon = 0; 1827 1828 fail: 1829 return (error); 1830 } 1831 1832 usbd_status 1833 urtw_led_mode0(struct urtw_softc *sc, int mode) 1834 { 1835 switch (mode) { 1836 case URTW_LED_CTL_POWER_ON: 1837 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1838 break; 1839 case URTW_LED_CTL_TX: 1840 if (sc->sc_gpio_ledinprogress == 1) 1841 return (0); 1842 1843 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1844 sc->sc_gpio_blinktime = 2; 1845 break; 1846 case URTW_LED_CTL_LINK: 1847 sc->sc_gpio_ledstate = URTW_LED_ON; 1848 break; 1849 default: 1850 break; 1851 } 1852 1853 switch (sc->sc_gpio_ledstate) { 1854 case URTW_LED_ON: 1855 if (sc->sc_gpio_ledinprogress != 0) 1856 break; 1857 urtw_led_on(sc, URTW_LED_GPIO); 1858 break; 1859 case URTW_LED_BLINK_NORMAL: 1860 if (sc->sc_gpio_ledinprogress != 0) 1861 break; 1862 sc->sc_gpio_ledinprogress = 1; 1863 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1864 URTW_LED_OFF : URTW_LED_ON; 1865 if (!usbd_is_dying(sc->sc_udev)) 1866 timeout_add_msec(&sc->sc_led_ch, 100); 1867 break; 1868 case URTW_LED_POWER_ON_BLINK: 1869 urtw_led_on(sc, URTW_LED_GPIO); 1870 usbd_delay_ms(sc->sc_udev, 100); 1871 urtw_led_off(sc, URTW_LED_GPIO); 1872 break; 1873 default: 1874 break; 1875 } 1876 return (0); 1877 } 1878 1879 usbd_status 1880 urtw_led_mode1(struct urtw_softc *sc, int mode) 1881 { 1882 return (USBD_INVAL); 1883 } 1884 1885 usbd_status 1886 urtw_led_mode2(struct urtw_softc *sc, int mode) 1887 { 1888 return (USBD_INVAL); 1889 } 1890 1891 usbd_status 1892 urtw_led_mode3(struct urtw_softc *sc, int mode) 1893 { 1894 return (USBD_INVAL); 1895 } 1896 1897 void 1898 urtw_ledusbtask(void *arg) 1899 { 1900 struct urtw_softc *sc = arg; 1901 1902 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1903 return; 1904 1905 urtw_led_blink(sc); 1906 } 1907 1908 void 1909 urtw_ledtask(void *arg) 1910 { 1911 struct urtw_softc *sc = arg; 1912 1913 /* 1914 * NB: to change a status of the led we need at least a sleep so we 1915 * can't do it here 1916 */ 1917 usb_add_task(sc->sc_udev, &sc->sc_ledtask); 1918 } 1919 1920 usbd_status 1921 urtw_led_ctl(struct urtw_softc *sc, int mode) 1922 { 1923 usbd_status error = 0; 1924 1925 switch (sc->sc_strategy) { 1926 case URTW_SW_LED_MODE0: 1927 error = urtw_led_mode0(sc, mode); 1928 break; 1929 case URTW_SW_LED_MODE1: 1930 error = urtw_led_mode1(sc, mode); 1931 break; 1932 case URTW_SW_LED_MODE2: 1933 error = urtw_led_mode2(sc, mode); 1934 break; 1935 case URTW_SW_LED_MODE3: 1936 error = urtw_led_mode3(sc, mode); 1937 break; 1938 default: 1939 break; 1940 } 1941 1942 return (error); 1943 } 1944 1945 usbd_status 1946 urtw_led_blink(struct urtw_softc *sc) 1947 { 1948 uint8_t ing = 0; 1949 usbd_status error; 1950 1951 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1952 error = urtw_led_on(sc, URTW_LED_GPIO); 1953 else 1954 error = urtw_led_off(sc, URTW_LED_GPIO); 1955 sc->sc_gpio_blinktime--; 1956 if (sc->sc_gpio_blinktime == 0) 1957 ing = 1; 1958 else { 1959 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 1960 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 1961 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 1962 ing = 1; 1963 } 1964 if (ing == 1) { 1965 if (sc->sc_gpio_ledstate == URTW_LED_ON && 1966 sc->sc_gpio_ledon == 0) 1967 error = urtw_led_on(sc, URTW_LED_GPIO); 1968 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 1969 sc->sc_gpio_ledon == 1) 1970 error = urtw_led_off(sc, URTW_LED_GPIO); 1971 1972 sc->sc_gpio_blinktime = 0; 1973 sc->sc_gpio_ledinprogress = 0; 1974 return (0); 1975 } 1976 1977 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 1978 URTW_LED_ON : URTW_LED_OFF; 1979 1980 switch (sc->sc_gpio_ledstate) { 1981 case URTW_LED_BLINK_NORMAL: 1982 if (!usbd_is_dying(sc->sc_udev)) 1983 timeout_add_msec(&sc->sc_led_ch, 100); 1984 break; 1985 default: 1986 break; 1987 } 1988 return (0); 1989 } 1990 1991 usbd_status 1992 urtw_update_msr(struct urtw_softc *sc) 1993 { 1994 struct ieee80211com *ic = &sc->sc_ic; 1995 uint8_t data; 1996 usbd_status error; 1997 1998 urtw_read8_m(sc, URTW_MSR, &data); 1999 data &= ~URTW_MSR_LINK_MASK; 2000 2001 /* Should always be set. */ 2002 if (sc->sc_hwrev & URTW_HWREV_8187B) 2003 data |= URTW_MSR_LINK_ENEDCA; 2004 2005 if (sc->sc_state == IEEE80211_S_RUN) { 2006 switch (ic->ic_opmode) { 2007 case IEEE80211_M_STA: 2008 case IEEE80211_M_MONITOR: 2009 data |= URTW_MSR_LINK_STA; 2010 break; 2011 default: 2012 break; 2013 } 2014 } else 2015 data |= URTW_MSR_LINK_NONE; 2016 2017 urtw_write8_m(sc, URTW_MSR, data); 2018 fail: 2019 return (error); 2020 } 2021 2022 uint16_t 2023 urtw_rate2rtl(int rate) 2024 { 2025 int i; 2026 2027 for (i = 0; i < nitems(urtw_ratetable); i++) { 2028 if (rate == urtw_ratetable[i].reg) 2029 return (urtw_ratetable[i].val); 2030 } 2031 2032 return (3); 2033 } 2034 2035 uint16_t 2036 urtw_rtl2rate(int rate) 2037 { 2038 int i; 2039 2040 for (i = 0; i < nitems(urtw_ratetable); i++) { 2041 if (rate == urtw_ratetable[i].val) 2042 return (urtw_ratetable[i].reg); 2043 } 2044 2045 return (0); 2046 } 2047 2048 usbd_status 2049 urtw_set_rate(struct urtw_softc *sc) 2050 { 2051 int i, basic_rate, min_rr_rate, max_rr_rate; 2052 uint16_t data; 2053 usbd_status error; 2054 2055 basic_rate = urtw_rate2rtl(48); 2056 min_rr_rate = urtw_rate2rtl(12); 2057 max_rr_rate = urtw_rate2rtl(48); 2058 2059 urtw_write8_m(sc, URTW_RESP_RATE, 2060 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2061 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2062 2063 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2064 data &= ~URTW_BRSR_MBR_8185; 2065 2066 for (i = 0; i <= basic_rate; i++) 2067 data |= (1 << i); 2068 2069 urtw_write16_m(sc, URTW_8187_BRSR, data); 2070 fail: 2071 return (error); 2072 } 2073 2074 usbd_status 2075 urtw_intr_enable(struct urtw_softc *sc) 2076 { 2077 usbd_status error; 2078 2079 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2080 fail: 2081 return (error); 2082 } 2083 2084 usbd_status 2085 urtw_rx_setconf(struct urtw_softc *sc) 2086 { 2087 struct ifnet *ifp = &sc->sc_ic.ic_if; 2088 struct ieee80211com *ic = &sc->sc_ic; 2089 uint32_t data; 2090 usbd_status error; 2091 2092 urtw_read32_m(sc, URTW_RX, &data); 2093 data = data &~ URTW_RX_FILTER_MASK; 2094 #if 0 2095 data = data | URTW_RX_FILTER_CTL; 2096 #endif 2097 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2098 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2099 2100 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2101 data = data | URTW_RX_FILTER_ICVERR; 2102 data = data | URTW_RX_FILTER_PWR; 2103 } 2104 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2105 data = data | URTW_RX_FILTER_CRCERR; 2106 2107 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2108 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2109 data = data | URTW_RX_FILTER_ALLMAC; 2110 } else { 2111 data = data | URTW_RX_FILTER_NICMAC; 2112 data = data | URTW_RX_CHECK_BSSID; 2113 } 2114 2115 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2116 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2117 data = data &~ URTW_MAX_RX_DMA_MASK; 2118 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2119 2120 urtw_write32_m(sc, URTW_RX, data); 2121 fail: 2122 return (error); 2123 } 2124 2125 usbd_status 2126 urtw_rx_enable(struct urtw_softc *sc) 2127 { 2128 int i; 2129 struct urtw_rx_data *rx_data; 2130 uint8_t data; 2131 usbd_status error; 2132 2133 /* 2134 * Start up the receive pipe. 2135 */ 2136 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2137 rx_data = &sc->sc_rx_data[i]; 2138 2139 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data, 2140 rx_data->buf, MCLBYTES, USBD_SHORT_XFER_OK, 2141 USBD_NO_TIMEOUT, urtw_rxeof); 2142 error = usbd_transfer(rx_data->xfer); 2143 if (error != USBD_IN_PROGRESS && error != 0) { 2144 printf("%s: could not queue Rx transfer\n", 2145 sc->sc_dev.dv_xname); 2146 goto fail; 2147 } 2148 } 2149 2150 error = urtw_rx_setconf(sc); 2151 if (error != 0) 2152 goto fail; 2153 2154 urtw_read8_m(sc, URTW_CMD, &data); 2155 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2156 fail: 2157 return (error); 2158 } 2159 2160 usbd_status 2161 urtw_tx_enable(struct urtw_softc *sc) 2162 { 2163 uint8_t data8; 2164 uint32_t data; 2165 usbd_status error; 2166 2167 if (sc->sc_hwrev & URTW_HWREV_8187) { 2168 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2169 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2170 URTW_CW_CONF_PERPACKET_RETRY); 2171 urtw_write8_m(sc, URTW_CW_CONF, data8); 2172 2173 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2174 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2175 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2176 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2177 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2178 2179 urtw_read32_m(sc, URTW_TX_CONF, &data); 2180 data &= ~URTW_TX_LOOPBACK_MASK; 2181 data |= URTW_TX_LOOPBACK_NONE; 2182 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2183 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2184 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2185 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2186 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2187 data &= ~URTW_TX_SWPLCPLEN; 2188 data |= URTW_TX_NOICV; 2189 urtw_write32_m(sc, URTW_TX_CONF, data); 2190 } else { 2191 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2192 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2193 URTW_TX_LONGRETRY; 2194 urtw_write32_m(sc, URTW_TX_CONF, data); 2195 } 2196 2197 urtw_read8_m(sc, URTW_CMD, &data8); 2198 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2199 fail: 2200 return (error); 2201 } 2202 2203 int 2204 urtw_init(struct ifnet *ifp) 2205 { 2206 struct urtw_softc *sc = ifp->if_softc; 2207 struct urtw_rf *rf = &sc->sc_rf; 2208 struct ieee80211com *ic = &sc->sc_ic; 2209 usbd_status error; 2210 2211 urtw_stop(ifp, 0); 2212 2213 error = urtw_reset(sc); 2214 if (error) 2215 goto fail; 2216 2217 urtw_write8_m(sc, 0x85, 0); 2218 urtw_write8_m(sc, URTW_GPIO, 0); 2219 2220 /* for led */ 2221 urtw_write8_m(sc, 0x85, 4); 2222 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2223 if (error != 0) 2224 goto fail; 2225 2226 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2227 if (error) 2228 goto fail; 2229 2230 /* applying MAC address again. */ 2231 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2232 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2233 if (error) 2234 goto fail; 2235 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2236 if (error) 2237 goto fail; 2238 2239 error = urtw_update_msr(sc); 2240 if (error) 2241 goto fail; 2242 2243 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2244 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2245 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2246 error = urtw_set_rate(sc); 2247 if (error != 0) 2248 goto fail; 2249 2250 error = rf->init(rf); 2251 if (error != 0) 2252 goto fail; 2253 if (rf->set_sens != NULL) 2254 rf->set_sens(rf); 2255 2256 urtw_write16_m(sc, 0x5e, 1); 2257 urtw_write16_m(sc, 0xfe, 0x10); 2258 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2259 urtw_write8_m(sc, 0xff, 0x60); 2260 urtw_write16_m(sc, 0x5e, 0); 2261 urtw_write8_m(sc, 0x85, 4); 2262 2263 error = urtw_intr_enable(sc); 2264 if (error != 0) 2265 goto fail; 2266 2267 /* reset softc variables */ 2268 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 2269 sc->sc_txtimer = 0; 2270 2271 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2272 error = urtw_open_pipes(sc); 2273 if (error != 0) 2274 goto fail; 2275 error = urtw_alloc_rx_data_list(sc); 2276 if (error != 0) 2277 goto fail; 2278 error = urtw_alloc_tx_data_list(sc); 2279 if (error != 0) 2280 goto fail; 2281 sc->sc_flags |= URTW_INIT_ONCE; 2282 } 2283 2284 error = urtw_rx_enable(sc); 2285 if (error != 0) 2286 goto fail; 2287 error = urtw_tx_enable(sc); 2288 if (error != 0) 2289 goto fail; 2290 2291 ifq_clr_oactive(&ifp->if_snd); 2292 ifp->if_flags |= IFF_RUNNING; 2293 2294 ifp->if_timer = 1; 2295 2296 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2297 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2298 else 2299 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2300 2301 return (0); 2302 fail: 2303 return (error); 2304 } 2305 2306 void 2307 urtw_set_multi(struct urtw_softc *sc) 2308 { 2309 struct arpcom *ac = &sc->sc_ic.ic_ac; 2310 struct ifnet *ifp = &ac->ac_if; 2311 2312 /* 2313 * XXX don't know how to set a device. Lack of docs. Just try to set 2314 * IFF_ALLMULTI flag here. 2315 */ 2316 ifp->if_flags |= IFF_ALLMULTI; 2317 } 2318 2319 int 2320 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2321 { 2322 struct urtw_softc *sc = ifp->if_softc; 2323 struct ieee80211com *ic = &sc->sc_ic; 2324 struct ifreq *ifr; 2325 int s, error = 0; 2326 2327 if (usbd_is_dying(sc->sc_udev)) 2328 return (ENXIO); 2329 2330 usbd_ref_incr(sc->sc_udev); 2331 2332 s = splnet(); 2333 2334 switch (cmd) { 2335 case SIOCSIFADDR: 2336 ifp->if_flags |= IFF_UP; 2337 /* FALLTHROUGH */ 2338 case SIOCSIFFLAGS: 2339 if (ifp->if_flags & IFF_UP) { 2340 /* 2341 * If only the PROMISC or ALLMULTI flag changes, then 2342 * don't do a full re-init of the chip, just update 2343 * the Rx filter. 2344 */ 2345 if ((ifp->if_flags & IFF_RUNNING) && 2346 ((ifp->if_flags ^ sc->sc_if_flags) & 2347 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2348 urtw_set_multi(sc); 2349 } else { 2350 if (!(ifp->if_flags & IFF_RUNNING)) 2351 sc->sc_init(ifp); 2352 } 2353 } else { 2354 if (ifp->if_flags & IFF_RUNNING) 2355 urtw_stop(ifp, 1); 2356 } 2357 sc->sc_if_flags = ifp->if_flags; 2358 break; 2359 2360 case SIOCADDMULTI: 2361 case SIOCDELMULTI: 2362 ifr = (struct ifreq *)data; 2363 error = (cmd == SIOCADDMULTI) ? 2364 ether_addmulti(ifr, &ic->ic_ac) : 2365 ether_delmulti(ifr, &ic->ic_ac); 2366 if (error == ENETRESET) { 2367 if (ifp->if_flags & IFF_RUNNING) 2368 urtw_set_multi(sc); 2369 error = 0; 2370 } 2371 break; 2372 2373 case SIOCS80211CHANNEL: 2374 /* 2375 * This allows for fast channel switching in monitor mode 2376 * (used by kismet). In IBSS mode, we must explicitly reset 2377 * the interface to generate a new beacon frame. 2378 */ 2379 error = ieee80211_ioctl(ifp, cmd, data); 2380 if (error == ENETRESET && 2381 ic->ic_opmode == IEEE80211_M_MONITOR) { 2382 urtw_set_chan(sc, ic->ic_ibss_chan); 2383 error = 0; 2384 } 2385 break; 2386 2387 default: 2388 error = ieee80211_ioctl(ifp, cmd, data); 2389 } 2390 2391 if (error == ENETRESET) { 2392 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == 2393 (IFF_RUNNING | IFF_UP)) 2394 sc->sc_init(ifp); 2395 error = 0; 2396 } 2397 2398 splx(s); 2399 2400 usbd_ref_decr(sc->sc_udev); 2401 2402 return (error); 2403 } 2404 2405 void 2406 urtw_start(struct ifnet *ifp) 2407 { 2408 struct urtw_softc *sc = ifp->if_softc; 2409 struct ieee80211com *ic = &sc->sc_ic; 2410 struct ieee80211_node *ni; 2411 struct mbuf *m0; 2412 2413 /* 2414 * net80211 may still try to send management frames even if the 2415 * IFF_RUNNING flag is not set... 2416 */ 2417 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 2418 return; 2419 2420 for (;;) { 2421 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2422 sc->sc_tx_normal_queued >= URTW_TX_DATA_LIST_COUNT) { 2423 ifq_set_oactive(&ifp->if_snd); 2424 break; 2425 } 2426 2427 m0 = mq_dequeue(&ic->ic_mgtq); 2428 if (m0 != NULL) { 2429 ni = m0->m_pkthdr.ph_cookie; 2430 #if NBPFILTER > 0 2431 if (ic->ic_rawbpf != NULL) 2432 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 2433 #endif 2434 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2435 != 0) 2436 break; 2437 } else { 2438 if (ic->ic_state != IEEE80211_S_RUN) 2439 break; 2440 m0 = ifq_dequeue(&ifp->if_snd); 2441 if (m0 == NULL) 2442 break; 2443 #if NBPFILTER > 0 2444 if (ifp->if_bpf != NULL) 2445 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 2446 #endif 2447 m0 = ieee80211_encap(ifp, m0, &ni); 2448 if (m0 == NULL) 2449 continue; 2450 #if NBPFILTER > 0 2451 if (ic->ic_rawbpf != NULL) 2452 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 2453 #endif 2454 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2455 != 0) { 2456 if (ni != NULL) 2457 ieee80211_release_node(ic, ni); 2458 ifp->if_oerrors++; 2459 break; 2460 } 2461 } 2462 sc->sc_txtimer = 5; 2463 } 2464 } 2465 2466 void 2467 urtw_watchdog(struct ifnet *ifp) 2468 { 2469 struct urtw_softc *sc = ifp->if_softc; 2470 2471 ifp->if_timer = 0; 2472 2473 if (sc->sc_txtimer > 0) { 2474 if (--sc->sc_txtimer == 0) { 2475 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2476 ifp->if_oerrors++; 2477 return; 2478 } 2479 ifp->if_timer = 1; 2480 } 2481 2482 ieee80211_watchdog(ifp); 2483 } 2484 2485 void 2486 urtw_txeof_low(struct usbd_xfer *xfer, void *priv, 2487 usbd_status status) 2488 { 2489 struct urtw_tx_data *data = priv; 2490 struct urtw_softc *sc = data->sc; 2491 struct ieee80211com *ic = &sc->sc_ic; 2492 struct ifnet *ifp = &ic->ic_if; 2493 int s; 2494 2495 if (status != USBD_NORMAL_COMPLETION) { 2496 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2497 return; 2498 2499 printf("%s: could not transmit buffer: %s\n", 2500 sc->sc_dev.dv_xname, usbd_errstr(status)); 2501 2502 if (status == USBD_STALLED) 2503 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2504 2505 ifp->if_oerrors++; 2506 return; 2507 } 2508 2509 s = splnet(); 2510 2511 ieee80211_release_node(ic, data->ni); 2512 data->ni = NULL; 2513 2514 sc->sc_txtimer = 0; 2515 2516 sc->sc_tx_low_queued--; 2517 ifq_clr_oactive(&ifp->if_snd); 2518 urtw_start(ifp); 2519 2520 splx(s); 2521 } 2522 2523 void 2524 urtw_txeof_normal(struct usbd_xfer *xfer, void *priv, 2525 usbd_status status) 2526 { 2527 struct urtw_tx_data *data = priv; 2528 struct urtw_softc *sc = data->sc; 2529 struct ieee80211com *ic = &sc->sc_ic; 2530 struct ifnet *ifp = &ic->ic_if; 2531 int s; 2532 2533 if (status != USBD_NORMAL_COMPLETION) { 2534 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2535 return; 2536 2537 printf("%s: could not transmit buffer: %s\n", 2538 sc->sc_dev.dv_xname, usbd_errstr(status)); 2539 2540 if (status == USBD_STALLED) 2541 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2542 2543 ifp->if_oerrors++; 2544 return; 2545 } 2546 2547 s = splnet(); 2548 2549 ieee80211_release_node(ic, data->ni); 2550 data->ni = NULL; 2551 2552 sc->sc_txtimer = 0; 2553 2554 sc->sc_tx_normal_queued--; 2555 ifq_clr_oactive(&ifp->if_snd); 2556 urtw_start(ifp); 2557 2558 splx(s); 2559 } 2560 2561 int 2562 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2563 int prior) 2564 { 2565 struct ieee80211com *ic = &sc->sc_ic; 2566 struct urtw_tx_data *data; 2567 struct ieee80211_frame *wh; 2568 struct ieee80211_key *k; 2569 usbd_status error; 2570 int xferlen; 2571 2572 wh = mtod(m0, struct ieee80211_frame *); 2573 2574 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2575 k = ieee80211_get_txkey(ic, wh, ni); 2576 2577 if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL) 2578 return (ENOBUFS); 2579 2580 /* packet header may have moved, reset our local pointer */ 2581 wh = mtod(m0, struct ieee80211_frame *); 2582 } 2583 2584 #if NBPFILTER > 0 2585 if (sc->sc_drvbpf != NULL) { 2586 struct mbuf mb; 2587 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2588 2589 tap->wt_flags = 0; 2590 tap->wt_rate = 0; 2591 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2592 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2593 2594 mb.m_data = (caddr_t)tap; 2595 mb.m_len = sc->sc_txtap_len; 2596 mb.m_next = m0; 2597 mb.m_nextpkt = NULL; 2598 mb.m_type = 0; 2599 mb.m_flags = 0; 2600 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2601 } 2602 #endif 2603 2604 if (sc->sc_hwrev & URTW_HWREV_8187) 2605 xferlen = m0->m_pkthdr.len + 4 * 3; 2606 else 2607 xferlen = m0->m_pkthdr.len + 4 * 8; 2608 2609 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2610 xferlen += 1; 2611 2612 data = &sc->sc_tx_data[sc->sc_txidx]; 2613 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT; 2614 2615 bzero(data->buf, URTW_TX_MAXSIZE); 2616 data->buf[0] = m0->m_pkthdr.len & 0xff; 2617 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2618 data->buf[1] |= (1 << 7); 2619 2620 /* XXX sc_preamble_mode is always 2. */ 2621 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2622 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2623 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2624 data->buf[2] |= 1; 2625 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2626 prior == URTW_PRIORITY_LOW) 2627 return ENOTSUP; /* TODO */ 2628 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2629 data->buf[2] |= (1 << 1); 2630 /* RTS rate - 10 means we use a basic rate. */ 2631 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2632 /* 2633 * XXX currently TX rate control depends on the rate value of 2634 * RX descriptor because I don't know how to we can control TX rate 2635 * in more smart way. Please fix me you find a thing. 2636 */ 2637 data->buf[3] = sc->sc_currate; 2638 if (prior == URTW_PRIORITY_NORMAL) { 2639 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2640 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2641 else if (ic->ic_fixed_rate != -1) 2642 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2643 } 2644 2645 if (sc->sc_hwrev & URTW_HWREV_8187) { 2646 data->buf[8] = 3; /* CW minimum */ 2647 data->buf[8] |= (7 << 4); /* CW maximum */ 2648 data->buf[9] |= 11; /* retry limitation */ 2649 m_copydata(m0, 0, m0->m_pkthdr.len, &data->buf[12]); 2650 } else { 2651 data->buf[21] |= 11; /* retry limitation */ 2652 m_copydata(m0, 0, m0->m_pkthdr.len, &data->buf[32]); 2653 } 2654 2655 data->ni = ni; 2656 2657 /* mbuf is no longer needed. */ 2658 m_freem(m0); 2659 2660 usbd_setup_xfer(data->xfer, 2661 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low : 2662 sc->sc_txpipe_normal, data, data->buf, xferlen, 2663 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTW_DATA_TIMEOUT, 2664 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2665 error = usbd_transfer(data->xfer); 2666 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2667 printf("%s: could not send frame: %s\n", 2668 sc->sc_dev.dv_xname, usbd_errstr(error)); 2669 return (EIO); 2670 } 2671 2672 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2673 if (error != 0) 2674 printf("%s: could not control LED (%d)\n", 2675 sc->sc_dev.dv_xname, error); 2676 2677 if (prior == URTW_PRIORITY_LOW) 2678 sc->sc_tx_low_queued++; 2679 else 2680 sc->sc_tx_normal_queued++; 2681 2682 return (0); 2683 } 2684 2685 usbd_status 2686 urtw_8225_usb_init(struct urtw_softc *sc) 2687 { 2688 uint8_t data; 2689 usbd_status error; 2690 2691 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2692 urtw_write8_m(sc, URTW_GPIO, 0); 2693 error = urtw_read8e(sc, 0x53, &data); 2694 if (error) 2695 goto fail; 2696 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2697 if (error) 2698 goto fail; 2699 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2700 urtw_write8_m(sc, URTW_GPIO, 0x20); 2701 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2702 2703 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2704 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2705 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2706 2707 usbd_delay_ms(sc->sc_udev, 500); 2708 fail: 2709 return (error); 2710 } 2711 2712 usbd_status 2713 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2714 { 2715 usbd_status error = 0; 2716 2717 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2718 fail: 2719 return (error); 2720 } 2721 2722 usbd_status 2723 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2724 { 2725 uint32_t phyw; 2726 usbd_status error; 2727 2728 phyw = ((data << 8) | (addr | 0x80)); 2729 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2730 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2731 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2732 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2733 /* 2734 * Delay removed from 8185 to 8187. 2735 * usbd_delay_ms(sc->sc_udev, 1); 2736 */ 2737 fail: 2738 return (error); 2739 } 2740 2741 usbd_status 2742 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2743 { 2744 data = data & 0xff; 2745 return (urtw_8187_write_phy(sc, addr, data)); 2746 } 2747 2748 usbd_status 2749 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2750 { 2751 data = data & 0xff; 2752 return (urtw_8187_write_phy(sc, addr, data | 0x10000)); 2753 } 2754 2755 usbd_status 2756 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2757 { 2758 usbd_status error; 2759 2760 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2761 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2762 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2763 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2764 fail: 2765 return (error); 2766 } 2767 2768 usbd_status 2769 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2770 { 2771 int i, idx, set; 2772 uint8_t *cck_pwltable; 2773 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2774 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2775 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2776 usbd_status error; 2777 2778 cck_pwrlvl_max = 11; 2779 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2780 ofdm_pwrlvl_min = 10; 2781 2782 /* CCK power setting */ 2783 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2784 idx = cck_pwrlvl % 6; 2785 set = cck_pwrlvl / 6; 2786 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2787 urtw_8225_txpwr_cck; 2788 2789 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2790 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2791 for (i = 0; i < 8; i++) { 2792 urtw_8187_write_phy_cck(sc, 0x44 + i, 2793 cck_pwltable[idx * 8 + i]); 2794 } 2795 usbd_delay_ms(sc->sc_udev, 1); 2796 2797 /* OFDM power setting */ 2798 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2799 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2800 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2801 2802 idx = ofdm_pwrlvl % 6; 2803 set = ofdm_pwrlvl / 6; 2804 2805 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2806 if (error) 2807 goto fail; 2808 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2809 urtw_8187_write_phy_ofdm(sc, 6, 0); 2810 urtw_8187_write_phy_ofdm(sc, 8, 0); 2811 2812 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2813 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2814 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2815 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2816 usbd_delay_ms(sc->sc_udev, 1); 2817 fail: 2818 return (error); 2819 } 2820 2821 usbd_status 2822 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2823 { 2824 usbd_status error; 2825 2826 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2827 usbd_delay_ms(sc->sc_udev, 1); 2828 fail: 2829 return (error); 2830 } 2831 2832 usbd_status 2833 urtw_8225_rf_init(struct urtw_rf *rf) 2834 { 2835 struct urtw_softc *sc = rf->rf_sc; 2836 int i; 2837 uint16_t data; 2838 usbd_status error; 2839 2840 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2841 if (error) 2842 goto fail; 2843 2844 error = urtw_8225_usb_init(sc); 2845 if (error) 2846 goto fail; 2847 2848 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2849 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2850 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2851 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2852 2853 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2854 if (error) 2855 goto fail; 2856 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2857 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2858 if (error) 2859 goto fail; 2860 2861 error = urtw_8185_rf_pins_enable(sc); 2862 if (error) 2863 goto fail; 2864 2865 usbd_delay_ms(sc->sc_udev, 500); 2866 2867 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2868 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2869 urtw_8225_rf_part1[i].val); 2870 } 2871 usbd_delay_ms(sc->sc_udev, 50); 2872 urtw_8225_write(sc, 0x2, 0xc4d); 2873 usbd_delay_ms(sc->sc_udev, 200); 2874 urtw_8225_write(sc, 0x2, 0x44d); 2875 usbd_delay_ms(sc->sc_udev, 200); 2876 urtw_8225_write(sc, 0x0, 0x127); 2877 2878 for (i = 0; i < nitems(urtw_8225_rxgain); i++) { 2879 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2880 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2881 } 2882 2883 urtw_8225_write(sc, 0x0, 0x27); 2884 urtw_8225_write(sc, 0x0, 0x22f); 2885 2886 for (i = 0; i < nitems(urtw_8225_agc); i++) { 2887 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2888 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2889 } 2890 2891 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2892 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2893 urtw_8225_rf_part2[i].val); 2894 usbd_delay_ms(sc->sc_udev, 1); 2895 } 2896 2897 error = urtw_8225_setgain(sc, 4); 2898 if (error) 2899 goto fail; 2900 2901 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2902 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2903 urtw_8225_rf_part3[i].val); 2904 usbd_delay_ms(sc->sc_udev, 1); 2905 } 2906 2907 urtw_write8_m(sc, 0x5b, 0x0d); 2908 2909 error = urtw_8225_set_txpwrlvl(sc, 1); 2910 if (error) 2911 goto fail; 2912 2913 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2914 usbd_delay_ms(sc->sc_udev, 1); 2915 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2916 usbd_delay_ms(sc->sc_udev, 1); 2917 2918 /* TX ant A, 0x0 for B */ 2919 error = urtw_8185_tx_antenna(sc, 0x3); 2920 if (error) 2921 goto fail; 2922 urtw_write32_m(sc, 0x94, 0x3dc00002); 2923 2924 error = urtw_8225_rf_set_chan(rf, 1); 2925 fail: 2926 return (error); 2927 } 2928 2929 usbd_status 2930 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2931 { 2932 struct urtw_softc *sc = rf->rf_sc; 2933 struct ieee80211com *ic = &sc->sc_ic; 2934 struct ieee80211_channel *c = ic->ic_ibss_chan; 2935 usbd_status error; 2936 2937 error = urtw_8225_set_txpwrlvl(sc, chan); 2938 if (error) 2939 goto fail; 2940 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2941 usbd_delay_ms(sc->sc_udev, 10); 2942 2943 urtw_write8_m(sc, URTW_SIFS, 0x22); 2944 2945 if (sc->sc_state == IEEE80211_S_ASSOC && 2946 ic->ic_flags & IEEE80211_F_SHSLOT) 2947 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_DS_SHSLOT); 2948 else 2949 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_DS_SLOT); 2950 2951 if (IEEE80211_IS_CHAN_G(c)) { 2952 urtw_write8_m(sc, URTW_DIFS, 0x14); 2953 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2954 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2955 } else { 2956 urtw_write8_m(sc, URTW_DIFS, 0x24); 2957 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2958 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2959 } 2960 2961 fail: 2962 return (error); 2963 } 2964 2965 usbd_status 2966 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2967 { 2968 struct urtw_softc *sc = rf->rf_sc; 2969 usbd_status error; 2970 2971 if (rf->sens > 6) 2972 return (-1); 2973 2974 if (rf->sens > 4) 2975 urtw_8225_write(sc, 0x0c, 0x850); 2976 else 2977 urtw_8225_write(sc, 0x0c, 0x50); 2978 2979 rf->sens = 6 - rf->sens; 2980 error = urtw_8225_setgain(sc, rf->sens); 2981 if (error) 2982 goto fail; 2983 2984 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 2985 2986 fail: 2987 return (error); 2988 } 2989 2990 void 2991 urtw_stop(struct ifnet *ifp, int disable) 2992 { 2993 struct urtw_softc *sc = ifp->if_softc; 2994 struct ieee80211com *ic = &sc->sc_ic; 2995 uint8_t data; 2996 usbd_status error; 2997 2998 ifp->if_flags &= ~IFF_RUNNING; 2999 ifq_clr_oactive(&ifp->if_snd); 3000 3001 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3002 3003 timeout_del(&sc->scan_to); 3004 timeout_del(&sc->sc_led_ch); 3005 3006 urtw_intr_disable(sc); 3007 urtw_read8_m(sc, URTW_CMD, &data); 3008 data &= ~URTW_CMD_TX_ENABLE; 3009 data &= ~URTW_CMD_RX_ENABLE; 3010 urtw_write8_m(sc, URTW_CMD, data); 3011 3012 if (sc->sc_rxpipe != NULL) 3013 usbd_abort_pipe(sc->sc_rxpipe); 3014 if (sc->sc_txpipe_low != NULL) 3015 usbd_abort_pipe(sc->sc_txpipe_low); 3016 if (sc->sc_txpipe_normal != NULL) 3017 usbd_abort_pipe(sc->sc_txpipe_normal); 3018 3019 fail: 3020 return; 3021 } 3022 3023 int 3024 urtw_isbmode(uint16_t rate) 3025 { 3026 rate = urtw_rtl2rate(rate); 3027 3028 return (((rate <= 22 && rate != 12 && rate != 18) || 3029 rate == 44) ? (1) : (0)); 3030 } 3031 3032 void 3033 urtw_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 3034 { 3035 struct urtw_rx_data *data = priv; 3036 struct urtw_softc *sc = data->sc; 3037 struct ieee80211com *ic = &sc->sc_ic; 3038 struct ifnet *ifp = &ic->ic_if; 3039 struct ieee80211_frame *wh; 3040 struct ieee80211_node *ni; 3041 struct ieee80211_rxinfo rxi; 3042 struct mbuf *m, *mnew; 3043 uint8_t *desc, quality, rate; 3044 int actlen, flen, len, nf, rssi, s; 3045 3046 if (status != USBD_NORMAL_COMPLETION) { 3047 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3048 return; 3049 3050 if (status == USBD_STALLED) 3051 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3052 ifp->if_ierrors++; 3053 goto skip; 3054 } 3055 3056 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3057 if (actlen < URTW_MIN_RXBUFSZ) { 3058 ifp->if_ierrors++; 3059 goto skip; 3060 } 3061 3062 if (sc->sc_hwrev & URTW_HWREV_8187) 3063 /* 4 dword and 4 byte CRC */ 3064 len = actlen - (4 * 4); 3065 else 3066 /* 5 dword and 4 byte CRC */ 3067 len = actlen - (4 * 5); 3068 3069 desc = data->buf + len; 3070 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3071 if (flen > actlen) { 3072 ifp->if_ierrors++; 3073 goto skip; 3074 } 3075 3076 rate = (desc[2] & 0xf0) >> 4; 3077 if (sc->sc_hwrev & URTW_HWREV_8187) { 3078 quality = desc[4] & 0xff; 3079 rssi = (desc[6] & 0xfe) >> 1; 3080 3081 /* XXX correct? */ 3082 if (!urtw_isbmode(rate)) { 3083 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3084 rssi = ((90 - rssi) * 100) / 65; 3085 } else { 3086 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3087 rssi = ((95 - rssi) * 100) / 65; 3088 } 3089 } else { 3090 quality = desc[12]; 3091 rssi = 14 - desc[14] / 2; 3092 } 3093 3094 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3095 if (mnew == NULL) { 3096 printf("%s: could not allocate rx mbuf\n", 3097 sc->sc_dev.dv_xname); 3098 ifp->if_ierrors++; 3099 goto skip; 3100 } 3101 MCLGET(mnew, M_DONTWAIT); 3102 if (!(mnew->m_flags & M_EXT)) { 3103 printf("%s: could not allocate rx mbuf cluster\n", 3104 sc->sc_dev.dv_xname); 3105 m_freem(mnew); 3106 ifp->if_ierrors++; 3107 goto skip; 3108 } 3109 3110 m = data->m; 3111 data->m = mnew; 3112 data->buf = mtod(mnew, uint8_t *); 3113 3114 /* finalize mbuf */ 3115 m->m_pkthdr.len = m->m_len = flen - 4; 3116 3117 s = splnet(); 3118 3119 #if NBPFILTER > 0 3120 if (sc->sc_drvbpf != NULL) { 3121 struct mbuf mb; 3122 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3123 3124 /* XXX Are variables correct? */ 3125 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3126 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3127 tap->wr_dbm_antsignal = (int8_t)rssi; 3128 3129 mb.m_data = (caddr_t)tap; 3130 mb.m_len = sc->sc_rxtap_len; 3131 mb.m_next = m; 3132 mb.m_nextpkt = NULL; 3133 mb.m_type = 0; 3134 mb.m_flags = 0; 3135 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 3136 } 3137 #endif 3138 wh = mtod(m, struct ieee80211_frame *); 3139 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3140 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3141 ni = ieee80211_find_rxnode(ic, wh); 3142 3143 /* XXX correct? */ 3144 if (!urtw_isbmode(rate)) { 3145 if (quality > 127) 3146 quality = 0; 3147 else if (quality < 27) 3148 quality = 100; 3149 else 3150 quality = 127 - quality; 3151 } else 3152 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3153 3154 nf = quality; 3155 3156 /* send the frame to the 802.11 layer */ 3157 memset(&rxi, 0, sizeof(rxi)); 3158 rxi.rxi_rssi = rssi; 3159 ieee80211_input(ifp, m, ni, &rxi); 3160 3161 /* node is no longer needed */ 3162 ieee80211_release_node(ic, ni); 3163 3164 splx(s); 3165 3166 skip: /* setup a new transfer */ 3167 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES, 3168 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3169 (void)usbd_transfer(xfer); 3170 } 3171 3172 usbd_status 3173 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3174 { 3175 uint8_t *gainp; 3176 usbd_status error; 3177 3178 /* XXX for A? */ 3179 gainp = urtw_8225v2_gain_bg; 3180 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3181 usbd_delay_ms(sc->sc_udev, 1); 3182 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3183 usbd_delay_ms(sc->sc_udev, 1); 3184 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3185 usbd_delay_ms(sc->sc_udev, 1); 3186 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3187 usbd_delay_ms(sc->sc_udev, 1); 3188 fail: 3189 return (error); 3190 } 3191 3192 usbd_status 3193 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3194 { 3195 int i; 3196 uint8_t *cck_pwrtable; 3197 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3198 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3199 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3200 usbd_status error; 3201 3202 /* CCK power setting */ 3203 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3204 cck_pwrlvl += sc->sc_txpwr_cck_base; 3205 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3206 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3207 urtw_8225v2_txpwr_cck; 3208 3209 for (i = 0; i < 8; i++) { 3210 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3211 } 3212 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3213 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3214 usbd_delay_ms(sc->sc_udev, 1); 3215 3216 /* OFDM power setting */ 3217 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3218 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3219 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3220 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3221 3222 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3223 if (error) 3224 goto fail; 3225 3226 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3227 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3228 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3229 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3230 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3231 3232 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3233 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3234 usbd_delay_ms(sc->sc_udev, 1); 3235 fail: 3236 return (error); 3237 } 3238 3239 usbd_status 3240 urtw_8225v2_rf_init(struct urtw_rf *rf) 3241 { 3242 struct urtw_softc *sc = rf->rf_sc; 3243 int i; 3244 uint16_t data; 3245 uint32_t data32; 3246 usbd_status error; 3247 3248 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3249 if (error) 3250 goto fail; 3251 3252 error = urtw_8225_usb_init(sc); 3253 if (error) 3254 goto fail; 3255 3256 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3257 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3258 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3259 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3260 3261 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3262 if (error) 3263 goto fail; 3264 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3265 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3266 if (error) 3267 goto fail; 3268 3269 error = urtw_8185_rf_pins_enable(sc); 3270 if (error) 3271 goto fail; 3272 3273 usbd_delay_ms(sc->sc_udev, 1000); 3274 3275 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 3276 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3277 urtw_8225v2_rf_part1[i].val); 3278 usbd_delay_ms(sc->sc_udev, 1); 3279 } 3280 usbd_delay_ms(sc->sc_udev, 50); 3281 3282 urtw_8225_write(sc, 0x0, 0x1b7); 3283 3284 for (i = 0; i < nitems(urtw_8225v2_rxgain); i++) { 3285 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3286 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3287 } 3288 3289 urtw_8225_write(sc, 0x3, 0x2); 3290 urtw_8225_write(sc, 0x5, 0x4); 3291 urtw_8225_write(sc, 0x0, 0xb7); 3292 urtw_8225_write(sc, 0x2, 0xc4d); 3293 usbd_delay_ms(sc->sc_udev, 100); 3294 urtw_8225_write(sc, 0x2, 0x44d); 3295 usbd_delay_ms(sc->sc_udev, 100); 3296 3297 error = urtw_8225_read(sc, 0x6, &data32); 3298 if (error != 0) 3299 goto fail; 3300 if (data32 != 0xe6) 3301 printf("%s: expect 0xe6!! (0x%x)\n", sc->sc_dev.dv_xname, 3302 data32); 3303 if (!(data32 & 0x80)) { 3304 urtw_8225_write(sc, 0x02, 0x0c4d); 3305 usbd_delay_ms(sc->sc_udev, 200); 3306 urtw_8225_write(sc, 0x02, 0x044d); 3307 usbd_delay_ms(sc->sc_udev, 100); 3308 error = urtw_8225_read(sc, 0x6, &data32); 3309 if (error != 0) 3310 goto fail; 3311 if (!(data32 & 0x80)) 3312 printf("%s: RF calibration failed\n", 3313 sc->sc_dev.dv_xname); 3314 } 3315 usbd_delay_ms(sc->sc_udev, 100); 3316 3317 urtw_8225_write(sc, 0x0, 0x2bf); 3318 for (i = 0; i < nitems(urtw_8225_agc); i++) { 3319 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3320 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3321 } 3322 3323 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 3324 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3325 urtw_8225v2_rf_part2[i].val); 3326 } 3327 3328 error = urtw_8225v2_setgain(sc, 4); 3329 if (error) 3330 goto fail; 3331 3332 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 3333 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3334 urtw_8225v2_rf_part3[i].val); 3335 } 3336 3337 urtw_write8_m(sc, 0x5b, 0x0d); 3338 3339 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3340 if (error) 3341 goto fail; 3342 3343 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3344 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3345 3346 /* TX ant A, 0x0 for B */ 3347 error = urtw_8185_tx_antenna(sc, 0x3); 3348 if (error) 3349 goto fail; 3350 urtw_write32_m(sc, 0x94, 0x3dc00002); 3351 3352 error = urtw_8225_rf_set_chan(rf, 1); 3353 fail: 3354 return (error); 3355 } 3356 3357 usbd_status 3358 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3359 { 3360 struct urtw_softc *sc = rf->rf_sc; 3361 struct ieee80211com *ic = &sc->sc_ic; 3362 struct ieee80211_channel *c = ic->ic_ibss_chan; 3363 usbd_status error; 3364 3365 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3366 if (error) 3367 goto fail; 3368 3369 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3370 usbd_delay_ms(sc->sc_udev, 10); 3371 3372 urtw_write8_m(sc, URTW_SIFS, 0x22); 3373 3374 if(sc->sc_state == IEEE80211_S_ASSOC && 3375 ic->ic_flags & IEEE80211_F_SHSLOT) 3376 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_DS_SHSLOT); 3377 else 3378 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_DS_SLOT); 3379 3380 if (IEEE80211_IS_CHAN_G(c)) { 3381 urtw_write8_m(sc, URTW_DIFS, 0x14); 3382 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3383 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3384 } else { 3385 urtw_write8_m(sc, URTW_DIFS, 0x24); 3386 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3387 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3388 } 3389 3390 fail: 3391 return (error); 3392 } 3393 3394 void 3395 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3396 { 3397 struct urtw_rf *rf = &sc->sc_rf; 3398 struct ieee80211com *ic = &sc->sc_ic; 3399 usbd_status error = 0; 3400 uint32_t data; 3401 u_int chan; 3402 3403 chan = ieee80211_chan2ieee(ic, c); 3404 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3405 return; 3406 /* 3407 * During changing the channel we need to temporary disable 3408 * TX. 3409 */ 3410 urtw_read32_m(sc, URTW_TX_CONF, &data); 3411 data &= ~URTW_TX_LOOPBACK_MASK; 3412 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3413 error = rf->set_chan(rf, chan); 3414 if (error != 0) { 3415 printf("%s could not change the channel\n", 3416 sc->sc_dev.dv_xname); 3417 return; 3418 } 3419 usbd_delay_ms(sc->sc_udev, 10); 3420 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3421 3422 fail: return; 3423 3424 } 3425 3426 void 3427 urtw_next_scan(void *arg) 3428 { 3429 struct urtw_softc *sc = arg; 3430 struct ieee80211com *ic = &sc->sc_ic; 3431 struct ifnet *ifp = &ic->ic_if; 3432 3433 if (usbd_is_dying(sc->sc_udev)) 3434 return; 3435 3436 usbd_ref_incr(sc->sc_udev); 3437 3438 if (ic->ic_state == IEEE80211_S_SCAN) 3439 ieee80211_next_scan(ifp); 3440 3441 usbd_ref_decr(sc->sc_udev); 3442 } 3443 3444 void 3445 urtw_task(void *arg) 3446 { 3447 struct urtw_softc *sc = arg; 3448 struct ieee80211com *ic = &sc->sc_ic; 3449 struct ieee80211_node *ni; 3450 enum ieee80211_state ostate; 3451 usbd_status error = 0; 3452 3453 if (usbd_is_dying(sc->sc_udev)) 3454 return; 3455 3456 ostate = ic->ic_state; 3457 3458 switch (sc->sc_state) { 3459 case IEEE80211_S_INIT: 3460 if (ostate == IEEE80211_S_RUN) { 3461 /* turn link LED off */ 3462 (void)urtw_led_off(sc, URTW_LED_GPIO); 3463 } 3464 break; 3465 3466 case IEEE80211_S_SCAN: 3467 urtw_set_chan(sc, ic->ic_bss->ni_chan); 3468 if (!usbd_is_dying(sc->sc_udev)) 3469 timeout_add_msec(&sc->scan_to, 200); 3470 break; 3471 3472 case IEEE80211_S_AUTH: 3473 case IEEE80211_S_ASSOC: 3474 urtw_set_chan(sc, ic->ic_bss->ni_chan); 3475 break; 3476 3477 case IEEE80211_S_RUN: 3478 ni = ic->ic_bss; 3479 3480 /* setting bssid. */ 3481 error = urtw_set_bssid(sc, ni->ni_bssid); 3482 if (error != 0) 3483 goto fail; 3484 urtw_update_msr(sc); 3485 /* XXX maybe the below would be incorrect. */ 3486 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3487 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3488 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3489 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3490 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3491 if (error != 0) 3492 printf("%s: could not control LED (%d)\n", 3493 sc->sc_dev.dv_xname, error); 3494 break; 3495 } 3496 3497 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3498 3499 fail: 3500 if (error != 0) 3501 DPRINTF(("%s: error processing RUN state.", 3502 sc->sc_dev.dv_xname)); 3503 } 3504 3505 usbd_status 3506 urtw_8187b_update_wmm(struct urtw_softc *sc) 3507 { 3508 struct ieee80211com *ic = &sc->sc_ic; 3509 struct ieee80211_channel *c = ic->ic_ibss_chan; 3510 uint32_t data; 3511 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3512 usbd_status error; 3513 3514 sifs = 0xa; 3515 if (IEEE80211_IS_CHAN_G(c)) 3516 slot = 0x9; 3517 else 3518 slot = 0x14; 3519 3520 aifs = (2 * slot) + sifs; 3521 ecwmin = 3; 3522 ecwmax = 7; 3523 3524 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3525 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3526 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3527 3528 urtw_write32_m(sc, URTW_AC_VO, data); 3529 urtw_write32_m(sc, URTW_AC_VI, data); 3530 urtw_write32_m(sc, URTW_AC_BE, data); 3531 urtw_write32_m(sc, URTW_AC_BK, data); 3532 3533 fail: 3534 return (error); 3535 } 3536 3537 usbd_status 3538 urtw_8187b_reset(struct urtw_softc *sc) 3539 { 3540 uint8_t data; 3541 usbd_status error; 3542 3543 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3544 if (error) 3545 goto fail; 3546 3547 urtw_read8_m(sc, URTW_CONFIG3, &data); 3548 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3549 URTW_CONFIG3_GNT_SELECT); 3550 3551 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3552 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3553 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3554 3555 urtw_write8_m(sc, 0x61, 0x10); 3556 urtw_read8_m(sc, 0x62, &data); 3557 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3558 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3559 3560 urtw_read8_m(sc, URTW_CONFIG3, &data); 3561 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3562 3563 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3564 if (error) 3565 goto fail; 3566 3567 urtw_read8_m(sc, URTW_CMD, &data); 3568 data = (data & 2) | URTW_CMD_RST; 3569 urtw_write8_m(sc, URTW_CMD, data); 3570 usbd_delay_ms(sc->sc_udev, 100); 3571 3572 urtw_read8_m(sc, URTW_CMD, &data); 3573 if (data & URTW_CMD_RST) { 3574 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 3575 goto fail; 3576 } 3577 3578 fail: 3579 return (error); 3580 } 3581 3582 int 3583 urtw_8187b_init(struct ifnet *ifp) 3584 { 3585 struct urtw_softc *sc = ifp->if_softc; 3586 struct urtw_rf *rf = &sc->sc_rf; 3587 struct ieee80211com *ic = &sc->sc_ic; 3588 uint8_t data; 3589 usbd_status error; 3590 3591 urtw_stop(ifp, 0); 3592 3593 error = urtw_8187b_update_wmm(sc); 3594 if (error != 0) 3595 goto fail; 3596 error = urtw_8187b_reset(sc); 3597 if (error) 3598 goto fail; 3599 3600 /* Applying MAC address again. */ 3601 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3602 if (error) 3603 goto fail; 3604 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3605 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3606 if (error) 3607 goto fail; 3608 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3609 if (error) 3610 goto fail; 3611 3612 error = urtw_update_msr(sc); 3613 if (error) 3614 goto fail; 3615 3616 error = rf->init(rf); 3617 if (error != 0) 3618 goto fail; 3619 3620 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3621 URTW_CMD_RX_ENABLE); 3622 error = urtw_intr_enable(sc); 3623 if (error != 0) 3624 goto fail; 3625 3626 error = urtw_write8e(sc, 0x41, 0xf4); 3627 if (error != 0) 3628 goto fail; 3629 error = urtw_write8e(sc, 0x40, 0x00); 3630 if (error != 0) 3631 goto fail; 3632 error = urtw_write8e(sc, 0x42, 0x00); 3633 if (error != 0) 3634 goto fail; 3635 error = urtw_write8e(sc, 0x42, 0x01); 3636 if (error != 0) 3637 goto fail; 3638 error = urtw_write8e(sc, 0x40, 0x0f); 3639 if (error != 0) 3640 goto fail; 3641 error = urtw_write8e(sc, 0x42, 0x00); 3642 if (error != 0) 3643 goto fail; 3644 error = urtw_write8e(sc, 0x42, 0x01); 3645 if (error != 0) 3646 goto fail; 3647 3648 urtw_read8_m(sc, 0xdb, &data); 3649 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3650 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3651 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3652 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3653 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3654 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3655 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3656 urtw_write8_m(sc, 0x61, 0); 3657 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3658 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3659 urtw_write8_m(sc, 0xda, 0x10); 3660 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3661 3662 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3663 3664 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3665 3666 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3667 3668 /* Reset softc variables. */ 3669 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 3670 sc->sc_txtimer = 0; 3671 3672 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3673 error = urtw_open_pipes(sc); 3674 if (error != 0) 3675 goto fail; 3676 error = urtw_alloc_rx_data_list(sc); 3677 if (error != 0) 3678 goto fail; 3679 error = urtw_alloc_tx_data_list(sc); 3680 if (error != 0) 3681 goto fail; 3682 sc->sc_flags |= URTW_INIT_ONCE; 3683 } 3684 3685 error = urtw_rx_enable(sc); 3686 if (error != 0) 3687 goto fail; 3688 error = urtw_tx_enable(sc); 3689 if (error != 0) 3690 goto fail; 3691 3692 ifp->if_flags |= IFF_RUNNING; 3693 ifq_clr_oactive(&ifp->if_snd); 3694 3695 ifp->if_timer = 1; 3696 3697 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3698 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3699 else 3700 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3701 3702 fail: 3703 return (error); 3704 } 3705 3706 usbd_status 3707 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3708 { 3709 int i; 3710 usbd_status error; 3711 3712 for (i = 0; i < nitems(urtw_8187b_regtbl); i++) { 3713 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3714 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3715 } 3716 3717 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3718 urtw_write16_m(sc, URTW_INT_MIG, 0); 3719 3720 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3721 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3722 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3723 3724 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3725 3726 fail: 3727 return (error); 3728 } 3729 3730 usbd_status 3731 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3732 { 3733 usbd_status error; 3734 3735 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3736 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3737 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3738 usbd_delay_ms(sc->sc_udev, 100); 3739 3740 fail: 3741 return (error); 3742 } 3743 3744 usbd_status 3745 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3746 { 3747 struct ieee80211com *ic = &sc->sc_ic; 3748 struct ieee80211_channel *c = ic->ic_ibss_chan; 3749 uint8_t aifs, difs, eifs, sifs, slot; 3750 usbd_status error; 3751 3752 urtw_write8_m(sc, URTW_SIFS, 0x22); 3753 3754 sifs = 0xa; 3755 if (IEEE80211_IS_CHAN_G(c)) { 3756 slot = 0x9; 3757 difs = 0x1c; 3758 eifs = 0x5b; 3759 } else { 3760 slot = 0x14; 3761 difs = 0x32; 3762 eifs = 0x5b; 3763 } 3764 aifs = (2 * slot) + sifs; 3765 3766 urtw_write8_m(sc, URTW_SLOT, slot); 3767 3768 urtw_write8_m(sc, URTW_AC_VO, aifs); 3769 urtw_write8_m(sc, URTW_AC_VI, aifs); 3770 urtw_write8_m(sc, URTW_AC_BE, aifs); 3771 urtw_write8_m(sc, URTW_AC_BK, aifs); 3772 3773 urtw_write8_m(sc, URTW_DIFS, difs); 3774 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3775 3776 fail: 3777 return (error); 3778 } 3779 3780 usbd_status 3781 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3782 { 3783 struct urtw_softc *sc = rf->rf_sc; 3784 int i; 3785 uint8_t data; 3786 usbd_status error; 3787 3788 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3789 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3790 urtw_read8_m(sc, URTW_CW_CONF, &data); 3791 urtw_write8_m(sc, URTW_CW_CONF, data | 3792 URTW_CW_CONF_PERPACKET_RETRY); 3793 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3794 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3795 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3796 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3797 3798 /* Auto rate fallback control. */ 3799 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3800 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3801 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3802 URTW_RATE_FALLBACK_ENABLE); 3803 3804 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3805 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3806 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3807 3808 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3809 if (error) 3810 goto fail; 3811 urtw_read8_m(sc, URTW_CONFIG1, &data); 3812 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3813 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3814 if (error) 3815 goto fail; 3816 3817 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3818 urtw_8225v2_b_config_mac(sc); 3819 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3820 3821 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3822 if (error) 3823 goto fail; 3824 urtw_read8_m(sc, URTW_CONFIG3, &data); 3825 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3826 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3827 if (error) 3828 goto fail; 3829 3830 urtw_8225v2_b_init_rfe(sc); 3831 3832 for (i = 0; i < nitems(urtw_8225v2_b_rf); i++) { 3833 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3834 urtw_8225v2_b_rf[i].val); 3835 } 3836 3837 for (i = 0; i < nitems(urtw_8225v2_rxgain); i++) { 3838 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3839 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3840 } 3841 3842 urtw_8225_write(sc, 0x03, 0x080); 3843 urtw_8225_write(sc, 0x05, 0x004); 3844 urtw_8225_write(sc, 0x00, 0x0b7); 3845 urtw_8225_write(sc, 0x02, 0xc4d); 3846 urtw_8225_write(sc, 0x02, 0x44d); 3847 urtw_8225_write(sc, 0x00, 0x2bf); 3848 3849 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3850 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3851 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3852 3853 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3854 for (i = 0; i < nitems(urtw_8225v2_agc); i++) { 3855 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3856 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3857 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3858 } 3859 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3860 3861 for (i = 0; i < nitems(urtw_8225v2_ofdm); i++) 3862 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3863 3864 urtw_8225v2_b_update_chan(sc); 3865 3866 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3867 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3868 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3869 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3870 3871 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3872 fail: 3873 return (error); 3874 } 3875 3876 usbd_status 3877 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3878 { 3879 struct urtw_softc *sc = rf->rf_sc; 3880 usbd_status error; 3881 3882 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3883 if (error) 3884 goto fail; 3885 3886 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3887 /* 3888 * Delay removed from 8185 to 8187. 3889 * usbd_delay_ms(sc->sc_udev, 10); 3890 */ 3891 3892 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3893 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3894 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3895 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3896 3897 fail: 3898 return (error); 3899 } 3900 3901 usbd_status 3902 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3903 { 3904 int i; 3905 uint8_t *cck_pwrtable; 3906 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3907 ofdm_pwrlvl_max; 3908 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3909 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3910 usbd_status error; 3911 3912 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3913 cck_pwrlvl_min = 0; 3914 cck_pwrlvl_max = 15; 3915 ofdm_pwrlvl_min = 2; 3916 ofdm_pwrlvl_max = 17; 3917 } else { 3918 cck_pwrlvl_min = 7; 3919 cck_pwrlvl_max = 22; 3920 ofdm_pwrlvl_min = 10; 3921 ofdm_pwrlvl_max = 25; 3922 } 3923 3924 /* CCK power setting */ 3925 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3926 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3927 3928 cck_pwrlvl += sc->sc_txpwr_cck_base; 3929 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3930 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3931 3932 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3933 urtw_8225v2_txpwr_cck; 3934 3935 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3936 if (cck_pwrlvl <= 6) 3937 ; /* do nothing */ 3938 else if (cck_pwrlvl <= 11) 3939 cck_pwrtable += 8; 3940 else 3941 cck_pwrtable += 16; 3942 } else { 3943 if (cck_pwrlvl <= 5) 3944 ; /* do nothing */ 3945 else if (cck_pwrlvl <= 11) 3946 cck_pwrtable += 8; 3947 else if (cck_pwrlvl <= 17) 3948 cck_pwrtable += 16; 3949 else 3950 cck_pwrtable += 24; 3951 } 3952 3953 for (i = 0; i < 8; i++) { 3954 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3955 } 3956 3957 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3958 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3959 /* 3960 * Delay removed from 8185 to 8187. 3961 * usbd_delay_ms(sc->sc_udev, 1); 3962 */ 3963 3964 /* OFDM power setting */ 3965 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3966 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3967 3968 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3969 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3970 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3971 3972 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3973 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3974 3975 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3976 if (ofdm_pwrlvl <= 11) { 3977 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3978 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3979 } else { 3980 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3981 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3982 } 3983 } else { 3984 if (ofdm_pwrlvl <= 11) { 3985 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3986 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3987 } else if (ofdm_pwrlvl <= 17) { 3988 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3989 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3990 } else { 3991 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3992 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3993 } 3994 } 3995 3996 /* 3997 * Delay removed from 8185 to 8187. 3998 * usbd_delay_ms(sc->sc_udev, 1); 3999 */ 4000 fail: 4001 return (error); 4002 } 4003 4004 int 4005 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4006 { 4007 int error; 4008 4009 urtw_write32_m(sc, URTW_BSSID, 4010 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4011 urtw_write16_m(sc, URTW_BSSID + 4, 4012 bssid[4] | bssid[5] << 8); 4013 4014 return 0; 4015 4016 fail: 4017 return error; 4018 } 4019 4020 int 4021 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4022 { 4023 int error; 4024 4025 urtw_write32_m(sc, URTW_MAC0, 4026 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4027 urtw_write16_m(sc, URTW_MAC4, 4028 addr[4] | addr[5] << 8); 4029 4030 return 0; 4031 4032 fail: 4033 return error; 4034 } 4035