1 /* $NetBSD: i915_irq.h,v 1.2 2021/12/18 23:45:28 riastradh Exp $ */
2
3 /* SPDX-License-Identifier: MIT */
4 /*
5 * Copyright © 2019 Intel Corporation
6 */
7
8 #ifndef __I915_IRQ_H__
9 #define __I915_IRQ_H__
10
11 #include <linux/ktime.h>
12 #include <linux/types.h>
13
14 #include "display/intel_display.h"
15 #include "i915_reg.h"
16
17 struct drm_crtc;
18 struct drm_device;
19 struct drm_display_mode;
20 struct drm_i915_private;
21 struct intel_crtc;
22 struct intel_uncore;
23
24 void intel_irq_init(struct drm_i915_private *dev_priv);
25 void intel_irq_fini(struct drm_i915_private *dev_priv);
26 int intel_irq_install(struct drm_i915_private *dev_priv);
27 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
28
29 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
30 enum pipe pipe);
31 void
32 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
33 u32 status_mask);
34
35 void
36 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
37 u32 status_mask);
38
39 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
40 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
41
42 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
43 u32 mask,
44 u32 bits);
45 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
46 u32 interrupt_mask,
47 u32 enabled_irq_mask);
48 static inline void
ilk_enable_display_irq(struct drm_i915_private * dev_priv,u32 bits)49 ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
50 {
51 ilk_update_display_irq(dev_priv, bits, bits);
52 }
53 static inline void
ilk_disable_display_irq(struct drm_i915_private * dev_priv,u32 bits)54 ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
55 {
56 ilk_update_display_irq(dev_priv, bits, 0);
57 }
58 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
59 enum pipe pipe,
60 u32 interrupt_mask,
61 u32 enabled_irq_mask);
bdw_enable_pipe_irq(struct drm_i915_private * dev_priv,enum pipe pipe,u32 bits)62 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
63 enum pipe pipe, u32 bits)
64 {
65 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
66 }
bdw_disable_pipe_irq(struct drm_i915_private * dev_priv,enum pipe pipe,u32 bits)67 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
68 enum pipe pipe, u32 bits)
69 {
70 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
71 }
72 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
73 u32 interrupt_mask,
74 u32 enabled_irq_mask);
75 static inline void
ibx_enable_display_interrupt(struct drm_i915_private * dev_priv,u32 bits)76 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
77 {
78 ibx_display_interrupt_update(dev_priv, bits, bits);
79 }
80 static inline void
ibx_disable_display_interrupt(struct drm_i915_private * dev_priv,u32 bits)81 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
82 {
83 ibx_display_interrupt_update(dev_priv, bits, 0);
84 }
85
86 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
87 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
88 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
89 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
90 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
91 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
92 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
93 u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
94
95 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
96 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
97 bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
98 void intel_synchronize_irq(struct drm_i915_private *i915);
99
100 int intel_get_crtc_scanline(struct intel_crtc *crtc);
101 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
102 u8 pipe_mask);
103 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
104 u8 pipe_mask);
105
106 bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
107 bool in_vblank_irq, int *vpos, int *hpos,
108 ktime_t *stime, ktime_t *etime,
109 const struct drm_display_mode *mode);
110
111 u32 i915_get_vblank_counter(struct drm_crtc *crtc);
112 u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
113
114 int i8xx_enable_vblank(struct drm_crtc *crtc);
115 int i915gm_enable_vblank(struct drm_crtc *crtc);
116 int i965_enable_vblank(struct drm_crtc *crtc);
117 int ilk_enable_vblank(struct drm_crtc *crtc);
118 int bdw_enable_vblank(struct drm_crtc *crtc);
119 void i8xx_disable_vblank(struct drm_crtc *crtc);
120 void i915gm_disable_vblank(struct drm_crtc *crtc);
121 void i965_disable_vblank(struct drm_crtc *crtc);
122 void ilk_disable_vblank(struct drm_crtc *crtc);
123 void bdw_disable_vblank(struct drm_crtc *crtc);
124
125 void gen2_irq_reset(struct intel_uncore *uncore);
126 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
127 i915_reg_t iir, i915_reg_t ier);
128
129 void gen2_irq_init(struct intel_uncore *uncore,
130 u32 imr_val, u32 ier_val);
131 void gen3_irq_init(struct intel_uncore *uncore,
132 i915_reg_t imr, u32 imr_val,
133 i915_reg_t ier, u32 ier_val,
134 i915_reg_t iir);
135
136 #define GEN8_IRQ_RESET_NDX(uncore, type, which) \
137 ({ \
138 unsigned int which_ = which; \
139 gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
140 GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
141 })
142
143 #define GEN3_IRQ_RESET(uncore, type) \
144 gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
145
146 #define GEN2_IRQ_RESET(uncore) \
147 gen2_irq_reset(uncore)
148
149 #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
150 ({ \
151 unsigned int which_ = which; \
152 gen3_irq_init((uncore), \
153 GEN8_##type##_IMR(which_), imr_val, \
154 GEN8_##type##_IER(which_), ier_val, \
155 GEN8_##type##_IIR(which_)); \
156 })
157
158 #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
159 gen3_irq_init((uncore), \
160 type##IMR, imr_val, \
161 type##IER, ier_val, \
162 type##IIR)
163
164 #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
165 gen2_irq_init((uncore), imr_val, ier_val)
166
167 #endif /* __I915_IRQ_H__ */
168