1 /* $NetBSD: i80321_timer.c,v 1.22 2018/07/12 10:46:42 maxv Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Timer/clock support for the Intel i80321 I/O processor.
40 */
41
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: i80321_timer.c,v 1.22 2018/07/12 10:46:42 maxv Exp $");
44
45 #include "opt_i80321.h"
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/time.h>
51 #include <sys/timetc.h>
52
53 #include <dev/clock_subr.h>
54
55 #include <sys/bus.h>
56 #include <arm/cpufunc.h>
57
58 #include <arm/xscale/i80321reg.h>
59 #include <arm/xscale/i80321var.h>
60
61 void (*i80321_hardclock_hook)(void);
62
63 #ifndef COUNTS_PER_SEC
64 #define COUNTS_PER_SEC 200000000 /* 200MHz */
65 #endif
66 #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000)
67
68 static void tmr1_tc_init(void);
69
70 static void *clock_ih;
71
72 static uint32_t counts_per_hz;
73
74 int clockhandler(void *);
75
76 __unused static inline uint32_t
tmr0_read(void)77 tmr0_read(void)
78 {
79 uint32_t rv;
80
81 __asm volatile("mrc p6, 0, %0, c0, c1, 0"
82 : "=r" (rv));
83 return (rv);
84 }
85
86 static inline void
tmr0_write(uint32_t val)87 tmr0_write(uint32_t val)
88 {
89
90 __asm volatile("mcr p6, 0, %0, c0, c1, 0"
91 :
92 : "r" (val));
93 }
94
95 static inline uint32_t
tcr0_read(void)96 tcr0_read(void)
97 {
98 uint32_t rv;
99
100 __asm volatile("mrc p6, 0, %0, c2, c1, 0"
101 : "=r" (rv));
102 return (rv);
103 }
104
105 static inline void
tcr0_write(uint32_t val)106 tcr0_write(uint32_t val)
107 {
108
109 __asm volatile("mcr p6, 0, %0, c2, c1, 0"
110 :
111 : "r" (val));
112 }
113
114 static inline void
trr0_write(uint32_t val)115 trr0_write(uint32_t val)
116 {
117
118 __asm volatile("mcr p6, 0, %0, c4, c1, 0"
119 :
120 : "r" (val));
121 }
122
123 __unused static inline uint32_t
tmr1_read(void)124 tmr1_read(void)
125 {
126 uint32_t rv;
127
128 __asm volatile("mrc p6, 0, %0, c1, c1, 0"
129 : "=r" (rv));
130 return (rv);
131 }
132
133 static inline void
tmr1_write(uint32_t val)134 tmr1_write(uint32_t val)
135 {
136
137 __asm volatile("mcr p6, 0, %0, c1, c1, 0"
138 :
139 : "r" (val));
140 }
141
142 static inline uint32_t
tcr1_read(void)143 tcr1_read(void)
144 {
145 uint32_t rv;
146
147 __asm volatile("mrc p6, 0, %0, c3, c1, 0"
148 : "=r" (rv));
149 return (rv);
150 }
151
152 static inline void
tcr1_write(uint32_t val)153 tcr1_write(uint32_t val)
154 {
155
156 __asm volatile("mcr p6, 0, %0, c3, c1, 0"
157 :
158 : "r" (val));
159 }
160
161 static inline void
trr1_write(uint32_t val)162 trr1_write(uint32_t val)
163 {
164
165 __asm volatile("mcr p6, 0, %0, c5, c1, 0"
166 :
167 : "r" (val));
168 }
169
170 static inline void
tisr_write(uint32_t val)171 tisr_write(uint32_t val)
172 {
173
174 __asm volatile("mcr p6, 0, %0, c6, c1, 0"
175 :
176 : "r" (val));
177 }
178
179 /*
180 * i80321_calibrate_delay:
181 *
182 * Calibrate the delay loop.
183 */
184 void
i80321_calibrate_delay(void)185 i80321_calibrate_delay(void)
186 {
187
188 /*
189 * Just use hz=100 for now -- we'll adjust it, if necessary,
190 * in cpu_initclocks().
191 */
192 counts_per_hz = COUNTS_PER_SEC / 100;
193
194 tmr0_write(0); /* stop timer */
195 tisr_write(TISR_TMR0); /* clear interrupt */
196 trr0_write(counts_per_hz); /* reload value */
197 tcr0_write(counts_per_hz); /* current value */
198
199 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
200 }
201
202 /*
203 * cpu_initclocks:
204 *
205 * Initialize the clock and get them going.
206 */
207 void
cpu_initclocks(void)208 cpu_initclocks(void)
209 {
210 u_int oldirqstate;
211
212 if (hz < 50 || COUNTS_PER_SEC % hz) {
213 aprint_error("Cannot get %d Hz clock; using 100 Hz\n", hz);
214 hz = 100;
215 }
216
217 /*
218 * We only have one timer available; stathz and profhz are
219 * always left as 0 (the upper-layer clock code deals with
220 * this situation).
221 */
222 if (stathz != 0)
223 aprint_error("Cannot get %d Hz statclock\n", stathz);
224 stathz = 0;
225
226 if (profhz != 0)
227 aprint_error("Cannot get %d Hz profclock\n", profhz);
228 profhz = 0;
229
230 /* Report the clock frequency. */
231 aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz);
232
233 oldirqstate = disable_interrupts(I32_bit);
234
235 /* Hook up the clock interrupt handler. */
236 clock_ih = i80321_intr_establish(ICU_INT_TMR0, IPL_CLOCK,
237 clockhandler, NULL);
238 if (clock_ih == NULL)
239 panic("cpu_initclocks: unable to register timer interrupt");
240
241 /* Set up the new clock parameters. */
242
243 tmr0_write(0); /* stop timer */
244 tisr_write(TISR_TMR0); /* clear interrupt */
245
246 counts_per_hz = COUNTS_PER_SEC / hz;
247
248 trr0_write(counts_per_hz); /* reload value */
249 tcr0_write(counts_per_hz); /* current value */
250
251 tmr0_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
252
253 restore_interrupts(oldirqstate);
254
255 tmr1_tc_init();
256 }
257
258 /*
259 * setstatclockrate:
260 *
261 * Set the rate of the statistics clock.
262 *
263 * We assume that hz is either stathz or profhz, and that neither
264 * will change after being set by cpu_initclocks(). We could
265 * recalculate the intervals here, but that would be a pain.
266 */
267 void
setstatclockrate(int newhz)268 setstatclockrate(int newhz)
269 {
270
271 /*
272 * XXX Use TMR1?
273 */
274 }
275
276 static inline uint32_t
tmr1_tc_get(struct timecounter * tch)277 tmr1_tc_get(struct timecounter *tch)
278 {
279 return (~tcr1_read());
280 }
281
282 void
tmr1_tc_init(void)283 tmr1_tc_init(void)
284 {
285 static struct timecounter tmr1_tc = {
286 .tc_get_timecount = tmr1_tc_get,
287 .tc_frequency = COUNTS_PER_SEC,
288 .tc_counter_mask = ~0,
289 .tc_name = "tmr1_count",
290 .tc_quality = 100,
291 };
292
293 /* program the tc */
294 trr1_write(~0); /* reload value */
295 tcr1_write(~0); /* current value */
296
297 tmr1_write(TMRx_ENABLE|TMRx_RELOAD|TMRx_CSEL_CORE);
298
299
300 trr1_write(~0);
301 tc_init(&tmr1_tc);
302 }
303
304 /*
305 * delay:
306 *
307 * Delay for at least N microseconds.
308 */
309 void
delay(u_int n)310 delay(u_int n)
311 {
312 uint32_t cur, last, delta, usecs;
313
314 /*
315 * This works by polling the timer and counting the
316 * number of microseconds that go by.
317 */
318 last = tcr0_read();
319 delta = usecs = 0;
320
321 while (n > usecs) {
322 cur = tcr0_read();
323
324 /* Check to see if the timer has wrapped around. */
325 if (last < cur)
326 delta += (last + (counts_per_hz - cur));
327 else
328 delta += (last - cur);
329
330 last = cur;
331
332 if (delta >= COUNTS_PER_USEC) {
333 usecs += delta / COUNTS_PER_USEC;
334 delta %= COUNTS_PER_USEC;
335 }
336 }
337 }
338
339 /*
340 * clockhandler:
341 *
342 * Handle the hardclock interrupt.
343 */
344 int
clockhandler(void * arg)345 clockhandler(void *arg)
346 {
347 struct clockframe *frame = arg;
348
349 tisr_write(TISR_TMR0);
350
351 hardclock(frame);
352
353 if (i80321_hardclock_hook != NULL)
354 (*i80321_hardclock_hook)();
355
356 return (1);
357 }
358