1 /* $NetBSD: intel_engine.h,v 1.5 2021/12/19 12:40:59 riastradh Exp $ */
2
3 /* SPDX-License-Identifier: MIT */
4 #ifndef _INTEL_RINGBUFFER_H_
5 #define _INTEL_RINGBUFFER_H_
6
7 #include <drm/drm_util.h>
8
9 #include <linux/hashtable.h>
10 #include <linux/irq_work.h>
11 #include <linux/random.h>
12 #include <linux/seqlock.h>
13
14 #include "i915_pmu.h"
15 #include "i915_reg.h"
16 #include "i915_request.h"
17 #include "i915_selftest.h"
18 #include "gt/intel_timeline.h"
19 #include "intel_engine_types.h"
20 #include "intel_gpu_commands.h"
21 #include "intel_workarounds.h"
22
23 struct drm_printer;
24 struct intel_gt;
25
26 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
27 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
28 * to give some inclination as to some of the magic values used in the various
29 * workarounds!
30 */
31 #define CACHELINE_BYTES 64
32 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
33
34 #define ENGINE_TRACE(e, fmt, ...) do { \
35 const struct intel_engine_cs *e__ __maybe_unused = (e); \
36 GEM_TRACE("%s %s: " fmt, \
37 dev_name(e__->i915->drm.dev), e__->name, \
38 ##__VA_ARGS__); \
39 } while (0)
40
41 /*
42 * The register defines to be used with the following macros need to accept a
43 * base param, e.g:
44 *
45 * REG_FOO(base) _MMIO((base) + <relative offset>)
46 * ENGINE_READ(engine, REG_FOO);
47 *
48 * register arrays are to be defined and accessed as follows:
49 *
50 * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
51 * ENGINE_READ_IDX(engine, REG_BAR, i)
52 */
53
54 #define __ENGINE_REG_OP(op__, engine__, ...) \
55 intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
56
57 #define __ENGINE_READ_OP(op__, engine__, reg__) \
58 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
59
60 #define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__)
61 #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__)
62 #define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__)
63 #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
64 #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
65
66 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
67 __ENGINE_REG_OP(read64_2x32, (engine__), \
68 lower_reg__((engine__)->mmio_base), \
69 upper_reg__((engine__)->mmio_base))
70
71 #define ENGINE_READ_IDX(engine__, reg__, idx__) \
72 __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
73
74 #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
75 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
76
77 #define ENGINE_WRITE16(...) __ENGINE_WRITE_OP(write16, __VA_ARGS__)
78 #define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
79 #define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
80
81 #define GEN6_RING_FAULT_REG_READ(engine__) \
82 intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
83
84 #define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
85 intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
86
87 #define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
88 ({ \
89 u32 __val; \
90 \
91 __val = intel_uncore_read((engine__)->uncore, \
92 RING_FAULT_REG(engine__)); \
93 __val &= ~(clear__); \
94 __val |= (set__); \
95 intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
96 __val); \
97 })
98
99 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
100 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
101 */
102
103 static inline unsigned int
execlists_num_ports(const struct intel_engine_execlists * const execlists)104 execlists_num_ports(const struct intel_engine_execlists * const execlists)
105 {
106 return execlists->port_mask + 1;
107 }
108
109 static inline struct i915_request *
execlists_active(const struct intel_engine_execlists * execlists)110 execlists_active(const struct intel_engine_execlists *execlists)
111 {
112 return *READ_ONCE(execlists->active);
113 }
114
115 #ifdef __NetBSD__
116 static inline int
execlists_active_lock_bh(struct intel_engine_execlists * execlists)117 execlists_active_lock_bh(struct intel_engine_execlists *execlists)
118 {
119 int s = splsoftserial(); /* prevent local softirq and lock recursion */
120 tasklet_lock(&execlists->tasklet);
121 return s;
122 }
123
124 static inline void
execlists_active_unlock_bh(struct intel_engine_execlists * execlists,int s)125 execlists_active_unlock_bh(struct intel_engine_execlists *execlists, int s)
126 {
127 tasklet_unlock(&execlists->tasklet);
128 splx(s); /* restore softirq, and kick ksoftirqd! */
129 }
130 #else
131 static inline void
execlists_active_lock_bh(struct intel_engine_execlists * execlists)132 execlists_active_lock_bh(struct intel_engine_execlists *execlists)
133 {
134 local_bh_disable(); /* prevent local softirq and lock recursion */
135 tasklet_lock(&execlists->tasklet);
136 }
137
138 static inline void
execlists_active_unlock_bh(struct intel_engine_execlists * execlists)139 execlists_active_unlock_bh(struct intel_engine_execlists *execlists)
140 {
141 tasklet_unlock(&execlists->tasklet);
142 local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
143 }
144 #endif
145
146 struct i915_request *
147 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
148
149 static inline u32
intel_read_status_page(const struct intel_engine_cs * engine,int reg)150 intel_read_status_page(const struct intel_engine_cs *engine, int reg)
151 {
152 /* Ensure that the compiler doesn't optimize away the load. */
153 return READ_ONCE(engine->status_page.addr[reg]);
154 }
155
156 static inline void
intel_write_status_page(struct intel_engine_cs * engine,int reg,u32 value)157 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
158 {
159 /* Writing into the status page should be done sparingly. Since
160 * we do when we are uncertain of the device state, we take a bit
161 * of extra paranoia to try and ensure that the HWS takes the value
162 * we give and that it doesn't end up trapped inside the CPU!
163 */
164 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
165 mb();
166 clflush(&engine->status_page.addr[reg]);
167 engine->status_page.addr[reg] = value;
168 clflush(&engine->status_page.addr[reg]);
169 mb();
170 } else {
171 WRITE_ONCE(engine->status_page.addr[reg], value);
172 }
173 }
174
175 /*
176 * Reads a dword out of the status page, which is written to from the command
177 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
178 * MI_STORE_DATA_IMM.
179 *
180 * The following dwords have a reserved meaning:
181 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
182 * 0x04: ring 0 head pointer
183 * 0x05: ring 1 head pointer (915-class)
184 * 0x06: ring 2 head pointer (915-class)
185 * 0x10-0x1b: Context status DWords (GM45)
186 * 0x1f: Last written status offset. (GM45)
187 * 0x20-0x2f: Reserved (Gen6+)
188 *
189 * The area from dword 0x30 to 0x3ff is available for driver usage.
190 */
191 #define I915_GEM_HWS_PREEMPT 0x32
192 #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
193 #define I915_GEM_HWS_SEQNO 0x40
194 #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
195 #define I915_GEM_HWS_SCRATCH 0x80
196 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH * sizeof(u32))
197
198 #define I915_HWS_CSB_BUF0_INDEX 0x10
199 #define I915_HWS_CSB_WRITE_INDEX 0x1f
200 #define CNL_HWS_CSB_WRITE_INDEX 0x2f
201
202 void intel_engine_stop(struct intel_engine_cs *engine);
203 void intel_engine_cleanup(struct intel_engine_cs *engine);
204
205 int intel_engines_init_mmio(struct intel_gt *gt);
206 int intel_engines_init(struct intel_gt *gt);
207
208 void intel_engines_release(struct intel_gt *gt);
209 void intel_engines_free(struct intel_gt *gt);
210
211 int intel_engine_init_common(struct intel_engine_cs *engine);
212 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
213
214 int intel_ring_submission_setup(struct intel_engine_cs *engine);
215
216 int intel_engine_stop_cs(struct intel_engine_cs *engine);
217 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
218
219 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
220
221 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
222 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
223
224 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
225 struct intel_instdone *instdone);
226
227 void intel_engine_init_execlists(struct intel_engine_cs *engine);
228
229 void intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
230 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
231
232 void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
233
234 static inline void
intel_engine_signal_breadcrumbs(struct intel_engine_cs * engine)235 intel_engine_signal_breadcrumbs(struct intel_engine_cs *engine)
236 {
237 irq_work_queue(&engine->breadcrumbs.irq_work);
238 }
239
240 void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
241 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
242
243 void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
244 struct drm_printer *p);
245
gen8_emit_pipe_control(u32 * batch,u32 flags,u32 offset)246 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
247 {
248 memset(batch, 0, 6 * sizeof(u32));
249
250 batch[0] = GFX_OP_PIPE_CONTROL(6);
251 batch[1] = flags;
252 batch[2] = offset;
253
254 return batch + 6;
255 }
256
257 static inline u32 *
gen8_emit_ggtt_write_rcs(u32 * cs,u32 value,u32 gtt_offset,u32 flags)258 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
259 {
260 /* We're using qword write, offset should be aligned to 8 bytes. */
261 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
262
263 /* w/a for post sync ops following a GPGPU operation we
264 * need a prior CS_STALL, which is emitted by the flush
265 * following the batch.
266 */
267 *cs++ = GFX_OP_PIPE_CONTROL(6);
268 *cs++ = flags | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;
269 *cs++ = gtt_offset;
270 *cs++ = 0;
271 *cs++ = value;
272 /* We're thrashing one dword of HWS. */
273 *cs++ = 0;
274
275 return cs;
276 }
277
278 static inline u32 *
gen8_emit_ggtt_write(u32 * cs,u32 value,u32 gtt_offset,u32 flags)279 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
280 {
281 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
282 GEM_BUG_ON(gtt_offset & (1 << 5));
283 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
284 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
285
286 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;
287 *cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;
288 *cs++ = 0;
289 *cs++ = value;
290
291 return cs;
292 }
293
__intel_engine_reset(struct intel_engine_cs * engine,bool stalled)294 static inline void __intel_engine_reset(struct intel_engine_cs *engine,
295 bool stalled)
296 {
297 if (engine->reset.rewind)
298 engine->reset.rewind(engine, stalled);
299 engine->serial++; /* contexts lost */
300 }
301
302 bool intel_engines_are_idle(struct intel_gt *gt);
303 bool intel_engine_is_idle(struct intel_engine_cs *engine);
304 void intel_engine_flush_submission(struct intel_engine_cs *engine);
305
306 void intel_engines_reset_default_submission(struct intel_gt *gt);
307
308 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
309
310 __printf(3, 4)
311 void intel_engine_dump(struct intel_engine_cs *engine,
312 struct drm_printer *m,
313 const char *header, ...);
314
315 int intel_enable_engine_stats(struct intel_engine_cs *engine);
316 void intel_disable_engine_stats(struct intel_engine_cs *engine);
317
318 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
319
320 struct i915_request *
321 intel_engine_find_active_request(struct intel_engine_cs *engine);
322
323 u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
324
325 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
326
inject_preempt_hang(struct intel_engine_execlists * execlists)327 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
328 {
329 if (!execlists->preempt_hang.inject_hang)
330 return false;
331
332 complete(&execlists->preempt_hang.completion);
333 return true;
334 }
335
336 #else
337
inject_preempt_hang(struct intel_engine_execlists * execlists)338 static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists)
339 {
340 return false;
341 }
342
343 #endif
344
345 void intel_engine_init_active(struct intel_engine_cs *engine,
346 unsigned int subclass);
347 #define ENGINE_PHYSICAL 0
348 #define ENGINE_MOCK 1
349 #define ENGINE_VIRTUAL 2
350
351 static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs * engine)352 intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
353 {
354 if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
355 return false;
356
357 return intel_engine_has_preemption(engine);
358 }
359
360 static inline bool
intel_engine_has_timeslices(const struct intel_engine_cs * engine)361 intel_engine_has_timeslices(const struct intel_engine_cs *engine)
362 {
363 if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
364 return false;
365
366 return intel_engine_has_semaphores(engine);
367 }
368
369 #endif /* _INTEL_RINGBUFFER_H_ */
370