1 /* $NetBSD: geodereg.h,v 1.9 2009/10/19 23:19:38 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 2005 David Young. All rights reserved. 5 * 6 * This code was written by David Young. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY DAVID YOUNG ``AS IS'' AND ANY 18 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 20 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DAVID 21 * YOUNG BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 28 * OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Register definitions for the AMD Geode SC1100. 33 */ 34 35 #ifndef _I386_PCI_GEODEREG_H_ 36 #define _I386_PCI_GEODEREG_H_ 37 38 #include <lib/libkern/libkern.h> 39 40 /* AMD Geode SC1100 X-Bus PCI Configuration Register: General 41 * Configuration Block Scratchpad. Set to 0x00000000 after chip reset. 42 * The BIOS writes the base address of the General Configuration 43 * Block to this register. 44 */ 45 #define SC1100_XBUS_CBA_SCRATCHPAD 0x64 46 47 #define SC1100_GCB_SIZE 64 48 49 /* watchdog timeout register, 16 bits. */ 50 #define SC1100_GCB_WDTO 0x00 51 52 /* Watchdog configuration register, 16 bits. */ 53 #define SC1100_GCB_WDCNFG 0x02 54 #define SC1100_WDCNFG_RESERVED __BITS(15,9) /* write as read */ 55 56 /* 32kHz clock power-down, 0: clock is enabled, 1: clock is disabled. */ 57 #define SC1100_WDCNFG_WD32KPD __BIT(8) 58 59 /* Watchdog event type 1, and type 2 60 * 61 * 00: no action (default after POR# is asserted) 62 * 01: interrupt 63 * 10: SMI 64 * 11: system reset 65 */ 66 #define SC1100_WDCNFG_WDTYPE2_MASK __BITS(7,6) 67 #define SC1100_WDCNFG_WDTYPE1_MASK __BITS(5,4) 68 69 #define SC1100_WDCNFG_WDTYPE2_NOACTION __SHIFTIN(0, SC1100_WDCNFG_WDTYPE2_MASK) 70 #define SC1100_WDCNFG_WDTYPE2_INTERRUPT __SHIFTIN(1, SC1100_WDCNFG_WDTYPE2_MASK) 71 #define SC1100_WDCNFG_WDTYPE2_SMI __SHIFTIN(2, SC1100_WDCNFG_WDTYPE2_MASK) 72 #define SC1100_WDCNFG_WDTYPE2_RESET __SHIFTIN(3, SC1100_WDCNFG_WDTYPE2_MASK) 73 74 #define SC1100_WDCNFG_WDTYPE1_NOACTION __SHIFTIN(0, SC1100_WDCNFG_WDTYPE1_MASK) 75 #define SC1100_WDCNFG_WDTYPE1_INTERRUPT __SHIFTIN(1, SC1100_WDCNFG_WDTYPE1_MASK) 76 #define SC1100_WDCNFG_WDTYPE1_SMI __SHIFTIN(2, SC1100_WDCNFG_WDTYPE1_MASK) 77 #define SC1100_WDCNFG_WDTYPE1_RESET __SHIFTIN(3, SC1100_WDCNFG_WDTYPE1_MASK) 78 79 /* Watchdog timer prescaler 80 * 81 * The prescaler divisor is 2**WDPRES. 1110 (0xe) and 1111 (0xf) are 82 * reserved values. 83 */ 84 #define SC1100_WDCNFG_WDPRES_MASK __BITS(3,0) 85 #define SC1100_WDCNFG_WDPRES_MAX 0xd 86 87 /* Watchdog status register, 8 bits. */ 88 #define SC1100_GCB_WDSTS 0x04 89 #define SC1100_WDSTS_RESERVED __BIT(7,4) /* write as read */ 90 /* Set to 1 when watchdog reset is asserted. Read-only. Reset either by 91 * POR# (power-on reset) or by writing 0 to WDOVF. 92 */ 93 #define SC1100_WDSTS_WDRST __BIT(3) 94 /* Set to 1 when watchdog SMI is asserted. Read-only. Reset either by 95 * POR# (power-on reset) or by writing 0 to WDOVF. 96 */ 97 #define SC1100_WDSTS_WDSMI __BIT(2) 98 /* Set to 1 when watchdog interrupt is asserted. Read-only. Reset either by 99 * POR# (power-on reset) or by writing 0 to WDOVF. 100 */ 101 #define SC1100_WDSTS_WDINT __BIT(1) 102 /* Set to 1 when watchdog overflow is asserted. Reset either by 103 * POR# (power-on reset) or by writing 1 to this bit. 104 */ 105 #define SC1100_WDSTS_WDOVF __BIT(0) 106 107 /* 108 * Helpful constants 109 */ 110 111 /* maximum watchdog interval in seconds */ 112 #define SC1100_WDIVL_MAX ((1 << SC1100_WDCNFG_WDPRES_MAX) * \ 113 UINT16_MAX / SC1100_WDCLK_HZ) 114 /* watchdog clock rate in Hertz */ 115 #define SC1100_WDCLK_HZ 32000 116 117 /* 118 * high resolution timer 119 */ 120 #define SC1100_GCB_TMVALUE_L 0x08 /* timer value */ 121 122 #define SC1100_GCB_TMSTS_B 0x0c /* status */ 123 #define SC1100_TMSTS_OVFL __BIT(0) /* set: overflow */ 124 125 #define SC1100_GCB_TMCNFG_B 0x0d /* configuration */ 126 #define SC1100_TMCNFG_TM27MPD __BIT(2) /* set: power down on SUSPA# */ 127 #define SC1100_TMCNFG_TMCLKSEL __BIT(1) /* set: 27MHz clock, clear: 1MHz */ 128 #define SC1100_TMCNFG_TMEN __BIT(0) /* set: timer interrupt enabled */ 129 130 #define SC1100_GCB_IID_B 0x3c /* chip identification register */ 131 132 #define SC1100_GCB_REV_B 0x3d /* revision register */ 133 134 #endif /* _I386_PCI_GEODEREG_H_ */ 135