1 /* $NetBSD: dwc_mmc.c,v 1.31 2024/02/09 17:16:42 skrll Exp $ */
2
3 /*-
4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: dwc_mmc.c,v 1.31 2024/02/09 17:16:42 skrll Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/proc.h>
39
40 #include <dev/sdmmc/sdmmcvar.h>
41 #include <dev/sdmmc/sdmmcchip.h>
42 #include <dev/sdmmc/sdmmc_ioreg.h>
43
44 #include <dev/ic/dwc_mmc_reg.h>
45 #include <dev/ic/dwc_mmc_var.h>
46
47 #define DWC_MMC_NDESC 64
48
49 static int dwc_mmc_host_reset(sdmmc_chipset_handle_t);
50 static uint32_t dwc_mmc_host_ocr(sdmmc_chipset_handle_t);
51 static int dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t);
52 static int dwc_mmc_card_detect(sdmmc_chipset_handle_t);
53 static int dwc_mmc_write_protect(sdmmc_chipset_handle_t);
54 static int dwc_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t);
55 static int dwc_mmc_bus_clock(sdmmc_chipset_handle_t, int);
56 static int dwc_mmc_bus_width(sdmmc_chipset_handle_t, int);
57 static int dwc_mmc_bus_rod(sdmmc_chipset_handle_t, int);
58 static int dwc_mmc_signal_voltage(sdmmc_chipset_handle_t, int);
59 static void dwc_mmc_exec_command(sdmmc_chipset_handle_t,
60 struct sdmmc_command *);
61 static void dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t, int);
62 static void dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t);
63
64 static struct sdmmc_chip_functions dwc_mmc_chip_functions = {
65 .host_reset = dwc_mmc_host_reset,
66 .host_ocr = dwc_mmc_host_ocr,
67 .host_maxblklen = dwc_mmc_host_maxblklen,
68 .card_detect = dwc_mmc_card_detect,
69 .write_protect = dwc_mmc_write_protect,
70 .bus_power = dwc_mmc_bus_power,
71 .bus_clock = dwc_mmc_bus_clock,
72 .bus_width = dwc_mmc_bus_width,
73 .bus_rod = dwc_mmc_bus_rod,
74 .signal_voltage = dwc_mmc_signal_voltage,
75 .exec_command = dwc_mmc_exec_command,
76 .card_enable_intr = dwc_mmc_card_enable_intr,
77 .card_intr_ack = dwc_mmc_card_intr_ack,
78 };
79
80 #define MMC_WRITE(sc, reg, val) \
81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
82 #define MMC_READ(sc, reg) \
83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
84
85 static int
dwc_mmc_dmabounce_setup(struct dwc_mmc_softc * sc)86 dwc_mmc_dmabounce_setup(struct dwc_mmc_softc *sc)
87 {
88 bus_dma_segment_t ds[1];
89 int error, rseg;
90
91 sc->sc_dmabounce_buflen = dwc_mmc_host_maxblklen(sc);
92 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0,
93 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK);
94 if (error)
95 return error;
96 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen,
97 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK);
98 if (error)
99 goto free;
100 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1,
101 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map);
102 if (error)
103 goto unmap;
104 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map,
105 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL,
106 BUS_DMA_WAITOK);
107 if (error)
108 goto destroy;
109 return 0;
110
111 destroy:
112 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map);
113 unmap:
114 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf,
115 sc->sc_dmabounce_buflen);
116 free:
117 bus_dmamem_free(sc->sc_dmat, ds, rseg);
118 return error;
119 }
120
121 static int
dwc_mmc_idma_setup(struct dwc_mmc_softc * sc)122 dwc_mmc_idma_setup(struct dwc_mmc_softc *sc)
123 {
124 int error;
125
126 sc->sc_idma_xferlen = 0x1000;
127
128 sc->sc_idma_ndesc = DWC_MMC_NDESC;
129 sc->sc_idma_size = sizeof(struct dwc_mmc_idma_desc) *
130 sc->sc_idma_ndesc;
131 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 8,
132 sc->sc_idma_size, sc->sc_idma_segs, 1,
133 &sc->sc_idma_nsegs, BUS_DMA_WAITOK);
134 if (error)
135 return error;
136 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs,
137 sc->sc_idma_nsegs, sc->sc_idma_size,
138 &sc->sc_idma_desc, BUS_DMA_WAITOK);
139 if (error)
140 goto free;
141 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1,
142 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map);
143 if (error)
144 goto unmap;
145 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map,
146 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK);
147 if (error)
148 goto destroy;
149 return 0;
150
151 destroy:
152 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map);
153 unmap:
154 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size);
155 free:
156 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs);
157 return error;
158 }
159
160 static void
dwc_mmc_attach_i(device_t self)161 dwc_mmc_attach_i(device_t self)
162 {
163 struct dwc_mmc_softc *sc = device_private(self);
164 struct sdmmcbus_attach_args saa;
165 bool poll_detect;
166
167 poll_detect = sc->sc_card_detect != NULL ||
168 (sc->sc_flags & (DWC_MMC_F_BROKEN_CD|DWC_MMC_F_NON_REMOVABLE)) == 0;
169
170 if (sc->sc_pre_power_on)
171 sc->sc_pre_power_on(sc);
172
173 dwc_mmc_signal_voltage(sc, SDMMC_SIGNAL_VOLTAGE_330);
174 dwc_mmc_host_reset(sc);
175 dwc_mmc_bus_width(sc, 1);
176
177 if (sc->sc_post_power_on)
178 sc->sc_post_power_on(sc);
179
180 memset(&saa, 0, sizeof(saa));
181 saa.saa_busname = "sdmmc";
182 saa.saa_sct = &dwc_mmc_chip_functions;
183 saa.saa_sch = sc;
184 saa.saa_clkmin = 400;
185 saa.saa_clkmax = sc->sc_clock_freq / 1000;
186 saa.saa_dmat = sc->sc_dmat;
187 saa.saa_caps = SMC_CAPS_SD_HIGHSPEED |
188 SMC_CAPS_MMC_HIGHSPEED |
189 SMC_CAPS_AUTO_STOP |
190 SMC_CAPS_DMA |
191 SMC_CAPS_MULTI_SEG_DMA;
192 if (sc->sc_bus_width == 8) {
193 saa.saa_caps |= SMC_CAPS_8BIT_MODE;
194 } else {
195 saa.saa_caps |= SMC_CAPS_4BIT_MODE;
196 }
197
198 if (poll_detect) {
199 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET;
200 }
201
202 sc->sc_sdmmc_dev = config_found(self, &saa, NULL, CFARGS_NONE);
203 }
204
205 static void
dwc_mmc_led(struct dwc_mmc_softc * sc,int on)206 dwc_mmc_led(struct dwc_mmc_softc *sc, int on)
207 {
208 if (sc->sc_set_led)
209 sc->sc_set_led(sc, on);
210 }
211
212 static int
dwc_mmc_host_reset(sdmmc_chipset_handle_t sch)213 dwc_mmc_host_reset(sdmmc_chipset_handle_t sch)
214 {
215 struct dwc_mmc_softc *sc = sch;
216 uint32_t fifoth, ctrl;
217 int retry = 1000;
218
219 #ifdef DWC_MMC_DEBUG
220 aprint_normal_dev(sc->sc_dev, "host reset\n");
221 #endif
222
223 if (ISSET(sc->sc_flags, DWC_MMC_F_PWREN_INV))
224 MMC_WRITE(sc, DWC_MMC_PWREN, 0);
225 else
226 MMC_WRITE(sc, DWC_MMC_PWREN, 1);
227
228 ctrl = MMC_READ(sc, DWC_MMC_GCTRL);
229 ctrl &= ~DWC_MMC_GCTRL_USE_INTERNAL_DMAC;
230 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl);
231
232 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET);
233
234 MMC_WRITE(sc, DWC_MMC_GCTRL,
235 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_RESET);
236 while (--retry > 0) {
237 if (!(MMC_READ(sc, DWC_MMC_GCTRL) & DWC_MMC_GCTRL_RESET))
238 break;
239 delay(100);
240 }
241
242 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0);
243
244 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff);
245
246 MMC_WRITE(sc, DWC_MMC_IMASK, 0);
247
248 MMC_WRITE(sc, DWC_MMC_RINT, 0xffffffff);
249
250 const uint32_t rx_wmark = (sc->sc_fifo_depth / 2) - 1;
251 const uint32_t tx_wmark = sc->sc_fifo_depth / 2;
252 fifoth = __SHIFTIN(DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE_16,
253 DWC_MMC_FIFOTH_DMA_MULTIPLE_TXN_SIZE);
254 fifoth |= __SHIFTIN(rx_wmark, DWC_MMC_FIFOTH_RX_WMARK);
255 fifoth |= __SHIFTIN(tx_wmark, DWC_MMC_FIFOTH_TX_WMARK);
256 MMC_WRITE(sc, DWC_MMC_FIFOTH, fifoth);
257
258 MMC_WRITE(sc, DWC_MMC_UHS, 0);
259
260 ctrl = MMC_READ(sc, DWC_MMC_GCTRL);
261 ctrl |= DWC_MMC_GCTRL_INTEN;
262 ctrl |= DWC_MMC_GCTRL_DMAEN;
263 ctrl |= DWC_MMC_GCTRL_SEND_AUTO_STOP_CCSD;
264 ctrl |= DWC_MMC_GCTRL_USE_INTERNAL_DMAC;
265 MMC_WRITE(sc, DWC_MMC_GCTRL, ctrl);
266
267 return 0;
268 }
269
270 static uint32_t
dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch)271 dwc_mmc_host_ocr(sdmmc_chipset_handle_t sch)
272 {
273 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS;
274 }
275
276 static int
dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch)277 dwc_mmc_host_maxblklen(sdmmc_chipset_handle_t sch)
278 {
279 return 32768;
280 }
281
282 static int
dwc_mmc_card_detect(sdmmc_chipset_handle_t sch)283 dwc_mmc_card_detect(sdmmc_chipset_handle_t sch)
284 {
285 struct dwc_mmc_softc *sc = sch;
286 int det_n;
287
288 if (sc->sc_card_detect != NULL) {
289 return sc->sc_card_detect(sc);
290 }
291 if ((sc->sc_flags & DWC_MMC_F_BROKEN_CD) != 0) {
292 return 1; /* broken card detect, assume present */
293 }
294 if ((sc->sc_flags & DWC_MMC_F_NON_REMOVABLE) != 0) {
295 return 1; /* non-removable device is always present */
296 }
297
298 det_n = MMC_READ(sc, DWC_MMC_CDETECT) & DWC_MMC_CDETECT_CARD_DETECT_N;
299
300 return !det_n;
301 }
302
303 static int
dwc_mmc_write_protect(sdmmc_chipset_handle_t sch)304 dwc_mmc_write_protect(sdmmc_chipset_handle_t sch)
305 {
306 struct dwc_mmc_softc *sc = sch;
307
308 if (!sc->sc_write_protect)
309 return 0; /* no write protect pin, assume rw */
310
311 return sc->sc_write_protect(sc);
312 }
313
314 static int
dwc_mmc_bus_power(sdmmc_chipset_handle_t sch,uint32_t ocr)315 dwc_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
316 {
317 struct dwc_mmc_softc *sc = sch;
318
319 if (ocr == 0)
320 sc->sc_card_inited = false;
321
322 return 0;
323 }
324
325 static int
dwc_mmc_signal_voltage(sdmmc_chipset_handle_t sch,int signal_voltage)326 dwc_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage)
327 {
328 struct dwc_mmc_softc *sc = sch;
329
330 if (sc->sc_signal_voltage == NULL)
331 return 0;
332
333 return sc->sc_signal_voltage(sc, signal_voltage);
334 }
335
336 static int
dwc_mmc_update_clock(struct dwc_mmc_softc * sc)337 dwc_mmc_update_clock(struct dwc_mmc_softc *sc)
338 {
339 uint32_t cmd;
340 int retry;
341
342 #ifdef DWC_MMC_DEBUG
343 aprint_normal_dev(sc->sc_dev, "update clock\n");
344 #endif
345
346 cmd = DWC_MMC_CMD_START |
347 DWC_MMC_CMD_UPCLK_ONLY |
348 DWC_MMC_CMD_WAIT_PRE_OVER;
349 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG))
350 cmd |= DWC_MMC_CMD_USE_HOLD_REG;
351 MMC_WRITE(sc, DWC_MMC_ARG, 0);
352 MMC_WRITE(sc, DWC_MMC_CMD, cmd);
353 retry = 200000;
354 while (--retry > 0) {
355 if (!(MMC_READ(sc, DWC_MMC_CMD) & DWC_MMC_CMD_START))
356 break;
357 delay(10);
358 }
359
360 if (retry == 0) {
361 aprint_error_dev(sc->sc_dev, "timeout updating clock\n");
362 #ifdef DWC_MMC_DEBUG
363 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n",
364 MMC_READ(sc, DWC_MMC_GCTRL));
365 device_printf(sc->sc_dev, "CLKENA: 0x%08x\n",
366 MMC_READ(sc, DWC_MMC_CLKENA));
367 device_printf(sc->sc_dev, "CLKDIV: 0x%08x\n",
368 MMC_READ(sc, DWC_MMC_CLKDIV));
369 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n",
370 MMC_READ(sc, DWC_MMC_TIMEOUT));
371 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n",
372 MMC_READ(sc, DWC_MMC_WIDTH));
373 device_printf(sc->sc_dev, "CMD: 0x%08x\n",
374 MMC_READ(sc, DWC_MMC_CMD));
375 device_printf(sc->sc_dev, "MINT: 0x%08x\n",
376 MMC_READ(sc, DWC_MMC_MINT));
377 device_printf(sc->sc_dev, "RINT: 0x%08x\n",
378 MMC_READ(sc, DWC_MMC_RINT));
379 device_printf(sc->sc_dev, "STATUS: 0x%08x\n",
380 MMC_READ(sc, DWC_MMC_STATUS));
381 #endif
382 return ETIMEDOUT;
383 }
384
385 return 0;
386 }
387
388 static int
dwc_mmc_set_clock(struct dwc_mmc_softc * sc,u_int freq)389 dwc_mmc_set_clock(struct dwc_mmc_softc *sc, u_int freq)
390 {
391 const u_int pll_freq = sc->sc_clock_freq / 1000;
392 u_int clk_div, ciu_div;
393
394 ciu_div = sc->sc_ciu_div > 0 ? sc->sc_ciu_div : 1;
395
396 if (freq != pll_freq)
397 clk_div = howmany(pll_freq, freq * ciu_div);
398 else
399 clk_div = 0;
400
401 MMC_WRITE(sc, DWC_MMC_CLKDIV, clk_div);
402
403 return dwc_mmc_update_clock(sc);
404 }
405
406 static int
dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch,int freq)407 dwc_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
408 {
409 struct dwc_mmc_softc *sc = sch;
410 uint32_t clkena;
411
412 MMC_WRITE(sc, DWC_MMC_CLKSRC, 0);
413 MMC_WRITE(sc, DWC_MMC_CLKENA, 0);
414 if (dwc_mmc_update_clock(sc) != 0)
415 return 1;
416
417 if (freq) {
418 if (sc->sc_bus_clock && sc->sc_bus_clock(sc, freq) != 0)
419 return 1;
420
421 if (dwc_mmc_set_clock(sc, freq) != 0)
422 return 1;
423
424 clkena = DWC_MMC_CLKENA_CARDCLKON;
425 MMC_WRITE(sc, DWC_MMC_CLKENA, clkena);
426 if (dwc_mmc_update_clock(sc) != 0)
427 return 1;
428 }
429
430 delay(1000);
431
432 return 0;
433 }
434
435 static int
dwc_mmc_bus_width(sdmmc_chipset_handle_t sch,int width)436 dwc_mmc_bus_width(sdmmc_chipset_handle_t sch, int width)
437 {
438 struct dwc_mmc_softc *sc = sch;
439
440 #ifdef DWC_MMC_DEBUG
441 aprint_normal_dev(sc->sc_dev, "width = %d\n", width);
442 #endif
443
444 switch (width) {
445 case 1:
446 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_1);
447 break;
448 case 4:
449 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_4);
450 break;
451 case 8:
452 MMC_WRITE(sc, DWC_MMC_WIDTH, DWC_MMC_WIDTH_8);
453 break;
454 default:
455 return 1;
456 }
457
458 sc->sc_mmc_width = width;
459
460 return 0;
461 }
462
463 static int
dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch,int on)464 dwc_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on)
465 {
466 return -1;
467 }
468
469 static int
dwc_mmc_dma_prepare(struct dwc_mmc_softc * sc,struct sdmmc_command * cmd)470 dwc_mmc_dma_prepare(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd)
471 {
472 struct dwc_mmc_idma_desc *dma = sc->sc_idma_desc;
473 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr;
474 bus_dmamap_t map;
475 bus_size_t off;
476 int desc, resid, seg;
477 uint32_t val;
478
479 /*
480 * If the command includes a dma map use it, otherwise we need to
481 * bounce. This can happen for SDIO IO_RW_EXTENDED (CMD53) commands.
482 */
483 if (cmd->c_dmamap) {
484 map = cmd->c_dmamap;
485 } else {
486 if (cmd->c_datalen > sc->sc_dmabounce_buflen)
487 return E2BIG;
488 map = sc->sc_dmabounce_map;
489
490 if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
491 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen);
492 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map,
493 0, cmd->c_datalen, BUS_DMASYNC_PREREAD);
494 } else {
495 memcpy(sc->sc_dmabounce_buf, cmd->c_data,
496 cmd->c_datalen);
497 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map,
498 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE);
499 }
500 }
501
502 desc = 0;
503 for (seg = 0; seg < map->dm_nsegs; seg++) {
504 bus_addr_t paddr = map->dm_segs[seg].ds_addr;
505 bus_size_t len = map->dm_segs[seg].ds_len;
506 resid = uimin(len, cmd->c_resid);
507 off = 0;
508 while (resid > 0) {
509 if (desc == sc->sc_idma_ndesc)
510 break;
511 len = uimin(sc->sc_idma_xferlen, resid);
512 dma[desc].dma_buf_size = htole32(len);
513 dma[desc].dma_buf_addr = htole32(paddr + off);
514 dma[desc].dma_config = htole32(
515 DWC_MMC_IDMA_CONFIG_CH |
516 DWC_MMC_IDMA_CONFIG_OWN);
517 cmd->c_resid -= len;
518 resid -= len;
519 off += len;
520 if (desc == 0) {
521 dma[desc].dma_config |= htole32(
522 DWC_MMC_IDMA_CONFIG_FD);
523 }
524 if (cmd->c_resid == 0) {
525 dma[desc].dma_config |= htole32(
526 DWC_MMC_IDMA_CONFIG_LD);
527 dma[desc].dma_config |= htole32(
528 DWC_MMC_IDMA_CONFIG_ER);
529 dma[desc].dma_next = 0;
530 } else {
531 dma[desc].dma_config |=
532 htole32(DWC_MMC_IDMA_CONFIG_DIC);
533 dma[desc].dma_next = htole32(
534 desc_paddr + ((desc+1) *
535 sizeof(struct dwc_mmc_idma_desc)));
536 }
537 ++desc;
538 }
539 }
540 if (desc == sc->sc_idma_ndesc) {
541 aprint_error_dev(sc->sc_dev,
542 "not enough descriptors for %d byte transfer!\n",
543 cmd->c_datalen);
544 return EIO;
545 }
546
547 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0,
548 sc->sc_idma_size, BUS_DMASYNC_PREWRITE);
549
550 MMC_WRITE(sc, DWC_MMC_DLBA, desc_paddr);
551
552 val = MMC_READ(sc, DWC_MMC_GCTRL);
553 val |= DWC_MMC_GCTRL_DMAEN;
554 MMC_WRITE(sc, DWC_MMC_GCTRL, val);
555 val |= DWC_MMC_GCTRL_DMARESET;
556 MMC_WRITE(sc, DWC_MMC_GCTRL, val);
557
558 if (cmd->c_flags & SCF_CMD_READ)
559 val = DWC_MMC_IDST_RECEIVE_INT;
560 else
561 val = 0;
562 MMC_WRITE(sc, DWC_MMC_IDIE, val);
563 MMC_WRITE(sc, DWC_MMC_DMAC,
564 DWC_MMC_DMAC_IDMA_ON|DWC_MMC_DMAC_FIX_BURST);
565
566 return 0;
567 }
568
569 static void
dwc_mmc_dma_complete(struct dwc_mmc_softc * sc,struct sdmmc_command * cmd)570 dwc_mmc_dma_complete(struct dwc_mmc_softc *sc, struct sdmmc_command *cmd)
571 {
572 MMC_WRITE(sc, DWC_MMC_DMAC, 0);
573 MMC_WRITE(sc, DWC_MMC_IDIE, 0);
574
575 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0,
576 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE);
577
578 if (cmd->c_dmamap == NULL) {
579 if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
580 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map,
581 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD);
582 memcpy(cmd->c_data, sc->sc_dmabounce_buf,
583 cmd->c_datalen);
584 } else {
585 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map,
586 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE);
587 }
588 }
589 }
590
591 static void
dwc_mmc_exec_command(sdmmc_chipset_handle_t sch,struct sdmmc_command * cmd)592 dwc_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
593 {
594 struct dwc_mmc_softc *sc = sch;
595 uint32_t cmdval = DWC_MMC_CMD_START;
596 int retry, error;
597 uint32_t imask;
598 u_int reg;
599
600 #ifdef DWC_MMC_DEBUG
601 aprint_normal_dev(sc->sc_dev,
602 "opcode %d flags 0x%x data %p datalen %d blklen %d\n",
603 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen,
604 cmd->c_blklen);
605 #endif
606
607 mutex_enter(&sc->sc_lock);
608 if (sc->sc_curcmd != NULL) {
609 device_printf(sc->sc_dev,
610 "WARNING: driver submitted a command while the controller was busy\n");
611 cmd->c_error = EBUSY;
612 SET(cmd->c_flags, SCF_ITSDONE);
613 mutex_exit(&sc->sc_lock);
614 return;
615 }
616 sc->sc_curcmd = cmd;
617
618 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff);
619
620 if (!sc->sc_card_inited) {
621 cmdval |= DWC_MMC_CMD_SEND_INIT_SEQ;
622 sc->sc_card_inited = true;
623 }
624
625 if (ISSET(sc->sc_flags, DWC_MMC_F_USE_HOLD_REG))
626 cmdval |= DWC_MMC_CMD_USE_HOLD_REG;
627
628 switch (cmd->c_opcode) {
629 case SD_IO_RW_DIRECT:
630 reg = (cmd->c_arg >> SD_ARG_CMD52_REG_SHIFT) &
631 SD_ARG_CMD52_REG_MASK;
632 if (reg != 0x6) /* func abort / card reset */
633 break;
634 /* FALLTHROUGH */
635 case MMC_GO_IDLE_STATE:
636 case MMC_STOP_TRANSMISSION:
637 case MMC_INACTIVE_STATE:
638 cmdval |= DWC_MMC_CMD_STOP_ABORT_CMD;
639 break;
640 }
641
642 if (cmd->c_flags & SCF_RSP_PRESENT)
643 cmdval |= DWC_MMC_CMD_RSP_EXP;
644 if (cmd->c_flags & SCF_RSP_136)
645 cmdval |= DWC_MMC_CMD_LONG_RSP;
646 if (cmd->c_flags & SCF_RSP_CRC)
647 cmdval |= DWC_MMC_CMD_CHECK_RSP_CRC;
648
649 imask = DWC_MMC_INT_ERROR | DWC_MMC_INT_CMD_DONE;
650
651 if (cmd->c_datalen > 0) {
652 unsigned int nblks;
653
654 MMC_WRITE(sc, DWC_MMC_GCTRL,
655 MMC_READ(sc, DWC_MMC_GCTRL) | DWC_MMC_GCTRL_FIFORESET);
656 for (retry = 0; retry < 100000; retry++) {
657 if (!(MMC_READ(sc, DWC_MMC_DMAC) & DWC_MMC_DMAC_SOFTRESET))
658 break;
659 delay(1);
660 }
661
662 cmdval |= DWC_MMC_CMD_DATA_EXP | DWC_MMC_CMD_WAIT_PRE_OVER;
663 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) {
664 cmdval |= DWC_MMC_CMD_WRITE;
665 }
666
667 nblks = cmd->c_datalen / cmd->c_blklen;
668 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0)
669 ++nblks;
670
671 if (nblks > 1 && cmd->c_opcode != SD_IO_RW_EXTENDED) {
672 cmdval |= DWC_MMC_CMD_SEND_AUTO_STOP;
673 imask |= DWC_MMC_INT_AUTO_CMD_DONE;
674 } else {
675 imask |= DWC_MMC_INT_DATA_OVER;
676 }
677
678 MMC_WRITE(sc, DWC_MMC_TIMEOUT, 0xffffffff);
679 MMC_WRITE(sc, DWC_MMC_BLKSZ, cmd->c_blklen);
680 MMC_WRITE(sc, DWC_MMC_BYTECNT,
681 nblks > 1 ? nblks * cmd->c_blklen : cmd->c_datalen);
682
683 #if 0
684 /*
685 * The following doesn't work on the 250a verid IP in Odroid-XU4.
686 *
687 * thrctl should only be used for UHS/HS200 and faster timings on
688 * >=240a
689 */
690
691 if (ISSET(cmd->c_flags, SCF_CMD_READ)) {
692 MMC_WRITE(sc, DWC_MMC_CARDTHRCTL,
693 __SHIFTIN(cmd->c_blklen, DWC_MMC_CARDTHRCTL_RDTHR) |
694 DWC_MMC_CARDTHRCTL_RDTHREN);
695 }
696 #endif
697 }
698
699 MMC_WRITE(sc, DWC_MMC_IMASK, imask | sc->sc_intr_card);
700 MMC_WRITE(sc, DWC_MMC_RINT, 0x7fff);
701
702 MMC_WRITE(sc, DWC_MMC_ARG, cmd->c_arg);
703
704 #ifdef DWC_MMC_DEBUG
705 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval);
706 #endif
707
708 cmd->c_resid = cmd->c_datalen;
709 if (cmd->c_datalen > 0) {
710 dwc_mmc_led(sc, 0);
711 cmd->c_error = dwc_mmc_dma_prepare(sc, cmd);
712 if (cmd->c_error != 0) {
713 SET(cmd->c_flags, SCF_ITSDONE);
714 goto done;
715 }
716 sc->sc_wait_dma = ISSET(cmd->c_flags, SCF_CMD_READ);
717 sc->sc_wait_data = true;
718 } else {
719 sc->sc_wait_dma = false;
720 sc->sc_wait_data = false;
721 }
722 sc->sc_wait_cmd = true;
723
724 if ((cmdval & DWC_MMC_CMD_WAIT_PRE_OVER) != 0) {
725 for (retry = 0; retry < 10000; retry++) {
726 if (!(MMC_READ(sc, DWC_MMC_STATUS) & DWC_MMC_STATUS_CARD_DATA_BUSY))
727 break;
728 delay(1);
729 }
730 }
731
732 mutex_enter(&sc->sc_intr_lock);
733
734 MMC_WRITE(sc, DWC_MMC_CMD, cmdval | cmd->c_opcode);
735
736 if (sc->sc_wait_dma)
737 MMC_WRITE(sc, DWC_MMC_PLDMND, 1);
738
739 struct bintime timeout = { .sec = 15, .frac = 0 };
740 const struct bintime epsilon = { .sec = 1, .frac = 0 };
741 while (!ISSET(cmd->c_flags, SCF_ITSDONE)) {
742 error = cv_timedwaitbt(&sc->sc_intr_cv,
743 &sc->sc_intr_lock, &timeout, &epsilon);
744 if (error != 0) {
745 cmd->c_error = error;
746 SET(cmd->c_flags, SCF_ITSDONE);
747 mutex_exit(&sc->sc_intr_lock);
748 goto done;
749 }
750 }
751
752 mutex_exit(&sc->sc_intr_lock);
753
754 if (cmd->c_error == 0 && cmd->c_datalen > 0)
755 dwc_mmc_dma_complete(sc, cmd);
756
757 if (cmd->c_datalen > 0)
758 dwc_mmc_led(sc, 1);
759
760 if (cmd->c_flags & SCF_RSP_PRESENT) {
761 if (cmd->c_flags & SCF_RSP_136) {
762 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0);
763 cmd->c_resp[1] = MMC_READ(sc, DWC_MMC_RESP1);
764 cmd->c_resp[2] = MMC_READ(sc, DWC_MMC_RESP2);
765 cmd->c_resp[3] = MMC_READ(sc, DWC_MMC_RESP3);
766 if (cmd->c_flags & SCF_RSP_CRC) {
767 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) |
768 (cmd->c_resp[1] << 24);
769 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) |
770 (cmd->c_resp[2] << 24);
771 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) |
772 (cmd->c_resp[3] << 24);
773 cmd->c_resp[3] = (cmd->c_resp[3] >> 8);
774 }
775 } else {
776 cmd->c_resp[0] = MMC_READ(sc, DWC_MMC_RESP0);
777 }
778 }
779
780 done:
781 KASSERT(ISSET(cmd->c_flags, SCF_ITSDONE));
782 MMC_WRITE(sc, DWC_MMC_IMASK, sc->sc_intr_card);
783 MMC_WRITE(sc, DWC_MMC_IDIE, 0);
784 MMC_WRITE(sc, DWC_MMC_RINT, 0x7fff);
785 MMC_WRITE(sc, DWC_MMC_IDST, 0xffffffff);
786
787 if (cmd->c_error) {
788 #ifdef DWC_MMC_DEBUG
789 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error);
790 #endif
791 MMC_WRITE(sc, DWC_MMC_DMAC, DWC_MMC_DMAC_SOFTRESET);
792 for (retry = 0; retry < 100; retry++) {
793 if (!(MMC_READ(sc, DWC_MMC_DMAC) & DWC_MMC_DMAC_SOFTRESET))
794 break;
795 kpause("dwcmmcrst", false, uimax(mstohz(1), 1), &sc->sc_lock);
796 }
797 }
798
799 sc->sc_curcmd = NULL;
800 mutex_exit(&sc->sc_lock);
801 }
802
803 static void
dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch,int enable)804 dwc_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
805 {
806 struct dwc_mmc_softc *sc = sch;
807 uint32_t imask;
808
809 mutex_enter(&sc->sc_intr_lock);
810 imask = MMC_READ(sc, DWC_MMC_IMASK);
811 if (enable)
812 imask |= sc->sc_intr_cardmask;
813 else
814 imask &= ~sc->sc_intr_cardmask;
815 sc->sc_intr_card = imask & sc->sc_intr_cardmask;
816 MMC_WRITE(sc, DWC_MMC_IMASK, imask);
817 mutex_exit(&sc->sc_intr_lock);
818 }
819
820 static void
dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch)821 dwc_mmc_card_intr_ack(sdmmc_chipset_handle_t sch)
822 {
823 struct dwc_mmc_softc *sc = sch;
824 uint32_t imask;
825
826 mutex_enter(&sc->sc_intr_lock);
827 imask = MMC_READ(sc, DWC_MMC_IMASK);
828 MMC_WRITE(sc, DWC_MMC_IMASK, imask | sc->sc_intr_card);
829 mutex_exit(&sc->sc_intr_lock);
830 }
831
832 int
dwc_mmc_init(struct dwc_mmc_softc * sc)833 dwc_mmc_init(struct dwc_mmc_softc *sc)
834 {
835 uint32_t val;
836
837 val = MMC_READ(sc, DWC_MMC_VERID);
838 sc->sc_verid = __SHIFTOUT(val, DWC_MMC_VERID_ID);
839
840 if (sizeof(bus_addr_t) > 4) {
841 int error = bus_dmatag_subregion(sc->sc_dmat, 0, __MASK(32),
842 &sc->sc_dmat, BUS_DMA_WAITOK);
843 if (error != 0) {
844 aprint_error_dev(sc->sc_dev,
845 "failed to create DMA subregion\n");
846 return ENOMEM;
847 }
848 }
849
850 if (sc->sc_fifo_reg == 0) {
851 if (sc->sc_verid < DWC_MMC_VERID_240A)
852 sc->sc_fifo_reg = 0x100;
853 else
854 sc->sc_fifo_reg = 0x200;
855 }
856
857 if (sc->sc_fifo_depth == 0) {
858 val = MMC_READ(sc, DWC_MMC_FIFOTH);
859 sc->sc_fifo_depth = __SHIFTOUT(val, DWC_MMC_FIFOTH_RX_WMARK) + 1;
860 }
861
862 if (sc->sc_intr_cardmask == 0)
863 sc->sc_intr_cardmask = DWC_MMC_INT_SDIO_INT(0);
864
865 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
866 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO);
867 cv_init(&sc->sc_intr_cv, "dwcmmcirq");
868
869 if (dwc_mmc_dmabounce_setup(sc) != 0 ||
870 dwc_mmc_idma_setup(sc) != 0) {
871 aprint_error_dev(sc->sc_dev, "failed to setup DMA\n");
872 return ENOMEM;
873 }
874
875 config_interrupts(sc->sc_dev, dwc_mmc_attach_i);
876
877 return 0;
878 }
879
880 int
dwc_mmc_intr(void * priv)881 dwc_mmc_intr(void *priv)
882 {
883 struct dwc_mmc_softc *sc = priv;
884 struct sdmmc_command *cmd;
885 uint32_t idst, mint, imask;
886
887 mutex_enter(&sc->sc_intr_lock);
888 idst = MMC_READ(sc, DWC_MMC_IDST);
889 mint = MMC_READ(sc, DWC_MMC_MINT);
890 if (!idst && !mint) {
891 mutex_exit(&sc->sc_intr_lock);
892 return 0;
893 }
894 MMC_WRITE(sc, DWC_MMC_IDST, idst);
895 MMC_WRITE(sc, DWC_MMC_RINT, mint);
896
897 cmd = sc->sc_curcmd;
898
899 #ifdef DWC_MMC_DEBUG
900 device_printf(sc->sc_dev, "mmc intr idst=%08X mint=%08X\n",
901 idst, mint);
902 #endif
903
904 /* Handle SDIO card interrupt */
905 if ((mint & sc->sc_intr_cardmask) != 0) {
906 imask = MMC_READ(sc, DWC_MMC_IMASK);
907 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~sc->sc_intr_cardmask);
908 sdmmc_card_intr(sc->sc_sdmmc_dev);
909 }
910
911 /* Error interrupts take priority over command and transfer interrupts */
912 if (cmd != NULL && (mint & DWC_MMC_INT_ERROR) != 0) {
913 imask = MMC_READ(sc, DWC_MMC_IMASK);
914 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_ERROR);
915 if ((mint & DWC_MMC_INT_RESP_TIMEOUT) != 0) {
916 cmd->c_error = ETIMEDOUT;
917 /* Wait for command to complete */
918 sc->sc_wait_data = sc->sc_wait_dma = false;
919 if (cmd->c_opcode != SD_IO_SEND_OP_COND &&
920 cmd->c_opcode != SD_IO_RW_DIRECT &&
921 !ISSET(cmd->c_flags, SCF_TOUT_OK))
922 device_printf(sc->sc_dev, "host controller timeout, mint=0x%08x\n", mint);
923 } else {
924 device_printf(sc->sc_dev, "host controller error, mint=0x%08x\n", mint);
925 cmd->c_error = EIO;
926 SET(cmd->c_flags, SCF_ITSDONE);
927 goto done;
928 }
929 }
930
931 if (cmd != NULL && (idst & DWC_MMC_IDST_RECEIVE_INT) != 0) {
932 MMC_WRITE(sc, DWC_MMC_IDIE, 0);
933 if (sc->sc_wait_dma == false)
934 device_printf(sc->sc_dev, "unexpected DMA receive interrupt\n");
935 sc->sc_wait_dma = false;
936 }
937
938 if (cmd != NULL && (mint & DWC_MMC_INT_CMD_DONE) != 0) {
939 imask = MMC_READ(sc, DWC_MMC_IMASK);
940 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~DWC_MMC_INT_CMD_DONE);
941 if (sc->sc_wait_cmd == false)
942 device_printf(sc->sc_dev, "unexpected command complete interrupt\n");
943 sc->sc_wait_cmd = false;
944 }
945
946 const uint32_t dmadone_mask = DWC_MMC_INT_AUTO_CMD_DONE|DWC_MMC_INT_DATA_OVER;
947 if (cmd != NULL && (mint & dmadone_mask) != 0) {
948 imask = MMC_READ(sc, DWC_MMC_IMASK);
949 MMC_WRITE(sc, DWC_MMC_IMASK, imask & ~dmadone_mask);
950 if (sc->sc_wait_data == false)
951 device_printf(sc->sc_dev, "unexpected data complete interrupt\n");
952 sc->sc_wait_data = false;
953 }
954
955 if (cmd != NULL &&
956 sc->sc_wait_dma == false &&
957 sc->sc_wait_cmd == false &&
958 sc->sc_wait_data == false) {
959 SET(cmd->c_flags, SCF_ITSDONE);
960 }
961
962 done:
963 if (cmd != NULL && ISSET(cmd->c_flags, SCF_ITSDONE)) {
964 cv_broadcast(&sc->sc_intr_cv);
965 }
966
967 mutex_exit(&sc->sc_intr_lock);
968
969 return 1;
970 }
971