1 /* $NetBSD: dm_services.h,v 1.3 2021/12/19 11:24:52 riastradh Exp $ */
2
3 /*
4 * Copyright 2015 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 /**
29 * This file defines external dependencies of Display Core.
30 */
31
32 #ifndef __DM_SERVICES_H__
33
34 #define __DM_SERVICES_H__
35
36 #include "amdgpu_dm_trace.h"
37
38 /* TODO: remove when DC is complete. */
39 #include "dm_services_types.h"
40 #include "logger_interface.h"
41 #include "link_service_types.h"
42
43 #undef DEPRECATED
44
45 struct dmub_srv;
46 struct dc_dmub_srv;
47
48 irq_handler_idx dm_register_interrupt(
49 struct dc_context *ctx,
50 struct dc_interrupt_params *int_params,
51 interrupt_handler ih,
52 void *handler_args);
53
54
55 /*
56 *
57 * GPU registers access
58 *
59 */
60 uint32_t dm_read_reg_func(
61 const struct dc_context *ctx,
62 uint32_t address,
63 const char *func_name);
64 /* enable for debugging new code, this adds 50k to the driver size. */
65 /* #define DM_CHECK_ADDR_0 */
66
67 #define dm_read_reg(ctx, address) \
68 dm_read_reg_func(ctx, address, __func__)
69
70
71
72 #define dm_write_reg(ctx, address, value) \
73 dm_write_reg_func(ctx, address, value, __func__)
74
dm_write_reg_func(const struct dc_context * ctx,uint32_t address,uint32_t value,const char * func_name)75 static inline void dm_write_reg_func(
76 const struct dc_context *ctx,
77 uint32_t address,
78 uint32_t value,
79 const char *func_name)
80 {
81 #ifdef DM_CHECK_ADDR_0
82 if (address == 0) {
83 DC_ERR("invalid register write. address = 0");
84 return;
85 }
86 #endif
87 cgs_write_register(ctx->cgs_device, address, value);
88 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
89 }
90
dm_read_index_reg(const struct dc_context * ctx,enum cgs_ind_reg addr_space,uint32_t index)91 static inline uint32_t dm_read_index_reg(
92 const struct dc_context *ctx,
93 enum cgs_ind_reg addr_space,
94 uint32_t index)
95 {
96 return cgs_read_ind_register(ctx->cgs_device, addr_space, index);
97 }
98
dm_write_index_reg(const struct dc_context * ctx,enum cgs_ind_reg addr_space,uint32_t index,uint32_t value)99 static inline void dm_write_index_reg(
100 const struct dc_context *ctx,
101 enum cgs_ind_reg addr_space,
102 uint32_t index,
103 uint32_t value)
104 {
105 cgs_write_ind_register(ctx->cgs_device, addr_space, index, value);
106 }
107
get_reg_field_value_ex(uint32_t reg_value,uint32_t mask,uint8_t shift)108 static inline uint32_t get_reg_field_value_ex(
109 uint32_t reg_value,
110 uint32_t mask,
111 uint8_t shift)
112 {
113 return (mask & reg_value) >> shift;
114 }
115
116 #define get_reg_field_value(reg_value, reg_name, reg_field)\
117 get_reg_field_value_ex(\
118 (reg_value),\
119 reg_name ## __ ## reg_field ## _MASK,\
120 reg_name ## __ ## reg_field ## __SHIFT)
121
set_reg_field_value_ex(uint32_t reg_value,uint32_t value,uint32_t mask,uint8_t shift)122 static inline uint32_t set_reg_field_value_ex(
123 uint32_t reg_value,
124 uint32_t value,
125 uint32_t mask,
126 uint8_t shift)
127 {
128 ASSERT(mask != 0);
129 return (reg_value & ~mask) | (mask & (value << shift));
130 }
131
132 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\
133 (reg_value) = set_reg_field_value_ex(\
134 (reg_value),\
135 (value),\
136 reg_name ## __ ## reg_field ## _MASK,\
137 reg_name ## __ ## reg_field ## __SHIFT)
138
139 uint32_t generic_reg_set_ex(const struct dc_context *ctx,
140 uint32_t addr, uint32_t reg_val, int n,
141 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
142
143 uint32_t generic_reg_update_ex(const struct dc_context *ctx,
144 uint32_t addr, int n,
145 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...);
146
147 struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);
148 void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);
149
150 void reg_sequence_start_gather(const struct dc_context *ctx);
151 void reg_sequence_start_execute(const struct dc_context *ctx);
152 void reg_sequence_wait_done(const struct dc_context *ctx);
153
154 #define FD(reg_field) reg_field ## __SHIFT, \
155 reg_field ## _MASK
156
157 /*
158 * return number of poll before condition is met
159 * return 0 if condition is not meet after specified time out tries
160 */
161 void generic_reg_wait(const struct dc_context *ctx,
162 uint32_t addr, uint32_t mask, uint32_t shift, uint32_t condition_value,
163 unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
164 const char *func_name, int line);
165
166 unsigned int __printflike(3,4) snprintf_count(char *pBuf, unsigned int bufSize, const char *fmt, ...);
167
168 /* These macros need to be used with soc15 registers in order to retrieve
169 * the actual offset.
170 */
171 #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \
172 dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__)
173
174 #define dm_read_reg_soc15(ctx, reg, inst_offset) \
175 dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__)
176
177 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\
178 generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \
179 n, __VA_ARGS__)
180
181 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\
182 generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \
183 n, __VA_ARGS__)
184
185 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
186 get_reg_field_value_ex(\
187 (reg_value),\
188 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
189 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
190
191 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
192 (reg_value) = set_reg_field_value_ex(\
193 (reg_value),\
194 (value),\
195 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
196 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
197
198 /**************************************
199 * Power Play (PP) interfaces
200 **************************************/
201
202 /* Gets valid clocks levels from pplib
203 *
204 * input: clk_type - display clk / sclk / mem clk
205 *
206 * output: array of valid clock levels for given type in ascending order,
207 * with invalid levels filtered out
208 *
209 */
210 bool dm_pp_get_clock_levels_by_type(
211 const struct dc_context *ctx,
212 enum dm_pp_clock_type clk_type,
213 struct dm_pp_clock_levels *clk_level_info);
214
215 bool dm_pp_get_clock_levels_by_type_with_latency(
216 const struct dc_context *ctx,
217 enum dm_pp_clock_type clk_type,
218 struct dm_pp_clock_levels_with_latency *clk_level_info);
219
220 bool dm_pp_get_clock_levels_by_type_with_voltage(
221 const struct dc_context *ctx,
222 enum dm_pp_clock_type clk_type,
223 struct dm_pp_clock_levels_with_voltage *clk_level_info);
224
225 bool dm_pp_notify_wm_clock_changes(
226 const struct dc_context *ctx,
227 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
228
229 void dm_pp_get_funcs(struct dc_context *ctx,
230 struct pp_smu_funcs *funcs);
231
232 /* DAL calls this function to notify PP about completion of Mode Set.
233 * For PP it means that current DCE clocks are those which were returned
234 * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter.
235 *
236 * If the clocks are higher than before, then PP does nothing.
237 *
238 * If the clocks are lower than before, then PP reduces the voltage.
239 *
240 * \returns true - call is successful
241 * false - call failed
242 */
243 bool dm_pp_apply_display_requirements(
244 const struct dc_context *ctx,
245 const struct dm_pp_display_configuration *pp_display_cfg);
246
247 bool dm_pp_apply_power_level_change_request(
248 const struct dc_context *ctx,
249 struct dm_pp_power_level_change_request *level_change_req);
250
251 bool dm_pp_apply_clock_for_voltage_request(
252 const struct dc_context *ctx,
253 struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
254
255 bool dm_pp_get_static_clocks(
256 const struct dc_context *ctx,
257 struct dm_pp_static_clock_info *static_clk_info);
258
259 /****** end of PP interfaces ******/
260
261 struct persistent_data_flag {
262 bool save_per_link;
263 bool save_per_edid;
264 };
265
266 /* Call to write data in registry editor for persistent data storage.
267 *
268 * \inputs sink - identify edid/link for registry folder creation
269 * module name - identify folders for registry
270 * key name - identify keys within folders for registry
271 * params - value to write in defined folder/key
272 * size - size of the input params
273 * flag - determine whether to save by link or edid
274 *
275 * \returns true - call is successful
276 * false - call failed
277 *
278 * sink module key
279 * -----------------------------------------------------------------------------
280 * NULL NULL NULL - failure
281 * NULL NULL - - create key with param value
282 * under base folder
283 * NULL - NULL - create module folder under base folder
284 * - NULL NULL - failure
285 * NULL - - - create key under module folder
286 * with no edid/link identification
287 * - NULL - - create key with param value
288 * under base folder
289 * - - NULL - create module folder under base folder
290 * - - - - create key under module folder
291 * with edid/link identification
292 */
293 bool dm_write_persistent_data(struct dc_context *ctx,
294 const struct dc_sink *sink,
295 const char *module_name,
296 const char *key_name,
297 void *params,
298 unsigned int size,
299 struct persistent_data_flag *flag);
300
301
302 /* Call to read data in registry editor for persistent data storage.
303 *
304 * \inputs sink - identify edid/link for registry folder creation
305 * module name - identify folders for registry
306 * key name - identify keys within folders for registry
307 * size - size of the output params
308 * flag - determine whether it was save by link or edid
309 *
310 * \returns params - value read from defined folder/key
311 * true - call is successful
312 * false - call failed
313 *
314 * sink module key
315 * -----------------------------------------------------------------------------
316 * NULL NULL NULL - failure
317 * NULL NULL - - read key under base folder
318 * NULL - NULL - failure
319 * - NULL NULL - failure
320 * NULL - - - read key under module folder
321 * with no edid/link identification
322 * - NULL - - read key under base folder
323 * - - NULL - failure
324 * - - - - read key under module folder
325 * with edid/link identification
326 */
327 bool dm_read_persistent_data(struct dc_context *ctx,
328 const struct dc_sink *sink,
329 const char *module_name,
330 const char *key_name,
331 void *params,
332 unsigned int size,
333 struct persistent_data_flag *flag);
334
335 bool dm_query_extended_brightness_caps
336 (struct dc_context *ctx, enum dm_acpi_display_type display,
337 struct dm_acpi_atif_backlight_caps *pCaps);
338
339 bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
340
341 /*
342 *
343 * print-out services
344 *
345 */
346 #define dm_log_to_buffer(buffer, size, fmt, args)\
347 vsnprintf(buffer, size, fmt, args)
348
dm_get_timestamp(struct dc_context * ctx)349 static inline unsigned long long dm_get_timestamp(struct dc_context *ctx)
350 {
351 return ktime_get_raw_ns();
352 }
353
354 unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
355 unsigned long long current_time_stamp,
356 unsigned long long last_time_stamp);
357
358 /*
359 * performance tracing
360 */
361 #define PERF_TRACE() trace_amdgpu_dc_performance(CTX->perf_trace->read_count,\
362 CTX->perf_trace->write_count, &CTX->perf_trace->last_entry_read,\
363 &CTX->perf_trace->last_entry_write, __func__, __LINE__)
364 #define PERF_TRACE_CTX(__CTX) trace_amdgpu_dc_performance(__CTX->perf_trace->read_count,\
365 __CTX->perf_trace->write_count, &__CTX->perf_trace->last_entry_read,\
366 &__CTX->perf_trace->last_entry_write, __func__, __LINE__)
367
368
369 /*
370 * Debug and verification hooks
371 */
372
373 void dm_dtn_log_begin(struct dc_context *ctx,
374 struct dc_log_buffer_ctx *log_ctx);
375 void dm_dtn_log_append_v(struct dc_context *ctx,
376 struct dc_log_buffer_ctx *log_ctx,
377 const char *msg, ...);
378 void dm_dtn_log_end(struct dc_context *ctx,
379 struct dc_log_buffer_ctx *log_ctx);
380
381 #endif /* __DM_SERVICES_H__ */
382