1 /* $NetBSD: agp_intel.c,v 1.39 2019/11/10 21:16:36 chs Exp $ */
2
3 /*-
4 * Copyright (c) 2000 Doug Rabson
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.4 2001/07/05 21:28:47 jhb Exp $
29 */
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: agp_intel.c,v 1.39 2019/11/10 21:16:36 chs Exp $");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/kernel.h>
38 #include <sys/proc.h>
39 #include <sys/agpio.h>
40 #include <sys/device.h>
41
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcidevs.h>
45 #include <dev/pci/agpvar.h>
46 #include <dev/pci/agpreg.h>
47
48 #include <sys/bus.h>
49
50 struct agp_intel_softc {
51 u_int32_t initial_aperture;
52 /* aperture size at startup */
53 struct agp_gatt *gatt;
54 struct pci_attach_args vga_pa;
55 u_int aperture_mask;
56 int chiptype; /* Chip type */
57 #define CHIP_INTEL 0x0
58 #define CHIP_I443 0x1
59 #define CHIP_I840 0x2
60 #define CHIP_I845 0x3
61 #define CHIP_I850 0x4
62 #define CHIP_I865 0x5
63
64 };
65
66 static u_int32_t agp_intel_get_aperture(struct agp_softc *);
67 static int agp_intel_set_aperture(struct agp_softc *, u_int32_t);
68 static int agp_intel_bind_page(struct agp_softc *, off_t, bus_addr_t);
69 static int agp_intel_unbind_page(struct agp_softc *, off_t);
70 static void agp_intel_flush_tlb(struct agp_softc *);
71 static int agp_intel_init(struct agp_softc *);
72 static bool agp_intel_resume(device_t, const pmf_qual_t *);
73
74 static struct agp_methods agp_intel_methods = {
75 agp_intel_get_aperture,
76 agp_intel_set_aperture,
77 agp_intel_bind_page,
78 agp_intel_unbind_page,
79 agp_intel_flush_tlb,
80 agp_generic_enable,
81 agp_generic_alloc_memory,
82 agp_generic_free_memory,
83 agp_generic_bind_memory,
84 agp_generic_unbind_memory,
85 };
86
87 static int
agp_intel_vgamatch(const struct pci_attach_args * pa)88 agp_intel_vgamatch(const struct pci_attach_args *pa)
89 {
90 switch (PCI_PRODUCT(pa->pa_id)) {
91 case PCI_PRODUCT_INTEL_82855GM_AGP:
92 case PCI_PRODUCT_INTEL_82855PM_AGP:
93 case PCI_PRODUCT_INTEL_82443LX_AGP:
94 case PCI_PRODUCT_INTEL_82443BX_AGP:
95 case PCI_PRODUCT_INTEL_82443GX_AGP:
96 case PCI_PRODUCT_INTEL_82850_AGP: /* i850/i860 */
97 case PCI_PRODUCT_INTEL_82845_AGP:
98 case PCI_PRODUCT_INTEL_82840_AGP:
99 case PCI_PRODUCT_INTEL_82865_AGP:
100 case PCI_PRODUCT_INTEL_82875P_AGP:
101 return (1);
102 }
103
104 return (0);
105 }
106
107 int
agp_intel_attach(device_t parent,device_t self,void * aux)108 agp_intel_attach(device_t parent, device_t self, void *aux)
109 {
110 struct agp_softc *sc = device_private(self);
111 struct pci_attach_args *pa = aux;
112 struct agp_intel_softc *isc;
113 struct agp_gatt *gatt;
114 u_int32_t value;
115
116 isc = malloc(sizeof *isc, M_AGP, M_WAITOK|M_ZERO);
117 sc->as_methods = &agp_intel_methods;
118 sc->as_chipc = isc;
119
120 if (pci_find_device(&isc->vga_pa, agp_intel_vgamatch) == 0) {
121 aprint_normal(": using generic initialization for Intel AGP\n");
122 aprint_normal_dev(sc->as_dev, "");
123 isc->chiptype = CHIP_INTEL;
124 }
125
126 pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
127 NULL);
128
129 if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) {
130 aprint_error(": can't map aperture\n");
131 free(isc, M_AGP);
132 sc->as_chipc = NULL;
133 return ENXIO;
134 }
135
136 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) {
137 case PCI_PRODUCT_INTEL_82443LX_AGP:
138 case PCI_PRODUCT_INTEL_82443BX_AGP:
139 case PCI_PRODUCT_INTEL_82443GX_AGP:
140 isc->chiptype = CHIP_I443;
141 break;
142 case PCI_PRODUCT_INTEL_82840_AGP:
143 isc->chiptype = CHIP_I840;
144 break;
145 case PCI_PRODUCT_INTEL_82855GM_AGP:
146 case PCI_PRODUCT_INTEL_82855PM_AGP:
147 case PCI_PRODUCT_INTEL_82845_AGP:
148 isc->chiptype = CHIP_I845;
149 break;
150 case PCI_PRODUCT_INTEL_82850_AGP:
151 isc->chiptype = CHIP_I850;
152 break;
153 case PCI_PRODUCT_INTEL_82865_AGP:
154 case PCI_PRODUCT_INTEL_82875P_AGP:
155 isc->chiptype = CHIP_I865;
156 break;
157 }
158
159 /* Determine maximum supported aperture size. */
160 value = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE);
161 pci_conf_write(sc->as_pc, sc->as_tag,
162 AGP_INTEL_APSIZE, APSIZE_MASK);
163 isc->aperture_mask = pci_conf_read(sc->as_pc, sc->as_tag,
164 AGP_INTEL_APSIZE) & APSIZE_MASK;
165 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_APSIZE, value);
166 isc->initial_aperture = AGP_GET_APERTURE(sc);
167
168 for (;;) {
169 gatt = agp_alloc_gatt(sc);
170 if (gatt)
171 break;
172
173 /*
174 * Probably contigmalloc failure. Try reducing the
175 * aperture so that the gatt size reduces.
176 */
177 if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
178 agp_generic_detach(sc);
179 aprint_error(": failed to set aperture\n");
180 return ENOMEM;
181 }
182 }
183 isc->gatt = gatt;
184
185 if (!pmf_device_register(self, NULL, agp_intel_resume))
186 aprint_error_dev(self, "couldn't establish power handler\n");
187
188 return agp_intel_init(sc);
189 }
190
191 static int
agp_intel_init(struct agp_softc * sc)192 agp_intel_init(struct agp_softc *sc)
193 {
194 struct agp_intel_softc *isc = sc->as_chipc;
195 struct agp_gatt *gatt = isc->gatt;
196 pcireg_t reg;
197
198 /* Install the gatt. */
199 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE,
200 gatt->ag_physical);
201
202 /* Enable the GLTB and setup the control register. */
203 switch (isc->chiptype) {
204 case CHIP_I443:
205 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
206 AGPCTRL_AGPRSE | AGPCTRL_GTLB);
207 break;
208
209 default:
210 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
211 pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL)
212 | AGPCTRL_GTLB);
213 }
214
215 /* Enable things, clear errors etc. */
216 switch (isc->chiptype) {
217 case CHIP_I845:
218 case CHIP_I865:
219 {
220 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG);
221 reg |= MCHCFG_AAGN;
222 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG, reg);
223 break;
224 }
225 case CHIP_I840:
226 case CHIP_I850:
227 {
228 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD);
229 reg |= AGPCMD_AGPEN;
230 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCMD,
231 reg);
232 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG);
233 reg |= MCHCFG_AAGN;
234 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I840_MCHCFG,
235 reg);
236 break;
237 }
238 default:
239 {
240 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG);
241 reg &= ~NBXCFG_APAE;
242 reg |= NBXCFG_AAGN;
243 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg);
244 }
245 }
246
247 /* Clear Error status */
248 switch (isc->chiptype) {
249 case CHIP_I840:
250 pci_conf_write(sc->as_pc, sc->as_tag,
251 AGP_INTEL_I8XX_ERRSTS, 0xc000);
252 break;
253
254 case CHIP_I845:
255 case CHIP_I850:
256 case CHIP_I865:
257 pci_conf_write(sc->as_pc, sc->as_tag,
258 AGP_INTEL_I8XX_ERRSTS, 0x00ff);
259 break;
260
261 default:
262 {
263 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_ERRSTS);
264 /* clear error bits (write-one-to-clear) - just write back */
265 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ERRSTS, reg);
266 }
267 }
268
269 return (0);
270 }
271
272 #if 0
273 static int
274 agp_intel_detach(struct agp_softc *sc)
275 {
276 int error;
277 pcireg_t reg;
278 struct agp_intel_softc *isc = sc->as_chipc;
279
280 error = agp_generic_detach(sc);
281 if (error)
282 return error;
283
284 /* XXX i845/i855PM/i840/i850E */
285 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG);
286 reg &= ~(1 << 9);
287 printf("%s: set NBXCFG to %x\n", __func__, reg);
288 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_NBXCFG, reg);
289 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_ATTBASE, 0);
290 AGP_SET_APERTURE(sc, isc->initial_aperture);
291 agp_free_gatt(sc, isc->gatt);
292
293 return 0;
294 }
295 #endif
296
297 static u_int32_t
agp_intel_get_aperture(struct agp_softc * sc)298 agp_intel_get_aperture(struct agp_softc *sc)
299 {
300 struct agp_intel_softc *isc = sc->as_chipc;
301 u_int32_t apsize;
302
303 apsize = pci_conf_read(sc->as_pc, sc->as_tag,
304 AGP_INTEL_APSIZE) & isc->aperture_mask;
305
306 /*
307 * The size is determined by the number of low bits of
308 * register APBASE which are forced to zero. The low 22 bits
309 * are always forced to zero and each zero bit in the apsize
310 * field just read forces the corresponding bit in the 27:22
311 * to be zero. We calculate the aperture size accordingly.
312 */
313 return (((apsize ^ isc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
314 }
315
316 static int
agp_intel_set_aperture(struct agp_softc * sc,u_int32_t aperture)317 agp_intel_set_aperture(struct agp_softc *sc, u_int32_t aperture)
318 {
319 struct agp_intel_softc *isc = sc->as_chipc;
320 u_int32_t apsize;
321
322 /*
323 * Reverse the magic from get_aperture.
324 */
325 apsize = ((aperture - 1) >> 22) ^ isc->aperture_mask;
326
327 /*
328 * Double check for sanity.
329 */
330 if ((((apsize ^ isc->aperture_mask) << 22) |
331 ((1 << 22) - 1)) + 1 != aperture)
332 return EINVAL;
333
334 pci_conf_write(sc->as_pc, sc->as_tag,
335 AGP_INTEL_APSIZE, apsize);
336
337 return 0;
338 }
339
340 static int
agp_intel_bind_page(struct agp_softc * sc,off_t offset,bus_addr_t physical)341 agp_intel_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
342 {
343 struct agp_intel_softc *isc = sc->as_chipc;
344
345 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT))
346 return EINVAL;
347
348 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
349 return 0;
350 }
351
352 static int
agp_intel_unbind_page(struct agp_softc * sc,off_t offset)353 agp_intel_unbind_page(struct agp_softc *sc, off_t offset)
354 {
355 struct agp_intel_softc *isc = sc->as_chipc;
356
357 if (offset < 0 || offset >= (isc->gatt->ag_entries << AGP_PAGE_SHIFT))
358 return EINVAL;
359
360 isc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
361 return 0;
362 }
363
364 static void
agp_intel_flush_tlb(struct agp_softc * sc)365 agp_intel_flush_tlb(struct agp_softc *sc)
366 {
367 struct agp_intel_softc *isc = sc->as_chipc;
368 pcireg_t reg;
369
370 switch (isc->chiptype) {
371 case CHIP_I865:
372 case CHIP_I850:
373 case CHIP_I845:
374 case CHIP_I840:
375 case CHIP_I443:
376 {
377 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL);
378 reg &= ~AGPCTRL_GTLB;
379 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
380 reg);
381 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
382 reg | AGPCTRL_GTLB);
383 break;
384 }
385 default: /* XXX */
386 {
387 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
388 0x2200);
389 pci_conf_write(sc->as_pc, sc->as_tag, AGP_INTEL_AGPCTRL,
390 0x2280);
391 }
392 }
393 }
394
395 static bool
agp_intel_resume(device_t dv,const pmf_qual_t * qual)396 agp_intel_resume(device_t dv, const pmf_qual_t *qual)
397 {
398 struct agp_softc *sc = device_private(dv);
399
400 agp_intel_init(sc);
401 agp_flush_cache();
402
403 return true;
404 }
405