1 /* $NetBSD: pl061.c,v 1.4 2021/08/07 16:19:12 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2018 Jonathan A. Kollasch
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: pl061.c,v 1.4 2021/08/07 16:19:12 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/kmem.h>
39 #include <sys/gpio.h>
40
41 #include <dev/gpio/gpiovar.h>
42 #include "gpio.h"
43
44 #include <dev/ic/pl061reg.h>
45 #include <dev/ic/pl061var.h>
46
47 void
plgpio_attach(struct plgpio_softc * sc)48 plgpio_attach(struct plgpio_softc *sc)
49 {
50 struct gpiobus_attach_args gba;
51 u_int pin;
52
53 sc->sc_gc.gp_cookie = sc;
54 sc->sc_gc.gp_pin_read = plgpio_pin_read;
55 sc->sc_gc.gp_pin_write = plgpio_pin_write;
56 sc->sc_gc.gp_pin_ctl = plgpio_pin_ctl;
57
58 const uint32_t cnf = PLGPIO_READ(sc, PL061_GPIOAFSEL_REG) |
59 sc->sc_reserved_mask;
60
61 for (pin = 0; pin < 8; pin++) {
62 sc->sc_pins[pin].pin_num = pin;
63 /* skip pins in hardware control mode */
64 if ((cnf & __BIT(pin)) != 0)
65 continue;
66 sc->sc_pins[pin].pin_caps =
67 GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
68 GPIO_PIN_TRISTATE;
69 sc->sc_pins[pin].pin_state =
70 plgpio_pin_read(sc, pin);
71 }
72
73 memset(&gba, 0, sizeof(gba));
74 gba.gba_gc = &sc->sc_gc;
75 gba.gba_pins = sc->sc_pins;
76 gba.gba_npins = 8;
77
78 #if NGPIO > 0
79 config_found(sc->sc_dev, &gba, gpiobus_print, CFARGS_NONE);
80 #endif
81 }
82
83 int
plgpio_pin_read(void * priv,int pin)84 plgpio_pin_read(void *priv, int pin)
85 {
86 struct plgpio_softc * const sc = priv;
87
88 const uint32_t v = PLGPIO_READ(sc, PL061_GPIODATA_REG(1<<pin));
89
90 return (v >> pin) & 1;
91 }
92
93 void
plgpio_pin_write(void * priv,int pin,int val)94 plgpio_pin_write(void *priv, int pin, int val)
95 {
96 struct plgpio_softc * const sc = priv;
97
98 PLGPIO_WRITE(sc, PL061_GPIODATA_REG(1 << pin), val << pin);
99 }
100
101 void
plgpio_pin_ctl(void * priv,int pin,int flags)102 plgpio_pin_ctl(void *priv, int pin, int flags)
103 {
104 struct plgpio_softc * const sc = priv;
105 uint32_t v;
106
107 if (flags & GPIO_PIN_INPUT) {
108 v = PLGPIO_READ(sc, PL061_GPIODIR_REG);
109 v &= ~(1 << pin);
110 PLGPIO_WRITE(sc, PL061_GPIODIR_REG, v);
111 } else if (flags & GPIO_PIN_OUTPUT) {
112 v = PLGPIO_READ(sc, PL061_GPIODIR_REG);
113 v |= (1 << pin);
114 PLGPIO_WRITE(sc, PL061_GPIODIR_REG, v);
115 }
116 }
117