1 /* $NetBSD: design_gsrd2.c,v 1.9 2023/12/20 14:18:37 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2006 Jachym Holecek
5 * All rights reserved.
6 *
7 * Written for DFC Design, s.r.o.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "opt_virtex.h"
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: design_gsrd2.c,v 1.9 2023/12/20 14:18:37 thorpej Exp $");
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/device.h>
40 #include <sys/kernel.h>
41 #include <sys/extent.h>
42 #include <sys/cpu.h>
43 #include <sys/bus.h>
44 #include <sys/intr.h>
45
46 #include <machine/powerpc.h>
47
48 #include <powerpc/ibm4xx/cpu.h>
49 #include <powerpc/ibm4xx/tlb.h>
50 #include <powerpc/ibm4xx/dev/plbvar.h>
51
52 #include <evbppc/virtex/dev/xcvbusvar.h>
53 #include <evbppc/virtex/dev/cdmacreg.h>
54 #include <evbppc/virtex/dev/temacreg.h>
55 #include <evbppc/virtex/dev/tftreg.h>
56
57 #include <evbppc/virtex/virtex.h>
58 #include <evbppc/virtex/dcr.h>
59
60
61 #define DCR_TEMAC_BASE 0x0030
62 #define DCR_TFT0_BASE 0x0082
63 #define DCR_TFT1_BASE 0x0086
64 #define DCR_CDMAC_BASE 0x0140
65
66 #define OPB_BASE 0x80000000 /* below are offsets in opb */
67 #define OPB_XLCOM_BASE 0x010000
68 #define OPB_GPIO_BASE 0x020000
69 #define OPB_PSTWO0_BASE 0x040000
70 #define OPB_PSTWO1_BASE 0x041000
71 #define CDMAC_NCHAN 2 /* cdmac {Tx,Rx} */
72 #define CDMAC_INTR_LINE 0
73
74 #define TFT_FB_BASE 0x3c00000
75 #define TFT_FB_SIZE (2*1024*1024)
76
77 /*
78 * CDMAC per-channel interrupt handler. CDMAC has one interrupt signal
79 * per two channels on mpmc2, so we have to dispatch channels manually.
80 *
81 * Note: we hardwire priority to IPL_NET, temac(4) is the only device that
82 * needs to service DMA interrupts anyway.
83 */
84 typedef struct cdmac_intrhand {
85 void (*cih_func)(void *);
86 void *cih_arg;
87 } *cdmac_intrhand_t;
88
89 /* Two instantiated channels, one logical interrupt per direction. */
90 static struct cdmac_intrhand cdmacintr[CDMAC_NCHAN];
91 static void *cdmac_ih;
92
93
94 /*
95 * DCR bus space leaf access routines.
96 */
97
98 #ifndef DESIGN_DFC
99 static void
tft0_write_4(bus_space_tag_t t,bus_space_handle_t h,uint32_t addr,uint32_t val)100 tft0_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr,
101 uint32_t val)
102 {
103 addr += h;
104
105 switch (addr) {
106 WCASE(DCR_TFT0_BASE, TFT_CTRL);
107 WCASE(DCR_TFT0_BASE, TFT_ADDR);
108 WDEAD(addr);
109 }
110 }
111
112 static uint32_t
tft0_read_4(bus_space_tag_t t,bus_space_handle_t h,uint32_t addr)113 tft0_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr)
114 {
115 uint32_t val;
116
117 addr += h;
118
119 switch (addr) {
120 RCASE(DCR_TFT0_BASE, TFT_CTRL);
121 RCASE(DCR_TFT0_BASE, TFT_ADDR);
122 RDEAD(addr);
123 }
124
125 return (val);
126 }
127 #endif /* !DESIGN_DFC */
128
129 static void
tft1_write_4(bus_space_tag_t t,bus_space_handle_t h,uint32_t addr,uint32_t val)130 tft1_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr,
131 uint32_t val)
132 {
133 addr += h;
134
135 switch (addr) {
136 WCASE(DCR_TFT1_BASE, TFT_CTRL);
137 WCASE(DCR_TFT0_BASE, TFT_ADDR);
138 WDEAD(addr);
139 }
140 }
141
142 static uint32_t
tft1_read_4(bus_space_tag_t t,bus_space_handle_t h,uint32_t addr)143 tft1_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr)
144 {
145 uint32_t val;
146
147 addr += h;
148
149 switch (addr) {
150 RCASE(DCR_TFT1_BASE, TFT_CTRL);
151 RCASE(DCR_TFT0_BASE, TFT_ADDR);
152 RDEAD(addr);
153 }
154
155 return (val);
156 }
157
158 #define DOCHAN(op, base, channel) \
159 op(base, channel + CDMAC_NEXT); \
160 op(base, channel + CDMAC_CURADDR); \
161 op(base, channel + CDMAC_CURSIZE); \
162 op(base, channel + CDMAC_CURDESC)
163
164 static void
cdmac_write_4(bus_space_tag_t t,bus_space_handle_t h,uint32_t addr,uint32_t val)165 cdmac_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr,
166 uint32_t val)
167 {
168 addr += h;
169
170 switch (addr) {
171 WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); /* Tx engine */
172 WCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); /* Rx engine */
173 WCASE(DCR_CDMAC_BASE, CDMAC_INTR);
174 DOCHAN(WCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(0));
175 DOCHAN(WCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(1));
176 WDEAD(addr);
177 }
178 }
179
180 static uint32_t
cdmac_read_4(bus_space_tag_t t,bus_space_handle_t h,uint32_t addr)181 cdmac_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr)
182 {
183 uint32_t val;
184
185 addr += h;
186
187 switch (addr) {
188 RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); /* Tx engine */
189 RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); /* Rx engine */
190 RCASE(DCR_CDMAC_BASE, CDMAC_INTR);
191 DOCHAN(RCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(0));
192 DOCHAN(RCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(1));
193 RDEAD(addr);
194 }
195
196 return (val);
197 }
198
199 #undef DOCHAN
200
201 static void
temac_write_4(bus_space_tag_t t,bus_space_handle_t h,uint32_t addr,uint32_t val)202 temac_write_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr,
203 uint32_t val)
204 {
205 addr += h;
206
207 switch (addr) {
208 WCASE(DCR_TEMAC_BASE, TEMAC_RESET);
209 WDEAD(addr);
210 }
211 }
212
213 static uint32_t
temac_read_4(bus_space_tag_t t,bus_space_handle_t h,uint32_t addr)214 temac_read_4(bus_space_tag_t t, bus_space_handle_t h, uint32_t addr)
215 {
216 uint32_t val;
217
218 addr += h;
219
220 switch (addr) {
221 RCASE(DCR_TEMAC_BASE, TEMAC_RESET);
222 RDEAD(addr);
223 }
224
225 return (val);
226 }
227
228 static const struct powerpc_bus_space cdmac_bst = {
229 DCR_BST_BODY(DCR_CDMAC_BASE, cdmac_read_4, cdmac_write_4)
230 };
231
232 static const struct powerpc_bus_space temac_bst = {
233 DCR_BST_BODY(DCR_TEMAC_BASE, temac_read_4, temac_write_4)
234 };
235
236 #ifndef DESIGN_DFC
237 static const struct powerpc_bus_space tft0_bst = {
238 DCR_BST_BODY(DCR_TFT0_BASE, tft0_read_4, tft0_write_4)
239 };
240 #endif
241
242 static const struct powerpc_bus_space tft1_bst = {
243 DCR_BST_BODY(DCR_TFT1_BASE, tft1_read_4, tft1_write_4)
244 };
245
246 static struct powerpc_bus_space opb_bst = {
247 .pbs_flags = _BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE,
248 .pbs_base = 0 /*OPB_BASE*/,
249 .pbs_offset = OPB_BASE,
250 };
251
252 static char opb_extent_storage[EXTENT_FIXED_STORAGE_SIZE(8)] __aligned(8);
253
254 /*
255 * Master device configuration table for GSRD2 design.
256 */
257 static const struct gsrddev {
258 const char *gdv_name;
259 const char *gdv_attr;
260 bus_space_tag_t gdv_bst;
261 bus_addr_t gdv_addr;
262 int gdv_intr;
263 int gdv_rx_dma;
264 int gdv_tx_dma;
265 int gdv_dcr; /* XXX bst flag */
266 } gsrd_devices[] = {
267 { /* gsrd_devices[0] */
268 .gdv_name = "xlcom",
269 .gdv_attr = "xcvbus",
270 .gdv_bst = &opb_bst,
271 .gdv_addr = OPB_XLCOM_BASE,
272 .gdv_intr = 2,
273 .gdv_rx_dma = -1,
274 .gdv_tx_dma = -1,
275 .gdv_dcr = 0,
276 },
277 { /* gsrd_devices[1] */
278 .gdv_name = "temac",
279 .gdv_attr = "xcvbus",
280 .gdv_bst = &temac_bst,
281 .gdv_addr = 0,
282 .gdv_intr = 1, /* unused MII intr */
283 .gdv_rx_dma = 1, /* cdmac Rx */
284 .gdv_tx_dma = 0, /* cdmac Tx */
285 .gdv_dcr = 1,
286 },
287 #ifndef DESIGN_DFC
288 { /* gsrd_devices[2] */
289 .gdv_name = "tft",
290 .gdv_attr = "plbus",
291 .gdv_bst = &tft0_bst,
292 .gdv_addr = 0,
293 .gdv_intr = -1,
294 .gdv_rx_dma = -1,
295 .gdv_tx_dma = -1,
296 .gdv_dcr = 1,
297 },
298 #endif
299 { /* gsrd_devices[2] */
300 .gdv_name = "tft",
301 .gdv_attr = "plbus",
302 .gdv_bst = &tft1_bst,
303 .gdv_addr = 0,
304 .gdv_intr = -1,
305 .gdv_rx_dma = -1,
306 .gdv_tx_dma = -1,
307 .gdv_dcr = 1,
308 },
309 #ifdef DESIGN_DFC
310 { /* gsrd_devices[3] */
311 .gdv_name = "pstwo",
312 .gdv_attr = "xcvbus",
313 .gdv_bst = &opb_bst,
314 .gdv_addr = OPB_PSTWO0_BASE,
315 .gdv_intr = 3,
316 .gdv_rx_dma = -1,
317 .gdv_tx_dma = -1,
318 .gdv_dcr = 0,
319 },
320 { /* gsrd_devices[4] */
321 .gdv_name = "pstwo",
322 .gdv_attr = "xcvbus",
323 .gdv_bst = &opb_bst,
324 .gdv_addr = OPB_PSTWO1_BASE,
325 .gdv_intr = 4,
326 .gdv_rx_dma = -1,
327 .gdv_tx_dma = -1,
328 .gdv_dcr = 0,
329 },
330 #endif
331 };
332
333 static struct ll_dmac *
virtex_mpmc_mapdma(int idx,struct ll_dmac * chan)334 virtex_mpmc_mapdma(int idx, struct ll_dmac *chan)
335 {
336 if (idx == -1)
337 return (NULL);
338
339 KASSERT(idx >= 0 && idx < CDMAC_NCHAN);
340
341 chan->dmac_iot = &cdmac_bst;
342 chan->dmac_ctrl_addr = CDMAC_CTRL_BASE(idx);
343 chan->dmac_stat_addr = CDMAC_STAT_BASE(idx);
344 chan->dmac_chan = idx;
345
346 return (chan);
347 }
348
349 static int
cdmac_intr(void * arg)350 cdmac_intr(void *arg)
351 {
352 uint32_t isr;
353 int did = 0;
354
355 isr = bus_space_read_4(&cdmac_bst, 0, CDMAC_INTR);
356
357 if (ISSET(isr, CDMAC_INTR_TX0) && cdmacintr[0].cih_func) {
358 (cdmacintr[0].cih_func)(cdmacintr[0].cih_arg);
359 did++;
360 }
361 if (ISSET(isr, CDMAC_INTR_RX0) && cdmacintr[1].cih_func) {
362 (cdmacintr[1].cih_func)(cdmacintr[1].cih_arg);
363 did++;
364 }
365
366 bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, isr); /* ack */
367
368 /* XXX This still happens all the time under load. */
369 #if 0
370 if (did == 0)
371 aprint_normal("WARNING: stray cdmac isr 0x%x\n", isr);
372 #endif
373 return (0);
374 }
375
376 /*
377 * Public interface.
378 */
379
380 void
virtex_autoconf(device_t self,struct plb_attach_args * paa)381 virtex_autoconf(device_t self, struct plb_attach_args *paa)
382 {
383
384 struct xcvbus_attach_args vaa;
385 struct ll_dmac rx, tx;
386 int i;
387
388 /* Reset DMA channels. */
389 bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(0), CDMAC_STAT_RESET);
390 bus_space_write_4(&cdmac_bst, 0, CDMAC_STAT_BASE(1), CDMAC_STAT_RESET);
391 bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, 0);
392
393 vaa.vaa_dmat = paa->plb_dmat;
394
395 for (i = 0; i < __arraycount(gsrd_devices); i++) {
396 const struct gsrddev *g = &gsrd_devices[i];
397
398 vaa._vaa_is_dcr = g->gdv_dcr; /* XXX bst flag */
399 vaa.vaa_name = g->gdv_name;
400 vaa.vaa_addr = g->gdv_addr;
401 vaa.vaa_intr = g->gdv_intr;
402 vaa.vaa_iot = g->gdv_bst;
403
404 vaa.vaa_rx_dmac = virtex_mpmc_mapdma(g->gdv_rx_dma, &rx);
405 vaa.vaa_tx_dmac = virtex_mpmc_mapdma(g->gdv_tx_dma, &tx);
406
407 config_found(self, &vaa, xcvbus_print,
408 CFARGS(.iattr = g->gdv_attr));
409 }
410
411 /* Setup the dispatch handler. */
412 cdmac_ih = intr_establish(CDMAC_INTR_LINE, IST_LEVEL, IPL_NET,
413 cdmac_intr, NULL);
414 if (cdmac_ih == NULL)
415 panic("virtex_mpmc_done: could not establish cdmac intr");
416
417 /* Clear (XXX?) and enable interrupts. */
418 bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, ~CDMAC_INTR_MIE);
419 bus_space_write_4(&cdmac_bst, 0, CDMAC_INTR, CDMAC_INTR_MIE);
420 }
421
422 void *
ll_dmac_intr_establish(int chan,void (* handler)(void *),void * arg)423 ll_dmac_intr_establish(int chan, void (*handler)(void *), void *arg)
424 {
425 KASSERT(chan >= 0 && chan < CDMAC_NCHAN);
426 KASSERT(cdmacintr[chan].cih_func == NULL);
427 KASSERT(cdmacintr[chan].cih_arg == NULL);
428
429 cdmacintr[chan].cih_func = handler;
430 cdmacintr[chan].cih_arg = arg;
431
432 return (&cdmacintr[chan]);
433 }
434
435 void
ll_dmac_intr_disestablish(int chan,void * handle)436 ll_dmac_intr_disestablish(int chan, void *handle)
437 {
438 int s;
439
440 KASSERT(chan >= 0 && chan < CDMAC_NCHAN);
441 KASSERT(&cdmacintr[chan] == handle);
442
443 s = splnet();
444 cdmacintr[chan].cih_func = NULL;
445 cdmacintr[chan].cih_arg = NULL;
446 splx(s);
447 }
448
449 int
virtex_bus_space_tag(const char * xname,bus_space_tag_t * bst)450 virtex_bus_space_tag(const char *xname, bus_space_tag_t *bst)
451 {
452 if (strncmp(xname, "xlcom", 5) == 0) {
453 *bst = &opb_bst;
454 return (0);
455 }
456
457 return (ENODEV);
458 }
459
460 void
virtex_machdep_init(vaddr_t endva,vsize_t maxsz,struct mem_region * phys,struct mem_region * avail)461 virtex_machdep_init(vaddr_t endva, vsize_t maxsz, struct mem_region *phys,
462 struct mem_region *avail)
463 {
464 ppc4xx_tlb_reserve(OPB_BASE, endva, maxsz, TLB_I | TLB_G);
465 endva += maxsz;
466
467 opb_bst.pbs_limit = maxsz;
468
469 if (bus_space_init(&opb_bst, "opbtag", opb_extent_storage,
470 sizeof(opb_extent_storage)))
471 panic("virtex_machdep_init: failed to initialize opb_bst");
472
473 /*
474 * The TFT controller is broken, we can't change FB address.
475 * Hardwire it at predefined base address, create uncached
476 * mapping.
477 */
478
479 avail[0].size = TFT_FB_BASE - avail[0].start;
480 ppc4xx_tlb_reserve(TFT_FB_BASE, endva, TFT_FB_SIZE, TLB_I | TLB_G);
481 }
482
483 void
device_register(device_t dev,void * aux)484 device_register(device_t dev, void *aux)
485 {
486 prop_number_t pn;
487 void *fb;
488
489 if (strncmp(device_xname(dev), "tft0", 4) == 0) {
490 fb = ppc4xx_tlb_mapiodev(TFT_FB_BASE, TFT_FB_SIZE);
491 if (fb == NULL)
492 panic("device_register: framebuffer mapping gone!\n");
493
494 pn = prop_number_create_unsigned_integer(TFT_FB_BASE);
495 if (pn == NULL) {
496 printf("WARNING: could not allocate virtex-tft-pa\n");
497 return ;
498 }
499 if (prop_dictionary_set(device_properties(dev),
500 "virtex-tft-pa", pn) != true)
501 printf("WARNING: could not set virtex-tft-pa\n");
502 prop_object_release(pn);
503
504 pn = prop_number_create_unsigned_integer((uintptr_t)fb);
505 if (pn == NULL) {
506 printf("WARNING: could not allocate virtex-tft-va\n");
507 return ;
508 }
509 if (prop_dictionary_set(device_properties(dev),
510 "virtex-tft-va", pn) != true)
511 printf("WARNING: could not set virtex-tft-va\n");
512 prop_object_release(pn);
513 }
514 }
515