1 /* $NetBSD: dcn20_vmid.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef DAL_DC_DCN20_DCN20_VMID_H_ 29 #define DAL_DC_DCN20_DCN20_VMID_H_ 30 31 #include "vmid.h" 32 33 #define BASE_INNER(seg) \ 34 DCE_BASE__INST0_SEG ## seg 35 36 #define BASE(seg) \ 37 BASE_INNER(seg) 38 39 #define SRI(reg_name, block, id)\ 40 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 41 mm ## block ## id ## _ ## reg_name 42 43 #define SF(reg_name, field_name, post_fix)\ 44 .field_name = reg_name ## __ ## field_name ## post_fix 45 46 #define DCN20_VMID_REG_LIST(id)\ 47 SRI(CNTL, DCN_VM_CONTEXT, id),\ 48 SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\ 49 SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\ 50 SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\ 51 SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\ 52 SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\ 53 SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id) 54 55 #define DCN20_VMID_MASK_SH_LIST(mask_sh)\ 56 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_DEPTH, mask_sh),\ 57 SF(DCN_VM_CONTEXT0_CNTL, VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, mask_sh),\ 58 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 59 SF(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 60 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 61 SF(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 62 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 63 SF(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, mask_sh) 64 65 #define DCN20_VMID_REG_FIELD_LIST(type)\ 66 type VM_CONTEXT0_PAGE_TABLE_DEPTH;\ 67 type VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE;\ 68 type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32;\ 69 type VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32;\ 70 type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4;\ 71 type VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32;\ 72 type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4;\ 73 type VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32 74 75 struct dcn20_vmid_shift { 76 DCN20_VMID_REG_FIELD_LIST(uint8_t); 77 }; 78 79 struct dcn20_vmid_mask { 80 DCN20_VMID_REG_FIELD_LIST(uint32_t); 81 }; 82 83 struct dcn20_vmid { 84 struct dc_context *ctx; 85 const struct dcn_vmid_registers *regs; 86 const struct dcn20_vmid_shift *shifts; 87 const struct dcn20_vmid_mask *masks; 88 }; 89 90 void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config); 91 92 #endif /* DAL_DC_DCN20_DCN20_VMID_H_ */ 93