xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/dcn10_link_encoder.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: dcn10_link_encoder.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2012-15 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  *  and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: AMD
25  *
26  */
27 
28 #ifndef __DC_LINK_ENCODER__DCN10_H__
29 #define __DC_LINK_ENCODER__DCN10_H__
30 
31 #include "link_encoder.h"
32 
33 #define TO_DCN10_LINK_ENC(link_encoder)\
34 	container_of(link_encoder, struct dcn10_link_encoder, base)
35 
36 
37 #define AUX_REG_LIST(id)\
38 	SRI(AUX_CONTROL, DP_AUX, id), \
39 	SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
40 
41 #define HPD_REG_LIST(id)\
42 	SRI(DC_HPD_CONTROL, HPD, id)
43 
44 #define LE_DCN_COMMON_REG_LIST(id) \
45 	SRI(DIG_BE_CNTL, DIG, id), \
46 	SRI(DIG_BE_EN_CNTL, DIG, id), \
47 	SRI(TMDS_CTL_BITS, DIG, id), \
48 	SRI(DP_CONFIG, DP, id), \
49 	SRI(DP_DPHY_CNTL, DP, id), \
50 	SRI(DP_DPHY_PRBS_CNTL, DP, id), \
51 	SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
52 	SRI(DP_DPHY_SYM0, DP, id), \
53 	SRI(DP_DPHY_SYM1, DP, id), \
54 	SRI(DP_DPHY_SYM2, DP, id), \
55 	SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
56 	SRI(DP_LINK_CNTL, DP, id), \
57 	SRI(DP_LINK_FRAMING_CNTL, DP, id), \
58 	SRI(DP_MSE_SAT0, DP, id), \
59 	SRI(DP_MSE_SAT1, DP, id), \
60 	SRI(DP_MSE_SAT2, DP, id), \
61 	SRI(DP_MSE_SAT_UPDATE, DP, id), \
62 	SRI(DP_SEC_CNTL, DP, id), \
63 	SRI(DP_VID_STREAM_CNTL, DP, id), \
64 	SRI(DP_DPHY_FAST_TRAINING, DP, id), \
65 	SRI(DP_SEC_CNTL1, DP, id), \
66 	SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
67 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
68 	SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
69 
70 
71 #define LE_DCN10_REG_LIST(id)\
72 	LE_DCN_COMMON_REG_LIST(id)
73 
74 struct dcn10_link_enc_aux_registers {
75 	uint32_t AUX_CONTROL;
76 	uint32_t AUX_DPHY_RX_CONTROL0;
77 	uint32_t AUX_DPHY_TX_CONTROL;
78 };
79 
80 struct dcn10_link_enc_hpd_registers {
81 	uint32_t DC_HPD_CONTROL;
82 };
83 
84 struct dcn10_link_enc_registers {
85 	uint32_t DIG_BE_CNTL;
86 	uint32_t DIG_BE_EN_CNTL;
87 	uint32_t DP_CONFIG;
88 	uint32_t DP_DPHY_CNTL;
89 	uint32_t DP_DPHY_INTERNAL_CTRL;
90 	uint32_t DP_DPHY_PRBS_CNTL;
91 	uint32_t DP_DPHY_SCRAM_CNTL;
92 	uint32_t DP_DPHY_SYM0;
93 	uint32_t DP_DPHY_SYM1;
94 	uint32_t DP_DPHY_SYM2;
95 	uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
96 	uint32_t DP_LINK_CNTL;
97 	uint32_t DP_LINK_FRAMING_CNTL;
98 	uint32_t DP_MSE_SAT0;
99 	uint32_t DP_MSE_SAT1;
100 	uint32_t DP_MSE_SAT2;
101 	uint32_t DP_MSE_SAT_UPDATE;
102 	uint32_t DP_SEC_CNTL;
103 	uint32_t DP_VID_STREAM_CNTL;
104 	uint32_t DP_DPHY_FAST_TRAINING;
105 	uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
106 	uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
107 	uint32_t DP_SEC_CNTL1;
108 	uint32_t TMDS_CTL_BITS;
109 	/* DCCG  */
110 	uint32_t CLOCK_ENABLE;
111 	/* DIG */
112 	uint32_t DIG_LANE_ENABLE;
113 	/* UNIPHY */
114 	uint32_t CHANNEL_XBAR_CNTL;
115 	/* DPCS */
116 	uint32_t RDPCSTX_PHY_CNTL3;
117 	uint32_t RDPCSTX_PHY_CNTL4;
118 	uint32_t RDPCSTX_PHY_CNTL5;
119 	uint32_t RDPCSTX_PHY_CNTL6;
120 	uint32_t RDPCSTX_PHY_CNTL7;
121 	uint32_t RDPCSTX_PHY_CNTL8;
122 	uint32_t RDPCSTX_PHY_CNTL9;
123 	uint32_t RDPCSTX_PHY_CNTL10;
124 	uint32_t RDPCSTX_PHY_CNTL11;
125 	uint32_t RDPCSTX_PHY_CNTL12;
126 	uint32_t RDPCSTX_PHY_CNTL13;
127 	uint32_t RDPCSTX_PHY_CNTL14;
128 	uint32_t RDPCSTX_PHY_CNTL15;
129 	uint32_t RDPCSTX_CNTL;
130 	uint32_t RDPCSTX_CLOCK_CNTL;
131 	uint32_t RDPCSTX_PHY_CNTL0;
132 	uint32_t RDPCSTX_PHY_CNTL2;
133 	uint32_t RDPCSTX_PLL_UPDATE_DATA;
134 	uint32_t RDPCS_TX_CR_ADDR;
135 	uint32_t RDPCS_TX_CR_DATA;
136 	uint32_t DPCSTX_TX_CLOCK_CNTL;
137 	uint32_t DPCSTX_TX_CNTL;
138 	uint32_t RDPCSTX_INTERRUPT_CONTROL;
139 	uint32_t RDPCSTX_PHY_FUSE0;
140 	uint32_t RDPCSTX_PHY_FUSE1;
141 	uint32_t RDPCSTX_PHY_FUSE2;
142 	uint32_t RDPCSTX_PHY_FUSE3;
143 	uint32_t RDPCSTX_PHY_RX_LD_VAL;
144 	uint32_t DPCSTX_DEBUG_CONFIG;
145 	uint32_t RDPCSTX_DEBUG_CONFIG;
146 	uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
147 	uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
148 	uint32_t DCIO_SOFT_RESET;
149 	/* indirect registers */
150 	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
151 	uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
152 	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
153 	uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
154 	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
155 	uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
156 	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
157 	uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
158 };
159 
160 #define LE_SF(reg_name, field_name, post_fix)\
161 	.field_name = reg_name ## __ ## field_name ## post_fix
162 
163 #define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
164 	LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
165 	LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
166 	LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
167 	LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
168 	LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
169 	LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
170 	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
171 	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
172 	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
173 	LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
174 	LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
175 	LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
176 	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
177 	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
178 	LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
179 	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
180 	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
181 	LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
182 	LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
183 	LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
184 	LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
185 	LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
186 	LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
187 	LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
188 	LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
189 	LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
190 	LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
191 	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
192 	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
193 	LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
194 	LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
195 	LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
196 	LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
197 	LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
198 	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
199 	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
200 	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
201 	LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
202 	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
203 	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
204 	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
205 	LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
206 	LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
207 	LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
208 	LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
209 	LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
210 	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
211 	LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
212 
213 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
214 	type DIG_ENABLE;\
215 	type DIG_HPD_SELECT;\
216 	type DIG_MODE;\
217 	type DIG_FE_SOURCE_SELECT;\
218 	type DPHY_BYPASS;\
219 	type DPHY_ATEST_SEL_LANE0;\
220 	type DPHY_ATEST_SEL_LANE1;\
221 	type DPHY_ATEST_SEL_LANE2;\
222 	type DPHY_ATEST_SEL_LANE3;\
223 	type DPHY_PRBS_EN;\
224 	type DPHY_PRBS_SEL;\
225 	type DPHY_SYM1;\
226 	type DPHY_SYM2;\
227 	type DPHY_SYM3;\
228 	type DPHY_SYM4;\
229 	type DPHY_SYM5;\
230 	type DPHY_SYM6;\
231 	type DPHY_SYM7;\
232 	type DPHY_SYM8;\
233 	type DPHY_SCRAMBLER_BS_COUNT;\
234 	type DPHY_SCRAMBLER_ADVANCE;\
235 	type DPHY_RX_FAST_TRAINING_CAPABLE;\
236 	type DPHY_LOAD_BS_COUNT;\
237 	type DPHY_TRAINING_PATTERN_SEL;\
238 	type DP_DPHY_HBR2_PATTERN_CONTROL;\
239 	type DP_LINK_TRAINING_COMPLETE;\
240 	type DP_IDLE_BS_INTERVAL;\
241 	type DP_VBID_DISABLE;\
242 	type DP_VID_ENHANCED_FRAME_MODE;\
243 	type DP_VID_STREAM_ENABLE;\
244 	type DP_UDI_LANES;\
245 	type DP_SEC_GSP0_LINE_NUM;\
246 	type DP_SEC_GSP0_PRIORITY;\
247 	type DP_MSE_SAT_SRC0;\
248 	type DP_MSE_SAT_SRC1;\
249 	type DP_MSE_SAT_SRC2;\
250 	type DP_MSE_SAT_SRC3;\
251 	type DP_MSE_SAT_SLOT_COUNT0;\
252 	type DP_MSE_SAT_SLOT_COUNT1;\
253 	type DP_MSE_SAT_SLOT_COUNT2;\
254 	type DP_MSE_SAT_SLOT_COUNT3;\
255 	type DP_MSE_SAT_UPDATE;\
256 	type DP_MSE_16_MTP_KEEPOUT;\
257 	type DC_HPD_EN;\
258 	type TMDS_CTL0;\
259 	type AUX_HPD_SEL;\
260 	type AUX_LS_READ_EN;\
261 	type AUX_RX_RECEIVE_WINDOW
262 
263 
264 #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
265 		type RDPCS_PHY_DP_TX0_DATA_EN;\
266 		type RDPCS_PHY_DP_TX1_DATA_EN;\
267 		type RDPCS_PHY_DP_TX2_DATA_EN;\
268 		type RDPCS_PHY_DP_TX3_DATA_EN;\
269 		type RDPCS_PHY_DP_TX0_PSTATE;\
270 		type RDPCS_PHY_DP_TX1_PSTATE;\
271 		type RDPCS_PHY_DP_TX2_PSTATE;\
272 		type RDPCS_PHY_DP_TX3_PSTATE;\
273 		type RDPCS_PHY_DP_TX0_MPLL_EN;\
274 		type RDPCS_PHY_DP_TX1_MPLL_EN;\
275 		type RDPCS_PHY_DP_TX2_MPLL_EN;\
276 		type RDPCS_PHY_DP_TX3_MPLL_EN;\
277 		type RDPCS_TX_FIFO_LANE0_EN;\
278 		type RDPCS_TX_FIFO_LANE1_EN;\
279 		type RDPCS_TX_FIFO_LANE2_EN;\
280 		type RDPCS_TX_FIFO_LANE3_EN;\
281 		type RDPCS_EXT_REFCLK_EN;\
282 		type RDPCS_TX_FIFO_EN;\
283 		type UNIPHY_LINK_ENABLE;\
284 		type UNIPHY_CHANNEL0_XBAR_SOURCE;\
285 		type UNIPHY_CHANNEL1_XBAR_SOURCE;\
286 		type UNIPHY_CHANNEL2_XBAR_SOURCE;\
287 		type UNIPHY_CHANNEL3_XBAR_SOURCE;\
288 		type UNIPHY_CHANNEL0_INVERT;\
289 		type UNIPHY_CHANNEL1_INVERT;\
290 		type UNIPHY_CHANNEL2_INVERT;\
291 		type UNIPHY_CHANNEL3_INVERT;\
292 		type UNIPHY_LINK_ENABLE_HPD_MASK;\
293 		type UNIPHY_LANE_STAGGER_DELAY;\
294 		type RDPCS_SRAMCLK_BYPASS;\
295 		type RDPCS_SRAMCLK_EN;\
296 		type RDPCS_SRAMCLK_CLOCK_ON;\
297 		type DPCS_TX_FIFO_EN;\
298 		type RDPCS_PHY_DP_TX0_DISABLE;\
299 		type RDPCS_PHY_DP_TX1_DISABLE;\
300 		type RDPCS_PHY_DP_TX2_DISABLE;\
301 		type RDPCS_PHY_DP_TX3_DISABLE;\
302 		type RDPCS_PHY_DP_TX0_CLK_RDY;\
303 		type RDPCS_PHY_DP_TX1_CLK_RDY;\
304 		type RDPCS_PHY_DP_TX2_CLK_RDY;\
305 		type RDPCS_PHY_DP_TX3_CLK_RDY;\
306 		type RDPCS_PHY_DP_TX0_REQ;\
307 		type RDPCS_PHY_DP_TX1_REQ;\
308 		type RDPCS_PHY_DP_TX2_REQ;\
309 		type RDPCS_PHY_DP_TX3_REQ;\
310 		type RDPCS_PHY_DP_TX0_ACK;\
311 		type RDPCS_PHY_DP_TX1_ACK;\
312 		type RDPCS_PHY_DP_TX2_ACK;\
313 		type RDPCS_PHY_DP_TX3_ACK;\
314 		type RDPCS_PHY_DP_TX0_RESET;\
315 		type RDPCS_PHY_DP_TX1_RESET;\
316 		type RDPCS_PHY_DP_TX2_RESET;\
317 		type RDPCS_PHY_DP_TX3_RESET;\
318 		type RDPCS_PHY_RESET;\
319 		type RDPCS_PHY_CR_MUX_SEL;\
320 		type RDPCS_PHY_REF_RANGE;\
321 		type RDPCS_PHY_DP4_POR;\
322 		type RDPCS_SRAM_BYPASS;\
323 		type RDPCS_SRAM_EXT_LD_DONE;\
324 		type RDPCS_PHY_DP_TX0_TERM_CTRL;\
325 		type RDPCS_PHY_DP_TX1_TERM_CTRL;\
326 		type RDPCS_PHY_DP_TX2_TERM_CTRL;\
327 		type RDPCS_PHY_DP_TX3_TERM_CTRL;\
328 		type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
329 		type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
330 		type RDPCS_PHY_DP_MPLLB_SSC_EN;\
331 		type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
332 		type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
333 		type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
334 		type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
335 		type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
336 		type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
337 		type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
338 		type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
339 		type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
340 		type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
341 		type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
342 		type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
343 		type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
344 		type RDPCS_PHY_TX_VBOOST_LVL;\
345 		type RDPCS_PHY_HDMIMODE_ENABLE;\
346 		type RDPCS_PHY_DP_REF_CLK_EN;\
347 		type RDPCS_PLL_UPDATE_DATA;\
348 		type RDPCS_SRAM_INIT_DONE;\
349 		type RDPCS_TX_CR_ADDR;\
350 		type RDPCS_TX_CR_DATA;\
351 		type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
352 		type RDPCS_PHY_DP_MPLLB_STATE;\
353 		type RDPCS_PHY_DP_TX0_WIDTH;\
354 		type RDPCS_PHY_DP_TX0_RATE;\
355 		type RDPCS_PHY_DP_TX1_WIDTH;\
356 		type RDPCS_PHY_DP_TX1_RATE;\
357 		type RDPCS_PHY_DP_TX2_WIDTH;\
358 		type RDPCS_PHY_DP_TX2_RATE;\
359 		type RDPCS_PHY_DP_TX3_WIDTH;\
360 		type RDPCS_PHY_DP_TX3_RATE;\
361 		type DPCS_SYMCLK_CLOCK_ON;\
362 		type DPCS_SYMCLK_GATE_DIS;\
363 		type DPCS_SYMCLK_EN;\
364 		type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
365 		type RDPCS_SYMCLK_DIV2_GATE_DIS;\
366 		type RDPCS_SYMCLK_DIV2_EN;\
367 		type DPCS_TX_DATA_SWAP;\
368 		type DPCS_TX_DATA_ORDER_INVERT;\
369 		type DPCS_TX_FIFO_RD_START_DELAY;\
370 		type RDPCS_TX_FIFO_RD_START_DELAY;\
371 		type RDPCS_REG_FIFO_ERROR_MASK;\
372 		type RDPCS_TX_FIFO_ERROR_MASK;\
373 		type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
374 		type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
375 		type RDPCS_PHY_DPALT_DP4;\
376 		type RDPCS_PHY_DPALT_DISABLE;\
377 		type RDPCS_PHY_DPALT_DISABLE_ACK;\
378 		type RDPCS_PHY_DP_MPLLB_V2I;\
379 		type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
380 		type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
381 		type RDPCS_PHY_RX_VREF_CTRL;\
382 		type RDPCS_PHY_DP_MPLLB_CP_INT;\
383 		type RDPCS_PHY_DP_MPLLB_CP_PROP;\
384 		type RDPCS_PHY_RX_REF_LD_VAL;\
385 		type RDPCS_PHY_RX_VCO_LD_VAL;\
386 		type DPCSTX_DEBUG_CONFIG; \
387 		type RDPCSTX_DEBUG_CONFIG; \
388 		type RDPCS_PHY_DP_TX0_EQ_MAIN;\
389 		type RDPCS_PHY_DP_TX0_EQ_PRE;\
390 		type RDPCS_PHY_DP_TX0_EQ_POST;\
391 		type RDPCS_PHY_DP_TX1_EQ_MAIN;\
392 		type RDPCS_PHY_DP_TX1_EQ_PRE;\
393 		type RDPCS_PHY_DP_TX1_EQ_POST;\
394 		type RDPCS_PHY_DP_TX2_EQ_MAIN;\
395 		type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
396 		type RDPCS_PHY_DP_TX2_EQ_PRE;\
397 		type RDPCS_PHY_DP_TX2_EQ_POST;\
398 		type RDPCS_PHY_DP_TX3_EQ_MAIN;\
399 		type RDPCS_PHY_DCO_RANGE;\
400 		type RDPCS_PHY_DCO_FINETUNE;\
401 		type RDPCS_PHY_DP_TX3_EQ_PRE;\
402 		type RDPCS_PHY_DP_TX3_EQ_POST;\
403 		type RDPCS_PHY_SUP_PRE_HP;\
404 		type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
405 		type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
406 		type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
407 		type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
408 		type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
409 		type UNIPHYA_SOFT_RESET;\
410 		type UNIPHYB_SOFT_RESET;\
411 		type UNIPHYC_SOFT_RESET;\
412 		type UNIPHYD_SOFT_RESET;\
413 		type UNIPHYE_SOFT_RESET;\
414 		type UNIPHYF_SOFT_RESET
415 
416 #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
417 	type DIG_LANE0EN;\
418 	type DIG_LANE1EN;\
419 	type DIG_LANE2EN;\
420 	type DIG_LANE3EN;\
421 	type DIG_CLK_EN;\
422 	type SYMCLKA_CLOCK_ENABLE;\
423 	type DPHY_FEC_EN;\
424 	type DPHY_FEC_READY_SHADOW;\
425 	type DPHY_FEC_ACTIVE_STATUS;\
426 	DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
427 	type VCO_LD_VAL_OVRD;\
428 	type VCO_LD_VAL_OVRD_EN;\
429 	type REF_LD_VAL_OVRD;\
430 	type REF_LD_VAL_OVRD_EN;\
431 	type AUX_RX_START_WINDOW; \
432 	type AUX_RX_HALF_SYM_DETECT_LEN; \
433 	type AUX_RX_TRANSITION_FILTER_EN; \
434 	type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
435 	type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
436 	type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
437 	type AUX_RX_PHASE_DETECT_LEN; \
438 	type AUX_RX_DETECTION_THRESHOLD; \
439 	type AUX_TX_PRECHARGE_LEN; \
440 	type AUX_TX_PRECHARGE_SYMBOLS; \
441 	type AUX_MODE_DET_CHECK_DELAY;\
442 	type DPCS_DBG_CBUS_DIS
443 
444 struct dcn10_link_enc_shift {
445 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
446 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
447 };
448 
449 struct dcn10_link_enc_mask {
450 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
451 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
452 };
453 
454 struct dcn10_link_encoder {
455 	struct link_encoder base;
456 	const struct dcn10_link_enc_registers *link_regs;
457 	const struct dcn10_link_enc_aux_registers *aux_regs;
458 	const struct dcn10_link_enc_hpd_registers *hpd_regs;
459 	const struct dcn10_link_enc_shift *link_shift;
460 	const struct dcn10_link_enc_mask *link_mask;
461 };
462 
463 
464 void dcn10_link_encoder_construct(
465 	struct dcn10_link_encoder *enc10,
466 	const struct encoder_init_data *init_data,
467 	const struct encoder_feature_support *enc_features,
468 	const struct dcn10_link_enc_registers *link_regs,
469 	const struct dcn10_link_enc_aux_registers *aux_regs,
470 	const struct dcn10_link_enc_hpd_registers *hpd_regs,
471 	const struct dcn10_link_enc_shift *link_shift,
472 	const struct dcn10_link_enc_mask *link_mask);
473 
474 bool dcn10_link_encoder_validate_dvi_output(
475 	const struct dcn10_link_encoder *enc10,
476 	enum signal_type connector_signal,
477 	enum signal_type signal,
478 	const struct dc_crtc_timing *crtc_timing);
479 
480 bool dcn10_link_encoder_validate_rgb_output(
481 	const struct dcn10_link_encoder *enc10,
482 	const struct dc_crtc_timing *crtc_timing);
483 
484 bool dcn10_link_encoder_validate_dp_output(
485 	const struct dcn10_link_encoder *enc10,
486 	const struct dc_crtc_timing *crtc_timing);
487 
488 bool dcn10_link_encoder_validate_wireless_output(
489 	const struct dcn10_link_encoder *enc10,
490 	const struct dc_crtc_timing *crtc_timing);
491 
492 bool dcn10_link_encoder_validate_output_with_stream(
493 	struct link_encoder *enc,
494 	const struct dc_stream_state *stream);
495 
496 /****************** HW programming ************************/
497 
498 /* initialize HW */  /* why do we initialze aux in here? */
499 void dcn10_link_encoder_hw_init(struct link_encoder *enc);
500 
501 void dcn10_link_encoder_destroy(struct link_encoder **enc);
502 
503 /* program DIG_MODE in DIG_BE */
504 /* TODO can this be combined with enable_output? */
505 void dcn10_link_encoder_setup(
506 	struct link_encoder *enc,
507 	enum signal_type signal);
508 
509 void enc1_configure_encoder(
510 	struct dcn10_link_encoder *enc10,
511 	const struct dc_link_settings *link_settings);
512 
513 /* enables TMDS PHY output */
514 /* TODO: still need depth or just pass in adjusted pixel clock? */
515 void dcn10_link_encoder_enable_tmds_output(
516 	struct link_encoder *enc,
517 	enum clock_source_id clock_source,
518 	enum dc_color_depth color_depth,
519 	enum signal_type signal,
520 	uint32_t pixel_clock);
521 
522 /* enables DP PHY output */
523 void dcn10_link_encoder_enable_dp_output(
524 	struct link_encoder *enc,
525 	const struct dc_link_settings *link_settings,
526 	enum clock_source_id clock_source);
527 
528 /* enables DP PHY output in MST mode */
529 void dcn10_link_encoder_enable_dp_mst_output(
530 	struct link_encoder *enc,
531 	const struct dc_link_settings *link_settings,
532 	enum clock_source_id clock_source);
533 
534 /* disable PHY output */
535 void dcn10_link_encoder_disable_output(
536 	struct link_encoder *enc,
537 	enum signal_type signal);
538 
539 /* set DP lane settings */
540 void dcn10_link_encoder_dp_set_lane_settings(
541 	struct link_encoder *enc,
542 	const struct link_training_settings *link_settings);
543 
544 void dcn10_link_encoder_dp_set_phy_pattern(
545 	struct link_encoder *enc,
546 	const struct encoder_set_dp_phy_pattern_param *param);
547 
548 /* programs DP MST VC payload allocation */
549 void dcn10_link_encoder_update_mst_stream_allocation_table(
550 	struct link_encoder *enc,
551 	const struct link_mst_stream_allocation_table *table);
552 
553 void dcn10_link_encoder_connect_dig_be_to_fe(
554 	struct link_encoder *enc,
555 	enum engine_id engine,
556 	bool connect);
557 
558 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
559 	struct link_encoder *enc,
560 	uint32_t index);
561 
562 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
563 
564 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
565 
566 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
567 			bool exit_link_training_required);
568 
569 void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
570 			unsigned int sdp_transmit_line_num_deadline);
571 
572 bool dcn10_is_dig_enabled(struct link_encoder *enc);
573 
574 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
575 
576 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
577 
578 enum signal_type dcn10_get_dig_mode(
579 	struct link_encoder *enc);
580 #endif /* __DC_LINK_ENCODER__DCN10_H__ */
581