xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/dce_audio.h (revision 70e1a2aaf42c498c8e063006ff875b4882a65c5e)
1 /*	$NetBSD: dce_audio.h,v 1.5 2021/12/19 12:22:48 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2012-15 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: AMD
25  *
26  */
27 #ifndef __DAL_AUDIO_DCE_110_H__
28 #define __DAL_AUDIO_DCE_110_H__
29 
30 #include "hw/audio.h"
31 
32 #define AUD_COMMON_REG_LIST(id)\
33 	SRI(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),\
34 	SRI(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),\
35 	SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
36 	SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
37 	SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
38 	SR(DCCG_AUDIO_DTO_SOURCE),\
39 	SR(DCCG_AUDIO_DTO0_MODULE),\
40 	SR(DCCG_AUDIO_DTO0_PHASE),\
41 	SR(DCCG_AUDIO_DTO1_MODULE),\
42 	SR(DCCG_AUDIO_DTO1_PHASE)
43 
44 
45  /* set field name */
46 #define SF(reg_name, field_name, post_fix)\
47 	.field_name = reg_name ## __ ## field_name ## post_fix
48 
49 
50 #define AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)\
51 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
52 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
53 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
54 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
55 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
56 		SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
57 		SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
58 		SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
59 		SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
60 		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
61 		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
62 		SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
63 
64 #define AUD_COMMON_MASK_SH_LIST(mask_sh)\
65 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh),\
66 		SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
67 		SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
68 
69 
70 struct dce_audio_registers {
71 	uint32_t AZALIA_F0_CODEC_ENDPOINT_INDEX;
72 	uint32_t AZALIA_F0_CODEC_ENDPOINT_DATA;
73 
74 	uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS;
75 	uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
76 	uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
77 
78 	uint32_t DCCG_AUDIO_DTO_SOURCE;
79 	uint32_t DCCG_AUDIO_DTO0_MODULE;
80 	uint32_t DCCG_AUDIO_DTO0_PHASE;
81 	uint32_t DCCG_AUDIO_DTO1_MODULE;
82 	uint32_t DCCG_AUDIO_DTO1_PHASE;
83 
84 	uint32_t AUDIO_RATE_CAPABILITIES;
85 };
86 
87 struct dce_audio_shift {
88 	uint8_t AZALIA_ENDPOINT_REG_INDEX;
89 	uint8_t AZALIA_ENDPOINT_REG_DATA;
90 
91 	uint8_t AUDIO_RATE_CAPABILITIES;
92 	uint8_t CLKSTOP;
93 	uint8_t EPSS;
94 
95 	uint8_t DCCG_AUDIO_DTO0_SOURCE_SEL;
96 	uint8_t DCCG_AUDIO_DTO_SEL;
97 	uint8_t DCCG_AUDIO_DTO0_MODULE;
98 	uint8_t DCCG_AUDIO_DTO0_PHASE;
99 	uint8_t DCCG_AUDIO_DTO1_MODULE;
100 	uint8_t DCCG_AUDIO_DTO1_PHASE;
101 	uint8_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
102 	uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
103 	uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
104 };
105 
106 struct dce_audio_mask {
107 	uint32_t AZALIA_ENDPOINT_REG_INDEX;
108 	uint32_t AZALIA_ENDPOINT_REG_DATA;
109 
110 	uint32_t AUDIO_RATE_CAPABILITIES;
111 	uint32_t CLKSTOP;
112 	uint32_t EPSS;
113 
114 	uint32_t DCCG_AUDIO_DTO0_SOURCE_SEL;
115 	uint32_t DCCG_AUDIO_DTO_SEL;
116 	uint32_t DCCG_AUDIO_DTO0_MODULE;
117 	uint32_t DCCG_AUDIO_DTO0_PHASE;
118 	uint32_t DCCG_AUDIO_DTO1_MODULE;
119 	uint32_t DCCG_AUDIO_DTO1_PHASE;
120 	uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
121 	uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
122 	uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
123 
124 };
125 
126 struct dce_audio {
127 	struct audio base;
128 	const struct dce_audio_registers *regs;
129 	const struct dce_audio_shift *shifts;
130 	const struct dce_audio_mask *masks;
131 };
132 
133 struct audio *dce_audio_create(
134 		struct dc_context *ctx,
135 		unsigned int inst,
136 		const struct dce_audio_registers *reg,
137 		const struct dce_audio_shift *shifts,
138 		const struct dce_audio_mask *masks);
139 
140 void dce_aud_destroy(struct audio **audio);
141 
142 void dce_aud_hw_init(struct audio *audio);
143 
144 void dce_aud_az_enable(struct audio *audio);
145 void dce_aud_az_disable(struct audio *audio);
146 
147 void dce_aud_az_configure(struct audio *audio,
148 	enum signal_type signal,
149 	const struct audio_crtc_info *crtc_info,
150 	const struct audio_info *audio_info);
151 
152 void dce_aud_wall_dto_setup(struct audio *audio,
153 	enum signal_type signal,
154 	const struct audio_crtc_info *crtc_info,
155 	const struct audio_pll_info *pll_info);
156 
157 #endif   /*__DAL_AUDIO_DCE_110_H__*/
158