1 /* $NetBSD: dce_clock_source.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* Copyright 2012-15 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DC_CLOCK_SOURCE_DCE_H__ 28 #define __DC_CLOCK_SOURCE_DCE_H__ 29 30 #include "../inc/clock_source.h" 31 32 #define TO_DCE110_CLK_SRC(clk_src)\ 33 container_of(clk_src, struct dce110_clk_src, base) 34 35 #define CS_COMMON_REG_LIST_DCE_100_110(id) \ 36 SRI(RESYNC_CNTL, PIXCLK, id), \ 37 SRI(PLL_CNTL, BPHYC_PLL, id) 38 39 #define CS_COMMON_REG_LIST_DCE_80(id) \ 40 SRI(RESYNC_CNTL, PIXCLK, id), \ 41 SRI(PLL_CNTL, DCCG_PLL, id) 42 43 #define CS_COMMON_REG_LIST_DCE_112(id) \ 44 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) 45 46 47 #define CS_SF(reg_name, field_name, post_fix)\ 48 .field_name = reg_name ## __ ## field_name ## post_fix 49 50 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 51 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ 52 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ 53 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ 54 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) 55 56 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 57 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 58 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) 59 60 #define CS_COMMON_REG_LIST_DCN2_0(index, pllid) \ 61 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 62 SRII(PHASE, DP_DTO, 0),\ 63 SRII(PHASE, DP_DTO, 1),\ 64 SRII(PHASE, DP_DTO, 2),\ 65 SRII(PHASE, DP_DTO, 3),\ 66 SRII(PHASE, DP_DTO, 4),\ 67 SRII(PHASE, DP_DTO, 5),\ 68 SRII(MODULO, DP_DTO, 0),\ 69 SRII(MODULO, DP_DTO, 1),\ 70 SRII(MODULO, DP_DTO, 2),\ 71 SRII(MODULO, DP_DTO, 3),\ 72 SRII(MODULO, DP_DTO, 4),\ 73 SRII(MODULO, DP_DTO, 5),\ 74 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 75 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 76 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 77 SRII(PIXEL_RATE_CNTL, OTG, 3),\ 78 SRII(PIXEL_RATE_CNTL, OTG, 4),\ 79 SRII(PIXEL_RATE_CNTL, OTG, 5) 80 81 #define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ 82 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 83 SRII(PHASE, DP_DTO, 0),\ 84 SRII(PHASE, DP_DTO, 1),\ 85 SRII(PHASE, DP_DTO, 2),\ 86 SRII(PHASE, DP_DTO, 3),\ 87 SRII(MODULO, DP_DTO, 0),\ 88 SRII(MODULO, DP_DTO, 1),\ 89 SRII(MODULO, DP_DTO, 2),\ 90 SRII(MODULO, DP_DTO, 3),\ 91 SRII(PIXEL_RATE_CNTL, OTG, 0),\ 92 SRII(PIXEL_RATE_CNTL, OTG, 1),\ 93 SRII(PIXEL_RATE_CNTL, OTG, 2),\ 94 SRII(PIXEL_RATE_CNTL, OTG, 3) 95 96 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ 97 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 98 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 99 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 100 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 101 102 #if defined(CONFIG_DRM_AMD_DC_DCN) 103 104 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ 105 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 106 SRII(PHASE, DP_DTO, 0),\ 107 SRII(PHASE, DP_DTO, 1),\ 108 SRII(PHASE, DP_DTO, 2),\ 109 SRII(PHASE, DP_DTO, 3),\ 110 SRII(MODULO, DP_DTO, 0),\ 111 SRII(MODULO, DP_DTO, 1),\ 112 SRII(MODULO, DP_DTO, 2),\ 113 SRII(MODULO, DP_DTO, 3),\ 114 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 115 SRII(PIXEL_RATE_CNTL, OTG, 1), \ 116 SRII(PIXEL_RATE_CNTL, OTG, 2), \ 117 SRII(PIXEL_RATE_CNTL, OTG, 3) 118 119 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 120 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 121 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 122 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 123 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 124 125 #endif 126 127 #define CS_REG_FIELD_LIST(type) \ 128 type PLL_REF_DIV_SRC; \ 129 type DCCG_DEEP_COLOR_CNTL1; \ 130 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \ 131 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ 132 type PLL_POST_DIV_PIXCLK; \ 133 type PLL_REF_DIV; \ 134 type DP_DTO0_PHASE; \ 135 type DP_DTO0_MODULO; \ 136 type DP_DTO0_ENABLE; 137 138 struct dce110_clk_src_shift { 139 CS_REG_FIELD_LIST(uint8_t) 140 }; 141 142 struct dce110_clk_src_mask{ 143 CS_REG_FIELD_LIST(uint32_t) 144 }; 145 146 struct dce110_clk_src_regs { 147 uint32_t RESYNC_CNTL; 148 uint32_t PIXCLK_RESYNC_CNTL; 149 uint32_t PLL_CNTL; 150 151 /* below are for DTO. 152 * todo: should probably use different struct to not waste space 153 */ 154 uint32_t PHASE[MAX_PIPES]; 155 uint32_t MODULO[MAX_PIPES]; 156 uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; 157 }; 158 159 struct dce110_clk_src { 160 struct clock_source base; 161 const struct dce110_clk_src_regs *regs; 162 const struct dce110_clk_src_mask *cs_mask; 163 const struct dce110_clk_src_shift *cs_shift; 164 struct dc_bios *bios; 165 166 struct spread_spectrum_data *dp_ss_params; 167 uint32_t dp_ss_params_cnt; 168 struct spread_spectrum_data *hdmi_ss_params; 169 uint32_t hdmi_ss_params_cnt; 170 struct spread_spectrum_data *dvi_ss_params; 171 uint32_t dvi_ss_params_cnt; 172 struct spread_spectrum_data *lvds_ss_params; 173 uint32_t lvds_ss_params_cnt; 174 175 uint32_t ext_clk_khz; 176 uint32_t ref_freq_khz; 177 178 struct calc_pll_clock_source calc_pll; 179 struct calc_pll_clock_source calc_pll_hdmi; 180 }; 181 182 bool dce110_clk_src_construct( 183 struct dce110_clk_src *clk_src, 184 struct dc_context *ctx, 185 struct dc_bios *bios, 186 enum clock_source_id, 187 const struct dce110_clk_src_regs *regs, 188 const struct dce110_clk_src_shift *cs_shift, 189 const struct dce110_clk_src_mask *cs_mask); 190 191 bool dce112_clk_src_construct( 192 struct dce110_clk_src *clk_src, 193 struct dc_context *ctx, 194 struct dc_bios *bios, 195 enum clock_source_id id, 196 const struct dce110_clk_src_regs *regs, 197 const struct dce110_clk_src_shift *cs_shift, 198 const struct dce110_clk_src_mask *cs_mask); 199 200 bool dcn20_clk_src_construct( 201 struct dce110_clk_src *clk_src, 202 struct dc_context *ctx, 203 struct dc_bios *bios, 204 enum clock_source_id id, 205 const struct dce110_clk_src_regs *regs, 206 const struct dce110_clk_src_shift *cs_shift, 207 const struct dce110_clk_src_mask *cs_mask); 208 209 #endif 210