xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/dc_link_dp.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: dc_link_dp.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2015 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: AMD
25  *
26  */
27 
28 #ifndef __DC_LINK_DP_H__
29 #define __DC_LINK_DP_H__
30 
31 #define LINK_TRAINING_ATTEMPTS 4
32 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
33 #define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 3200 /*us*/
34 #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
35 
36 struct dc_link;
37 struct dc_stream_state;
38 struct dc_link_settings;
39 
40 bool dp_verify_link_cap(
41 	struct dc_link *link,
42 	struct dc_link_settings *known_limit_link_setting,
43 	int *fail_count);
44 
45 bool dp_verify_link_cap_with_retries(
46 	struct dc_link *link,
47 	struct dc_link_settings *known_limit_link_setting,
48 	int attempts);
49 
50 bool dp_verify_mst_link_cap(
51 	struct dc_link *link);
52 
53 bool dp_validate_mode_timing(
54 	struct dc_link *link,
55 	const struct dc_crtc_timing *timing);
56 
57 void decide_link_settings(
58 	struct dc_stream_state *stream,
59 	struct dc_link_settings *link_setting);
60 
61 bool perform_link_training_with_retries(
62 	const struct dc_link_settings *link_setting,
63 	bool skip_video_pattern,
64 	int attempts,
65 	struct pipe_ctx *pipe_ctx,
66 	enum signal_type signal);
67 
68 bool is_mst_supported(struct dc_link *link);
69 
70 bool detect_dp_sink_caps(struct dc_link *link);
71 
72 void detect_edp_sink_caps(struct dc_link *link);
73 
74 bool is_dp_active_dongle(const struct dc_link *link);
75 
76 void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
77 
78 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
79 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
80 
81 bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
82 
83 void dp_set_fec_ready(struct dc_link *link, bool ready);
84 void dp_set_fec_enable(struct dc_link *link, bool enable);
85 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
86 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
87 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
88 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
89 
90 #endif /* __DC_LINK_DP_H__ */
91