1 /* $NetBSD: cv3dpb.c,v 1.7 2023/12/20 00:40:42 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Radoslaw Kujawa.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/types.h>
33 #include <sys/param.h>
34 #include <sys/time.h>
35 #include <sys/systm.h>
36 #include <sys/errno.h>
37 #include <sys/device.h>
38
39 #include <uvm/uvm_extern.h>
40
41 #include <machine/bus.h>
42 #include <machine/cpu.h>
43
44 #include <amiga/dev/zbusvar.h>
45 #include <amiga/pci/cv3dpbreg.h>
46 #include <amiga/pci/cv3dpbvar.h>
47
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/pci/pcidevs.h>
51 #include <dev/pci/pciconf.h>
52
53 /* Zorro IDs */
54 #define ZORRO_MANID_P5 8512
55 #define ZORRO_PRODID_CV643D_Z3 67 /* CV64/3D on Z3 bus */
56
57 static int cv3dpb_match(device_t, cfdata_t, void *);
58 static void cv3dpb_attach(device_t, device_t, void *);
59 pcireg_t cv3dpb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int);
60 void cv3dpb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
61 int cv3dpb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno);
62 int cv3dpb_pci_intr_map(const struct pci_attach_args *pa,
63 pci_intr_handle_t *ihp);
64 static bool cv3dpb_bus_map(struct cv3dpb_softc *sc);
65
66 CFATTACH_DECL_NEW(cv3dpb, sizeof(struct cv3dpb_softc),
67 cv3dpb_match, cv3dpb_attach, NULL, NULL);
68
69 static int
cv3dpb_match(device_t parent,cfdata_t cf,void * aux)70 cv3dpb_match(device_t parent, cfdata_t cf, void *aux)
71 {
72 struct zbus_args *zap;
73
74 zap = aux;
75
76 if (zap->manid != ZORRO_MANID_P5)
77 return 0;
78
79 if (zap->prodid != ZORRO_PRODID_CV643D_Z3)
80 return 0;
81
82 #ifdef P5PB_DEBUG
83 aprint_normal("cv3dpb matched by Zorro ID %d, %d\n", zap->manid,
84 zap->prodid);
85 #endif
86
87 return 10;
88 }
89
90
91 static void
cv3dpb_attach(device_t parent,device_t self,void * aux)92 cv3dpb_attach(device_t parent, device_t self, void *aux)
93 {
94 struct cv3dpb_softc *sc;
95 struct pcibus_attach_args pba;
96 struct zbus_args *zap;
97
98 sc = device_private(self);
99 pci_chipset_tag_t pc = &sc->apc;
100 sc->sc_dev = self;
101 zap = aux;
102
103 sc->ba = zap->va;
104
105 if(!(cv3dpb_bus_map(sc))) {
106 aprint_error_dev(self,
107 "couldn't map PCI configuration registers\n");
108 return;
109 }
110
111 aprint_normal(": CyberVision 64/3D PCI bridge\n");
112
113 #ifdef P5PB_DEBUG
114 aprint_normal("cv3dpb: mapped %x -> %x, %x -> %x\n, %x -> %x\n",
115 P5BUS_PCI_CONF_BASE, sc->pci_conf_area.base,
116 P5BUS_PCI_IO_BASE, sc->pci_io_area.base,
117 P5BUS_PCI_MEM_BASE, sc->pci_mem_area.base );
118 #endif
119
120 /* Initialize the PCI chipset tag. */
121 sc->apc.pc_conf_v = (void*) pc;
122 sc->apc.pc_bus_maxdevs = cv3dpb_pci_bus_maxdevs;
123 sc->apc.pc_make_tag = amiga_pci_make_tag;
124 sc->apc.pc_decompose_tag = amiga_pci_decompose_tag;
125 sc->apc.pc_conf_read = cv3dpb_pci_conf_read;
126 sc->apc.pc_conf_write = cv3dpb_pci_conf_write;
127 //sc->apc.pc_attach_hook = cv3dpb_pci_attach_hook;
128
129 sc->apc.pc_intr_map = cv3dpb_pci_intr_map;
130 sc->apc.pc_intr_string = amiga_pci_intr_string;
131 sc->apc.pc_intr_establish = amiga_pci_intr_establish;
132 sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish;
133
134 pba.pba_iot = &(sc->pci_io_area);
135 pba.pba_memt = &(sc->pci_mem_area);
136 pba.pba_dmat = NULL;
137 pba.pba_dmat64 = NULL;
138 pba.pba_pc = pc;
139 pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY;
140 pba.pba_bus = 0;
141 pba.pba_bridgetag = NULL;
142
143 config_found(self, &pba, pcibusprint, CFARGS_NONE);
144 }
145
146 pcireg_t
cv3dpb_pci_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)147 cv3dpb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
148 {
149 uint32_t data;
150 uint32_t bus, dev, func;
151
152 if ((unsigned int)reg >= PCI_CONF_SIZE)
153 return (pcireg_t) -1;
154
155 pci_decompose_tag(pc, tag, &bus, &dev, &func);
156
157 data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah,
158 (func<<5) + reg);
159 #ifdef P5PB_DEBUG
160 aprint_normal("cv3dpb conf read va: %lx, bus: %d, dev: %d, "
161 "func: %d, reg: %d -r-> data %x\n",
162 pc->pci_conf_datah, bus, dev, func, reg, data);
163 #endif
164 return data;
165 }
166
167 void
cv3dpb_pci_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t val)168 cv3dpb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val)
169 {
170 uint32_t bus, dev, func;
171
172 if ((unsigned int)reg >= PCI_CONF_SIZE)
173 return;
174
175 pci_decompose_tag(pc, tag, &bus, &dev, &func);
176
177 bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah,
178 (func << 5) + reg, val);
179 #ifdef P5PB_DEBUG
180 aprint_normal("cv3dpb conf write va: %lx, bus: %d, dev: %d, "
181 "func: %d, reg: %d -w-> data %x\n",
182 pc->pci_conf_datah, bus, dev, func, reg, val);
183 #endif
184
185 }
186
187 /* There can be only one. */
188 int
cv3dpb_pci_bus_maxdevs(pci_chipset_tag_t pc,int busno)189 cv3dpb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
190 {
191 return 1;
192 }
193
194 int
cv3dpb_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)195 cv3dpb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
196 {
197 /* TODO: add sanity checking */
198
199 *ihp = 2; /* XXX: untested */
200 return 0;
201 }
202
203 bool
cv3dpb_bus_map(struct cv3dpb_softc * sc)204 cv3dpb_bus_map(struct cv3dpb_softc *sc) {
205 #ifdef P5PB_DEBUG
206 aprint_normal("cv3dpb: cv3dpb_bus_map called, ba = %x\n",
207 (bus_addr_t) sc->ba);
208 #endif /* P5PB_DEBUG */
209
210 sc->pci_conf_area.base = (bus_addr_t) sc->ba + CV643D_PCI_CONF_BASE;
211 sc->pci_conf_area.absm = &amiga_bus_stride_1;
212
213 sc->pci_mem_area.base = (bus_addr_t) sc->ba + CV643D_PCI_MEM_BASE;
214 sc->pci_mem_area.absm = &amiga_bus_stride_1;
215
216 sc->pci_io_area.base = (bus_addr_t) sc->ba + CV643D_PCI_IO_BASE;
217 sc->pci_io_area.absm = &amiga_bus_stride_1;
218
219 sc->apc.pci_conf_datat = &(sc->pci_conf_area);
220
221 if (bus_space_map(sc->apc.pci_conf_datat, 0,
222 CV643D_PCI_CONF_SIZE, 0, &sc->apc.pci_conf_datah))
223 return false;
224
225 return true;
226 }
227
228