1 /* $NetBSD: tegra.h,v 1.3 2021/12/18 23:45:33 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 #ifndef __NVKM_DEVICE_TEGRA_H__ 5 #define __NVKM_DEVICE_TEGRA_H__ 6 #include <core/device.h> 7 #include <core/mm.h> 8 9 struct nvkm_device_tegra { 10 const struct nvkm_device_tegra_func *func; 11 struct nvkm_device device; 12 struct platform_device *pdev; 13 int irq; 14 15 struct reset_control *rst; 16 struct clk *clk; 17 struct clk *clk_ref; 18 struct clk *clk_pwr; 19 20 struct regulator *vdd; 21 22 struct { 23 /* 24 * Protects accesses to mm from subsystems 25 */ 26 struct mutex mutex; 27 28 struct nvkm_mm mm; 29 struct iommu_domain *domain; 30 unsigned long pgshift; 31 } iommu; 32 33 int gpu_speedo; 34 int gpu_speedo_id; 35 }; 36 37 struct nvkm_device_tegra_func { 38 /* 39 * If an IOMMU is used, indicates which address bit will trigger a 40 * IOMMU translation when set (when this bit is not set, IOMMU is 41 * bypassed). A value of 0 means an IOMMU is never used. 42 */ 43 u8 iommu_bit; 44 /* 45 * Whether the chip requires a reference clock 46 */ 47 bool require_ref_clk; 48 /* 49 * Whether the chip requires the VDD regulator 50 */ 51 bool require_vdd; 52 }; 53 54 int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *, 55 struct platform_device *, 56 const char *cfg, const char *dbg, 57 bool detect, bool mmio, u64 subdev_mask, 58 struct nvkm_device **); 59 #endif 60