1 /* $NetBSD: cia_swiz_bus_mem.c,v 1.20 2023/12/04 00:32:10 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(1, "$NetBSD: cia_swiz_bus_mem.c,v 1.20 2023/12/04 00:32:10 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/syslog.h> 37 #include <sys/device.h> 38 39 #include <sys/bus.h> 40 41 #include <alpha/pci/ciareg.h> 42 #include <alpha/pci/ciavar.h> 43 44 #define CHIP cia_swiz 45 46 #define CHIP_D_MEM_ARENA(v) (((struct cia_config *)(v))->cc_d_mem_arena) 47 #define CHIP_S_MEM_ARENA(v) (((struct cia_config *)(v))->cc_s_mem_arena) 48 49 /* Dense region 1 */ 50 #define CHIP_D_MEM_W1_BUS_START(v) 0x00000000UL 51 #define CHIP_D_MEM_W1_BUS_END(v) 0xffffffffUL 52 #define CHIP_D_MEM_W1_SYS_START(v) CIA_PCI_DENSE 53 #define CHIP_D_MEM_W1_SYS_END(v) (CIA_PCI_DENSE + 0xffffffffUL) 54 55 /* Sparse region 1 */ 56 #define CHIP_S_MEM_W1_BUS_START(v) \ 57 HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem) 58 #define CHIP_S_MEM_W1_BUS_END(v) \ 59 (CHIP_S_MEM_W1_BUS_START(v) + HAE_MEM_REG1_MASK) 60 #define CHIP_S_MEM_W1_SYS_START(v) \ 61 CIA_PCI_SMEM1 62 #define CHIP_S_MEM_W1_SYS_END(v) \ 63 (CIA_PCI_SMEM1 + ((HAE_MEM_REG1_MASK + 1) << 5) - 1) 64 65 /* Sparse region 2 */ 66 #define CHIP_S_MEM_W2_BUS_START(v) \ 67 HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem) 68 #define CHIP_S_MEM_W2_BUS_END(v) \ 69 (CHIP_S_MEM_W2_BUS_START(v) + HAE_MEM_REG2_MASK) 70 #define CHIP_S_MEM_W2_SYS_START(v) \ 71 CIA_PCI_SMEM2 72 #define CHIP_S_MEM_W2_SYS_END(v) \ 73 (CIA_PCI_SMEM2 + ((HAE_MEM_REG2_MASK + 1) << 5) - 1) 74 75 /* Sparse region 3 */ 76 #define CHIP_S_MEM_W3_BUS_START(v) \ 77 HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem) 78 #define CHIP_S_MEM_W3_BUS_END(v) \ 79 (CHIP_S_MEM_W3_BUS_START(v) + HAE_MEM_REG3_MASK) 80 #define CHIP_S_MEM_W3_SYS_START(v) \ 81 CIA_PCI_SMEM3 82 #define CHIP_S_MEM_W3_SYS_END(v) \ 83 (CIA_PCI_SMEM3 + ((HAE_MEM_REG3_MASK + 1) << 5) - 1) 84 85 #include <alpha/pci/pci_swiz_bus_mem_chipdep.c> 86