1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -verify-machineinstrs \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 4; RUN: -check-prefix=P7BE 5; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 7; RUN: -check-prefix=P8LE 8; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \ 9; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 10; RUN: -check-prefix=P9LE 11 12; FIXME: P7BE for i128 looks wrong. 13define <1 x i128> @One1i128() { 14; P7BE-LABEL: One1i128: 15; P7BE: # %bb.0: # %entry 16; P7BE-NEXT: li r3, -1 17; P7BE-NEXT: li r4, -1 18; P7BE-NEXT: blr 19; 20; P8LE-LABEL: One1i128: 21; P8LE: # %bb.0: # %entry 22; P8LE-NEXT: xxleqv vs34, vs34, vs34 23; P8LE-NEXT: blr 24; 25; P9LE-LABEL: One1i128: 26; P9LE: # %bb.0: # %entry 27; P9LE-NEXT: xxleqv vs34, vs34, vs34 28; P9LE-NEXT: blr 29entry: 30 ret <1 x i128> <i128 -1> 31} 32 33define <2 x i64> @One2i64() { 34; P7BE-LABEL: One2i64: 35; P7BE: # %bb.0: # %entry 36; P7BE-NEXT: vspltisb v2, -1 37; P7BE-NEXT: blr 38; 39; P8LE-LABEL: One2i64: 40; P8LE: # %bb.0: # %entry 41; P8LE-NEXT: xxleqv vs34, vs34, vs34 42; P8LE-NEXT: blr 43; 44; P9LE-LABEL: One2i64: 45; P9LE: # %bb.0: # %entry 46; P9LE-NEXT: xxleqv vs34, vs34, vs34 47; P9LE-NEXT: blr 48entry: 49 ret <2 x i64> <i64 -1, i64 -1> 50} 51 52define <4 x i32> @One4i32() { 53; P7BE-LABEL: One4i32: 54; P7BE: # %bb.0: # %entry 55; P7BE-NEXT: vspltisb v2, -1 56; P7BE-NEXT: blr 57; 58; P8LE-LABEL: One4i32: 59; P8LE: # %bb.0: # %entry 60; P8LE-NEXT: xxleqv vs34, vs34, vs34 61; P8LE-NEXT: blr 62; 63; P9LE-LABEL: One4i32: 64; P9LE: # %bb.0: # %entry 65; P9LE-NEXT: xxleqv vs34, vs34, vs34 66; P9LE-NEXT: blr 67entry: 68 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 69} 70 71define <8 x i16> @One8i16() { 72; P7BE-LABEL: One8i16: 73; P7BE: # %bb.0: # %entry 74; P7BE-NEXT: vspltisb v2, -1 75; P7BE-NEXT: blr 76; 77; P8LE-LABEL: One8i16: 78; P8LE: # %bb.0: # %entry 79; P8LE-NEXT: xxleqv vs34, vs34, vs34 80; P8LE-NEXT: blr 81; 82; P9LE-LABEL: One8i16: 83; P9LE: # %bb.0: # %entry 84; P9LE-NEXT: xxleqv vs34, vs34, vs34 85; P9LE-NEXT: blr 86entry: 87 ret <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 88} 89 90define <16 x i8> @One16i8() { 91; P7BE-LABEL: One16i8: 92; P7BE: # %bb.0: # %entry 93; P7BE-NEXT: vspltisb v2, -1 94; P7BE-NEXT: blr 95; 96; P8LE-LABEL: One16i8: 97; P8LE: # %bb.0: # %entry 98; P8LE-NEXT: xxleqv vs34, vs34, vs34 99; P8LE-NEXT: blr 100; 101; P9LE-LABEL: One16i8: 102; P9LE: # %bb.0: # %entry 103; P9LE-NEXT: xxleqv vs34, vs34, vs34 104; P9LE-NEXT: blr 105entry: 106 ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 107} 108