1 /* $NetBSD: becc.c,v 1.18 2021/08/07 16:18:46 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Autoconfiguration support for the ADI Engineering Big Endian
40 * Companion Chip.
41 */
42
43 #include <sys/cdefs.h>
44 __KERNEL_RCSID(0, "$NetBSD: becc.c,v 1.18 2021/08/07 16:18:46 thorpej Exp $");
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/device.h>
49
50 #define _ARM32_BUS_DMA_PRIVATE
51 #include <sys/bus.h>
52
53 #include <arm/xscale/i80200reg.h>
54 #include <arm/xscale/beccreg.h>
55 #include <arm/xscale/beccvar.h>
56
57 /*
58 * Virtual address at which the BECC is mapped. This is filled in
59 * by machine-dependent code.
60 */
61 vaddr_t becc_vaddr;
62
63 /*
64 * BECC revision number. This is initialized by early bootstrap code.
65 */
66 int becc_rev;
67 const char *becc_revisions[] = {
68 "<= 7",
69 "8",
70 ">= 9",
71 };
72
73 /*
74 * There can be only one BECC, so we keep a global pointer to
75 * the softc, so board-specific code can use features of the
76 * BECC without having to have a handle on the softc itself.
77 */
78 struct becc_softc *becc_softc;
79
80 static int becc_search(device_t, cfdata_t, const int *, void *);
81 static int becc_print(void *, const char *);
82
83 static void becc_pci_dma_init(struct becc_softc *);
84 static void becc_local_dma_init(struct becc_softc *);
85
86 /*
87 * becc_attach:
88 *
89 * Board-independent attach routine for the BECC.
90 */
91 void
becc_attach(struct becc_softc * sc)92 becc_attach(struct becc_softc *sc)
93 {
94 struct pcibus_attach_args pba;
95 uint32_t reg;
96
97 becc_softc = sc;
98
99 /*
100 * Set the AF bit in the BCUMOD since the BECC will honor it.
101 * This allows the BECC to return the requested 4-byte word
102 * first when filling a cache line.
103 */
104 __asm volatile("mrc p13, 0, %0, c1, c1, 0" : "=r" (reg));
105 __asm volatile("mcr p13, 0, %0, c1, c1, 0" : : "r" (reg | BCUMOD_AF));
106
107 /*
108 * Program the address windows of the PCI core. Note
109 * that PCI master and target cycles must be disabled
110 * while we configure the windows.
111 */
112 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);
113 reg &= ~(PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE);
114 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg);
115
116 /*
117 * Program the two inbound PCI memory windows.
118 */
119 becc_pcicore_write(sc, PCI_MAPREG_START + 0,
120 sc->sc_iwin[0].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT |
121 PCI_MAPREG_MEM_PREFETCHABLE_MASK);
122 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 0);
123 BECC_CSR_WRITE(BECC_PSTR0, sc->sc_iwin[0].iwin_xlate & PSTRx_ADDRMASK);
124
125 becc_pcicore_write(sc, PCI_MAPREG_START + 4,
126 sc->sc_iwin[1].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT |
127 PCI_MAPREG_MEM_PREFETCHABLE_MASK);
128 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 4);
129 BECC_CSR_WRITE(BECC_PSTR1, sc->sc_iwin[1].iwin_xlate & PSTRx_ADDRMASK);
130
131 /*
132 * ...and the third on v8 and later.
133 */
134 if (becc_rev >= BECC_REV_V8) {
135 becc_pcicore_write(sc, PCI_MAPREG_START + 8,
136 sc->sc_iwin[2].iwin_base | PCI_MAPREG_MEM_TYPE_32BIT |
137 PCI_MAPREG_MEM_PREFETCHABLE_MASK);
138 reg = becc_pcicore_read(sc, PCI_MAPREG_START + 8);
139 BECC_CSR_WRITE(BECC_PSTR2,
140 sc->sc_iwin[2].iwin_xlate & PSTR2_ADDRMASK);
141 }
142
143 /*
144 * Program the two outbound PCI memory windows.
145 * NOTE: WE DO NOT BYTE-SWAP OUTBOUND WINDOWS IN BIG-ENDIAN
146 * MODE. I know this seems counter-intuitive, but that's
147 * how it is.
148 *
149 * There's a third window on v9 and later, but we don't
150 * use it for anything; program it anyway, just to be
151 * safe.
152 */
153 BECC_CSR_WRITE(BECC_POMR1, sc->sc_owin_xlate[0] /* | POMRx_F32 */);
154 BECC_CSR_WRITE(BECC_POMR2, sc->sc_owin_xlate[1] /* | POMRx_F32 */);
155
156 if (becc_rev >= BECC_REV_V9)
157 BECC_CSR_WRITE(BECC_POMR3,
158 sc->sc_owin_xlate[2] /* | POMRx_F32 */);
159
160 /*
161 * Program the PCI I/O window. See note above about byte-swapping.
162 *
163 * XXX What about STREAM transfers?
164 */
165 BECC_CSR_WRITE(BECC_POIR, sc->sc_ioout_xlate);
166
167 /*
168 * Configure PCI configuration cycle access.
169 */
170 BECC_CSR_WRITE(BECC_POCR, 0);
171
172 /*
173 * ...and now reenable PCI access.
174 */
175 reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);
176 reg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
177 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
178 becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG, reg);
179
180 /* Initialize the bus space tags. */
181 becc_io_bs_init(&sc->sc_pci_iot, sc);
182 becc_mem_bs_init(&sc->sc_pci_memt, sc);
183
184 /* Initialize the PCI chipset tag. */
185 becc_pci_init(&sc->sc_pci_chipset, sc);
186
187 /* Initialize the DMA tags. */
188 becc_pci_dma_init(sc);
189 becc_local_dma_init(sc);
190
191 /*
192 * Attach any on-chip peripherals. We used indirect config, since
193 * the BECC is a soft-core with a variety of peripherals, depending
194 * on configuration.
195 */
196 config_search(sc->sc_dev, NULL,
197 CFARGS(.search = becc_search,
198 .iattr = "becc"));
199
200 /*
201 * Attach the PCI bus.
202 */
203 pba.pba_iot = &sc->sc_pci_iot;
204 pba.pba_memt = &sc->sc_pci_memt;
205 pba.pba_dmat = &sc->sc_pci_dmat;
206 pba.pba_dmat64 = NULL;
207 pba.pba_pc = &sc->sc_pci_chipset;
208 pba.pba_bus = 0;
209 pba.pba_bridgetag = NULL;
210 pba.pba_intrswiz = 0;
211 pba.pba_intrtag = 0;
212 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
213 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
214 config_found(sc->sc_dev, &pba, pcibusprint,
215 CFARGS(.iattr = "pcibus"));
216 }
217
218 /*
219 * becc_search:
220 *
221 * Indirect autoconfiguration glue for BECC.
222 */
223 static int
becc_search(device_t parent,cfdata_t cf,const int * ldesc,void * aux)224 becc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
225 {
226 struct becc_softc *sc = device_private(parent);
227 struct becc_attach_args ba;
228
229 ba.ba_dmat = &sc->sc_local_dmat;
230
231 if (config_probe(parent, cf, &ba))
232 config_attach(parent, cf, &ba, becc_print, CFARGS_NONE);
233
234 return (0);
235 }
236
237 /*
238 * becc_print:
239 *
240 * Autoconfiguration cfprint routine when attaching
241 * to the BECC.
242 */
243 static int
becc_print(void * aux,const char * pnp)244 becc_print(void *aux, const char *pnp)
245 {
246
247 return (UNCONF);
248 }
249
250 /*
251 * becc_pci_dma_init:
252 *
253 * Initialize the PCI DMA tag.
254 */
255 static void
becc_pci_dma_init(struct becc_softc * sc)256 becc_pci_dma_init(struct becc_softc *sc)
257 {
258 bus_dma_tag_t dmat = &sc->sc_pci_dmat;
259 struct arm32_dma_range *dr = sc->sc_pci_dma_range;
260 int i = 0;
261
262 /*
263 * If we have the 128MB window, put it first, since it
264 * will always cover the entire memory range.
265 */
266 if (becc_rev >= BECC_REV_V8) {
267 dr[i].dr_sysbase = sc->sc_iwin[2].iwin_xlate;
268 dr[i].dr_busbase = sc->sc_iwin[2].iwin_base;
269 dr[i].dr_len = (128U * 1024 * 1024);
270 i++;
271 }
272
273 dr[i].dr_sysbase = sc->sc_iwin[0].iwin_xlate;
274 dr[i].dr_busbase = sc->sc_iwin[0].iwin_base;
275 dr[i].dr_len = (32U * 1024 * 1024);
276 i++;
277
278 dr[i].dr_sysbase = sc->sc_iwin[1].iwin_xlate;
279 dr[i].dr_busbase = sc->sc_iwin[1].iwin_base;
280 dr[i].dr_len = (32U * 1024 * 1024);
281 i++;
282
283 dmat->_ranges = dr;
284 dmat->_nranges = i;
285
286 dmat->_dmamap_create = _bus_dmamap_create;
287 dmat->_dmamap_destroy = _bus_dmamap_destroy;
288 dmat->_dmamap_load = _bus_dmamap_load;
289 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
290 dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
291 dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
292 dmat->_dmamap_unload = _bus_dmamap_unload;
293 dmat->_dmamap_sync_pre = _bus_dmamap_sync;
294 dmat->_dmamap_sync_post = NULL;
295
296 dmat->_dmamem_alloc = _bus_dmamem_alloc;
297 dmat->_dmamem_free = _bus_dmamem_free;
298 dmat->_dmamem_map = _bus_dmamem_map;
299 dmat->_dmamem_unmap = _bus_dmamem_unmap;
300 dmat->_dmamem_mmap = _bus_dmamem_mmap;
301
302 dmat->_dmatag_subregion = _bus_dmatag_subregion;
303 dmat->_dmatag_destroy = _bus_dmatag_destroy;
304 }
305
306 /*
307 * becc_local_dma_init:
308 *
309 * Initialize the local DMA tag.
310 */
311 static void
becc_local_dma_init(struct becc_softc * sc)312 becc_local_dma_init(struct becc_softc *sc)
313 {
314 bus_dma_tag_t dmat = &sc->sc_local_dmat;
315
316 dmat->_ranges = NULL;
317 dmat->_nranges = 0;
318
319 dmat->_dmamap_create = _bus_dmamap_create;
320 dmat->_dmamap_destroy = _bus_dmamap_destroy;
321 dmat->_dmamap_load = _bus_dmamap_load;
322 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
323 dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
324 dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
325 dmat->_dmamap_unload = _bus_dmamap_unload;
326 dmat->_dmamap_sync_pre = _bus_dmamap_sync;
327 dmat->_dmamap_sync_post = NULL;
328
329 dmat->_dmamem_alloc = _bus_dmamem_alloc;
330 dmat->_dmamem_free = _bus_dmamem_free;
331 dmat->_dmamem_map = _bus_dmamem_map;
332 dmat->_dmamem_unmap = _bus_dmamem_unmap;
333 dmat->_dmamem_mmap = _bus_dmamem_mmap;
334 }
335
336 uint32_t
becc_pcicore_read(struct becc_softc * sc,bus_addr_t reg)337 becc_pcicore_read(struct becc_softc *sc, bus_addr_t reg)
338 {
339 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg;
340
341 return (*(volatile uint32_t *) va);
342 }
343
344 void
becc_pcicore_write(struct becc_softc * sc,bus_addr_t reg,uint32_t val)345 becc_pcicore_write(struct becc_softc *sc, bus_addr_t reg, uint32_t val)
346 {
347 vaddr_t va = sc->sc_pci_cfg_base | (1U << BECC_IDSEL_BIT) | reg;
348
349 *(volatile uint32_t *) va = val;
350 }
351