1 /* ********************************************************************* 2 * BCM1280/BCM1480 Board Support Package 3 * 4 * PCI constants File: bcm1480_pci.h 5 * 6 * This module contains constants and macros to describe 7 * the PCI-X interface on the BCM1255/BCM1280/BCM1455/BCM1480. 8 * 9 * BCM1480 specification level: 1X55_1X80_UM100-R (12/18/03) 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49 #ifndef _BCM1480_PCI_H 50 #define _BCM1480_PCI_H 51 52 #include "sb1250_defs.h" 53 54 55 /* 56 * PCI Reset Register (Table 108) 57 */ 58 59 #define M_BCM1480_PCI_RESET_PIN _SB_MAKEMASK1(0) 60 #define M_BCM1480_PCI_INTERNAL_RESET _SB_MAKEMASK1(1) 61 #define M_BCM1480_PCI_TIMEOUT_RESET _SB_MAKEMASK1(2) 62 #define M_BCM1480_PCI_RESET_INTR _SB_MAKEMASK1(4) 63 #define M_BCM1480_PCI_M66EN_STATUS _SB_MAKEMASK1(8) 64 #define M_BCM1480_PCI_M66EN_DRIVE_LOW _SB_MAKEMASK1(11) 65 #define M_BCM1480_PCI_PCIXCAP_STATUS _SB_MAKEMASK1(12) 66 #define M_BCM1480_PCI_PCIXCAP_PULLUP _SB_MAKEMASK1(15) 67 #define M_BCM1480_PCI_PERR_RST_ASSERT _SB_MAKEMASK1(16) 68 #define M_BCM1480_PCI_DEVSEL_RST_ASSERT _SB_MAKEMASK1(17) 69 #define M_BCM1480_PCI_STOP_RST_ASSERT _SB_MAKEMASK1(18) 70 #define M_BCM1480_PCI_TRDY_RST_ASSERT _SB_MAKEMASK1(19) 71 #define M_BCM1480_PCI_PERR_RST_STATUS _SB_MAKEMASK1(20) 72 #define M_BCM1480_PCI_DEVSEL_RST_STATUS _SB_MAKEMASK1(21) 73 #define M_BCM1480_PCI_STOP_RST_STATUS _SB_MAKEMASK1(22) 74 #define M_BCM1480_PCI_TRDY_RST_STATUS _SB_MAKEMASK1(23) 75 76 /* 77 * PCI DLL Register (Table 110) 78 */ 79 80 #define S_BCM1480_PCI_DLL_BYPASS_MODE 0 81 #define M_BCM1480_PCI_DLL_BYPASS_MODE _SB_MAKEMASK(2,S_BCM1480_PCI_DLL_BYPASS_MODE) 82 #define V_BCM1480_PCI_DLL_BYPASS_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_PCI_DLL_BYPASS_MODE) 83 #define G_BCM1480_PCI_DLL_BYPASS_MODE(x) _SB_GETVALUE(x,S_BCM1480_PCI_DLL_BYPASS_MODE,M_BCM1480_PCI_DLL_BYPASS_MODE) 84 #define K_BCM1480_PCI_DLL_AUTO 0x0 85 #define K_BCM1480_PCI_DLL_FORCE_BYPASS 0x1 86 #define K_BCM1480_PCI_DLL_FORCE_USE 0x2 87 88 #define M_BCM1480_PCI_DLL_FIXED_VALUE_EN _SB_MAKEMASK1(3) 89 90 #define S_BCM1480_PCI_DLL_FIXED_VALUE 4 91 #define M_BCM1480_PCI_DLL_FIXED_VALUE _SB_MAKEMASK(6,S_BCM1480_PCI_DLL_FIXED_VALUE) 92 #define V_BCM1480_PCI_DLL_FIXED_VALUE(x) _SB_MAKEVALUE(x,S_BCM1480_PCI_DLL_FIXED_VALUE) 93 #define G_BCM1480_PCI_DLL_FIXED_VALUE(x) _SB_GETVALUE(x,S_BCM1480_PCI_DLL_FIXED_VALUE,M_BCM1480_PCI_DLL_FIXED_VALUE) 94 95 #define S_BCM1480_PCI_DLL_DELAY 12 96 #define M_BCM1480_PCI_DLL_DELAY _SB_MAKEMASK(4,S_BCM1480_PCI_DLL_DELAY) 97 #define V_BCM1480_PCI_DLL_DELAY(x) _SB_MAKEVALUE(x,S_BCM1480_PCI_DLL_DELAY) 98 #define G_BCM1480_PCI_DLL_DELAY(x) _SB_GETVALUE(x,S_BCM1480_PCI_DLL_DELAY,M_BCM1480_PCI_DLL_DELAY) 99 100 #define S_BCM1480_PCI_DLL_STEP_SIZE 16 101 #define M_BCM1480_PCI_DLL_STEP_SIZE _SB_MAKEMASK(4,S_BCM1480_PCI_DLL_STEP_SIZE) 102 #define V_BCM1480_PCI_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x,S_BCM1480_PCI_DLL_STEP_SIZE) 103 #define G_BCM1480_PCI_DLL_STEP_SIZE(x) _SB_GETVALUE(x,S_BCM1480_PCI_DLL_STEP_SIZE,M_BCM1480_PCI_DLL_STEP_SIZE) 104 105 106 /* 107 * The following definitions refer to PCI Configuration Space of the 108 * PCI-X Host Bridge (PHB). All registers are 32 bits. 109 */ 110 111 #define K_BCM1480_PHB_VENDOR_SIBYTE 0x166D 112 #define K_BCM1480_PHB_DEVICE_BCM1480 0x0012 113 114 /* 115 * PHB Interface Configuration Header (Table 111). 116 * The first 64 bytes are a standard Type 0 header. The bridge also 117 * implements the standard PCIX and MSI capabilities. Only 118 * device-specific extensions are defined here. 119 */ 120 121 #define R_BCM1480_PHB_FCTRL 0x0040 122 #define R_BCM1480_PHB_MAPBASE 0x0044 /* 0x44 through 0x80 - map table */ 123 #define BCM1480_PHB_MAPENTRIES 16 /* 64 bytes, 16 entries */ 124 #define R_BCM1480_PHB_MAP(n) (R_BCM1480_PHB_MAPBASE + (n)*4) 125 #define R_BCM1480_PHB_ERRORADDR 0x0084 /* lower, upper */ 126 #define R_BCM1480_PHB_ADDSTATCMD 0x008C 127 #define R_BCM1480_PHB_SUBSYSSET 0x0090 128 #define R_BCM1480_PHB_SIGNALINTA 0x0094 129 #define R_BCM1480_PHB_EXTCONFIGDIS 0x0098 130 #define R_BCM1480_PHB_VENDORIDSET 0x009C 131 #define R_BCM1480_PHB_CLASSREVSET 0x00A0 132 #define R_BCM1480_PHB_TIMEOUT 0x00A4 133 #define R_BCM1480_PHB_XACTCTRL 0x00A8 134 #define R_BCM1480_PHB_TESTDEBUG 0x00AC 135 #define R_BCM1480_PHB_OMAPBASE 0x00B0 /* 0xB0 through 0xCC - omap table */ 136 #define BCM1480_PHB_OMAPENTRIES 4 /* 32 bytes, 4 entries */ 137 #define R_BCM1480_PHB_OMAP(n) (R_BCM1480_PHB_OMAPBASE + (n)*8) 138 #define R_BCM1480_PHB_MSICAP 0x00D0 139 #define R_BCM1480_PHB_PCIXCAP 0x00E0 140 #define R_BCM1480_PHB_TGTDONE 0x00E8 141 142 143 /* 144 * PHB Feature Control Register (Table 116) 145 */ 146 147 #define M_BCM1480_PHB_FCTRL_FULL_BAR_EN _SB_MAKEMASK1_32(0) 148 #define M_BCM1480_PHB_FCTRL_FULL_BAR_SPLIT _SB_MAKEMASK1_32(1) 149 #define M_BCM1480_PHB_FCTRL_LOW_MEM_EN _SB_MAKEMASK1_32(2) 150 #define M_BCM1480_PHB_FCTRL_UPPER_MEM_EN _SB_MAKEMASK1_32(3) 151 #define M_BCM1480_PHB_FCTRL_EXP_MEM_EN _SB_MAKEMASK1_32(4) 152 #define M_BCM1480_PHB_FCTRL_EXP_MEM_SPLIT _SB_MAKEMASK1_32(5) 153 #define M_BCM1480_PHB_FCTRL_TOP_ACC_EN _SB_MAKEMASK1_32(6) 154 #define M_BCM1480_PHB_FCTRL_TOP_ACC_SPLIT _SB_MAKEMASK1_32(7) 155 #define M_BCM1480_PHB_FCTRL_USE_NODE_ID _SB_MAKEMASK1_32(8) 156 #define M_BCM1480_PHB_FCTRL_UPPER_MEM_TR _SB_MAKEMASK1_32(12) 157 #define V_BCM1480_PHB_FCTRL_DEFAULT 0 158 159 /* 160 * PHB BAR0/1 Map Table Entry (Offsets 0x44-0x80) (Table 117) 161 */ 162 163 #define M_BCM1480_PHB_MAP_ENABLE _SB_MAKEMASK1_32(0) 164 #define M_BCM1480_PHB_MAP_L2CA _SB_MAKEMASK1_32(2) 165 #define M_BCM1480_PHB_MAP_ENDIAN _SB_MAKEMASK1_32(3) 166 167 #define S_BCM1480_PHB_MAP_ADDR 12 168 #define M_BCM1480_PHB_MAP_ADDR _SB_MAKEMASK_32(20,S_BCM1480_PHB_MAP_ADDR) 169 #define V_BCM1480_PHB_MAP_ADDR(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_MAP_ADDR) 170 #define G_BCM1480_PHB_MAP_ADDR(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_MAP_ADDR,M_BCM1480_PHB_MAP_ADDR) 171 172 /* 173 * PHB Additional Status and Command Register (Table 118) 174 */ 175 176 #define M_BCM1480_PHB_ASTCMD_HOTPLUG_EN _SB_MAKEMASK1_32(0) 177 #define M_BCM1480_PHB_ASTCMD_SERR_DET _SB_MAKEMASK1_32(1) 178 #define M_BCM1480_PHB_ASTCMD_TRDY_ERR _SB_MAKEMASK1_32(2) 179 #define M_BCM1480_PHB_ASTCMD_RETRY_ERR _SB_MAKEMASK1_32(3) 180 #define M_BCM1480_PHB_ASTCMD_TRDY_INT_EN _SB_MAKEMASK1_32(4) 181 #define M_BCM1480_PHB_ASTCMD_RETRY_INT_EN _SB_MAKEMASK1_32(5) 182 #define M_BCM1480_PHB_ASTCMD_COMPL_TO_ERR _SB_MAKEMASK1_32(6) 183 #define M_BCM1480_PHB_ASTCMD_COMPL_TO_INT_EN _SB_MAKEMASK1_32(7) 184 #define M_BCM1480_PHB_ASTCMD_64B_DEVICE_SET _SB_MAKEMASK1_32(16) 185 #define M_BCM1480_PHB_ASTCMD_133MHZ_CAP_SET _SB_MAKEMASK1_32(17) 186 #define V_BCM1480_PHB_ASTCMD_DEFAULT (M_BCM1480_PHB_ASTCMD_64B_DEVICE_SET | \ 187 M_BCM1480_PHB_ASTCMD_133MHZ_CAP_SET) 188 189 /* 190 * PHB INTA Control Register (Table 119) 191 */ 192 193 #define M_BCM1480_PHB_SIGNAL_INTA _SB_MAKEMASK1_32(0) 194 195 /* 196 * PHB External Configuratation Disable Register (Table 120) 197 */ 198 199 #define M_BCM1480_PHB_EXT_CONFIG_DIS _SB_MAKEMASK1_32(0) 200 201 /* 202 * PHB Timeout Register (Table 121) 203 */ 204 205 #define S_BCM1480_PHB_TIMEOUT_TRDY 0 206 #define M_BCM1480_PHB_TIMEOUT_TRDY _SB_MAKEMASK_32(8,S_BCM1480_PHB_TIMEOUT_TRDY) 207 #define V_BCM1480_PHB_TIMEOUT_TRDY(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_TRDY) 208 #define G_BCM1480_PHB_TIMEOUT_TRDY(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_TRDY,M_BCM1480_PHB_TIMEOUT_TRDY) 209 210 #define S_BCM1480_PHB_TIMEOUT_RETRY 8 211 #define M_BCM1480_PHB_TIMEOUT_RETRY _SB_MAKEMASK_32(8,S_BCM1480_PHB_TIMEOUT_RETRY) 212 #define V_BCM1480_PHB_TIMEOUT_RETRY(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_RETRY) 213 #define G_BCM1480_PHB_TIMEOUT_RETRY(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_RETRY,M_BCM1480_PHB_TIMEOUT_RETRY) 214 215 #define S_BCM1480_PHB_TIMEOUT_COMPL 16 216 #define M_BCM1480_PHB_TIMEOUT_COMPL _SB_MAKEMASK_32(4,S_BCM1480_PHB_TIMEOUT_COMPL) 217 #define V_BCM1480_PHB_TIMEOUT_COMPL(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_COMPL) 218 #define G_BCM1480_PHB_TIMEOUT_COMPL(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_COMPL,M_BCM1480_PHB_TIMEOUT_COMPL) 219 220 #define S_BCM1480_PHB_TIMEOUT_INB_RD_PREF 20 221 #define M_BCM1480_PHB_TIMEOUT_INB_RD_PREF _SB_MAKEMASK_32(4,S_BCM1480_PHB_TIMEOUT_INB_RD_PREF) 222 #define V_BCM1480_PHB_TIMEOUT_INB_RD_PREF(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_INB_RD_PREF) 223 #define G_BCM1480_PHB_TIMEOUT_INB_RD_PREF(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_INB_RD_PREF,M_BCM1480_PHB_TIMEOUT_INB_RD_PREF) 224 225 #define M_BCM1480_PHB_TIMEOUT_INB_RD_OUTB_WR _SB_MAKEMASK1_32(24) 226 #define M_BCM1480_PHB_TIMEOUT_INB_RD_OUTB_RD _SB_MAKEMASK1_32(25) 227 #define M_BCM1480_PHB_TIMEOUT_INB_RD_INB_WR _SB_MAKEMASK1_32(25) 228 229 #define S_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG 28 230 #define M_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG _SB_MAKEMASK_32(4,S_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG) 231 #define V_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG) 232 #define G_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG,M_BCM1480_PHB_TIMEOUT_OUTB_FWD_PROG) 233 234 #define V_BCM1480_PHB_TIMEOUT_DEFAULT (V_BCM1480_PHB_TIMEOUT_TRDY(0x80) | \ 235 V_BCM1480_PHB_TIMEOUT_RETRY(0x80) | \ 236 V_BCM1480_PHB_TIMEOUT_COMPL(0xA)) 237 238 /* 239 * PHB Transaction Control Register (Table 122) 240 */ 241 242 #define S_BCM1480_PHB_XACT_WR_COMBINE_TMR 0 243 #define M_BCM1480_PHB_XACT_WR_COMBINE_TMR _SB_MAKEMASK_32(8,S_BCM1480_PHB_XACT_WR_COMBINE_TMR) 244 #define V_BCM1480_PHB_XACT_WR_COMBINE_TMR(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_WR_COMBINE_TMR) 245 #define G_BCM1480_PHB_XACT_WR_COMBINE_TMR(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_WR_COMBINE_TMR,M_BCM1480_PHB_XACT_WR_COMBINE_TMR) 246 247 #define S_BCM1480_PHB_XACT_OUTB_NP_ORDER 8 248 #define M_BCM1480_PHB_XACT_OUTB_NP_ORDER _SB_MAKEMASK_32(2,S_BCM1480_PHB_XACT_OUTB_NP_ORDER) 249 #define V_BCM1480_PHB_XACT_OUTB_NP_ORDER(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_OUTB_NP_ORDER) 250 #define G_BCM1480_PHB_XACT_OUTB_NP_ORDER(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_OUTB_NP_ORDER,M_BCM1480_PHB_XACT_OUTB_NP_ORDER) 251 252 #define M_BCM1480_PHB_XACT_SET_WR_RLX_ORDER _SB_MAKEMASK1_32(10) 253 #define M_BCM1480_PHB_XACT_SET_RSP_RLX_ORDER _SB_MAKEMASK1_32(11) 254 #define M_BCM1480_PHB_XACT_SET_WR_NO_SNOOP _SB_MAKEMASK1_32(12) 255 #define M_BCM1480_PHB_XACT_SET_RD_NO_SNOOP _SB_MAKEMASK1_32(13) 256 #define M_BCM1480_PHB_XACT_SET_OUTB_RD_PREF_DIS _SB_MAKEMASK1_32(14) 257 #define M_BCM1480_PHB_XACT_SET_OUTB_RSP_WR_ORD_DIS _SB_MAKEMASK1_32(15) 258 259 #define S_BCM1480_PHB_XACT_INB_RD_MAX_PREF 20 260 #define M_BCM1480_PHB_XACT_INB_RD_MAX_PREF _SB_MAKEMASK_32(3,S_BCM1480_PHB_XACT_INB_RD_MAX_PREF) 261 #define V_BCM1480_PHB_XACT_INB_RD_MAX_PREF(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_MAX_PREF) 262 #define G_BCM1480_PHB_XACT_INB_RD_MAX_PREF(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_MAX_PREF,M_BCM1480_PHB_XACT_INB_RD_MAX_PREF) 263 264 #define S_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF 24 265 #define M_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF _SB_MAKEMASK_32(3,S_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF) 266 #define V_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF) 267 #define G_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF,M_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF) 268 269 #define S_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF 28 270 #define M_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF _SB_MAKEMASK_32(3,S_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF) 271 #define V_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF) 272 #define G_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF,M_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF) 273 274 #define K_BCM1480_PHB_PREF_256B 0x0 275 #define K_BCM1480_PHB_PREF_32B 0x1 276 #define K_BCM1480_PHB_PREF_64B 0x2 277 #define K_BCM1480_PHB_PREF_96B 0x3 278 #define K_BCM1480_PHB_PREF_128B 0x4 /* also 0x5 */ 279 #define K_BCM1480_PHB_PREF_192B 0x6 /* also 0x7 */ 280 281 #define V_BCM1480_PHB_XACT_DEFAULT (V_BCM1480_PHB_XACT_WR_COMBINE_TMR(0x20) | \ 282 V_BCM1480_PHB_XACT_OUTB_NP_ORDER(0x1) | \ 283 V_BCM1480_PHB_XACT_INB_RD_MAX_PREF(0x1) | \ 284 V_BCM1480_PHB_XACT_INB_RD_LN_MAX_PREF(0x1) | \ 285 V_BCM1480_PHB_XACT_INB_RD_MUL_MAX_PREF(0x4)) 286 287 /* 288 * PHB Test and Debug Register (Table 123) 289 */ 290 291 #define M_BCM1480_PHB_TEST_LOOPBACK _SB_MAKEMASK1_32(0) 292 #define M_BCM1480_PHB_TEST_32BIT_MODE _SB_MAKEMASK1_32(1) 293 #define M_BCM1480_PHB_TEST_QUICK_TEST _SB_MAKEMASK1_32(2) 294 295 /* 296 * PHB Outbound Map Table Entries (Lower, Upper) (Tables 124 and 125) 297 */ 298 299 #define M_BCM1480_PHB_OMAP_L_ENABLE _SB_MAKEMASK1_32(0) 300 301 #define S_BCM1480_PHB_OMAP_L_ADDR 20 302 #define M_BCM1480_PHB_OMAP_L_ADDR _SB_MAKEMASK_32(12,S_BCM1480_PHB_OMAP_L_ADDR) 303 #define V_BCM1480_PHB_OMAP_L_ADDR(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_OMAP_L_ADDR) 304 #define G_BCM1480_PHB_OMAP_L_ADDR(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_OMAP_L_ADDR,M_BCM1480_PHB_OMAP_L_ADDR) 305 306 #define S_BCM1480_PHB_OMAP_U_ADDR 0 307 #define M_BCM1480_PHB_OMAP_U_ADDR _SB_MAKEMASK_32(32,S_BCM1480_PHB_OMAP_U_ADDR) 308 #define V_BCM1480_PHB_OMAP_U_ADDR(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_OMAP_U_ADDR) 309 #define G_BCM1480_PHB_OMAP_U_ADDR(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_OMAP_U_ADDR,M_BCM1480_PHB_OMAP_U_ADDR) 310 311 /* 312 * PHB Target Done Register (Table 129) 313 */ 314 315 #define S_BCM1480_PHB_TGT_DONE_COUNTER 0 316 #define M_BCM1480_PHB_TGT_DONE_COUNTER _SB_MAKEMASK_32(8,S_BCM1480_PHB_TGT_DONE_COUNTER) 317 #define V_BCM1480_PHB_TGT_DONE_COUNTER(x) _SB_MAKEVALUE_32(x,S_BCM1480_PHB_TGT_DONE_COUNTER) 318 #define G_BCM1480_PHB_TGT_DONE_COUNTER(x) _SB_GETVALUE_32(x,S_BCM1480_PHB_TGT_DONE_COUNTER,M_BCM1480_PHB_TGT_DONE_COUNTER) 319 320 321 struct bcm1480_inbw_conf { 322 323 unsigned long long pa; /* Base address(Physical) of the memory region to be mapped at BAR0 */ 324 325 unsigned int offset; /* Offset from the Base address - Start of the region */ 326 327 unsigned int len; /* Length of the region */ 328 329 int l2ca; /* L2CA flag */ 330 331 int endian; /* Endian flag */ 332 }; 333 334 #endif /* _BCM1480_PCI_H */ 335 336