1 /* $NetBSD: aupcivar.h,v 1.3 2011/04/04 20:37:51 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _MIPS_ALCHEMY_DEV_AUPCIVAR_H 35 #define _MIPS_ALCHEMY_DEV_AUPCIVAR_H 36 37 #include <dev/pci/pcivar.h> 38 39 /* 40 * PCI configuration space encompasses all 32-bits. 41 * 42 * PCI memory space encompasses all 32-bits, excepting that portion of 43 * the address space that is decoded by the Alchemy core for accesses 44 * to host memory. (That range is determined dynamically.) 45 * 46 * PCI I/O address range. We want to start offset from zero to avoid 47 * potential problems with devices. These addresses do not 48 * participate on the Alchemy system bus, hence we can choose any 49 * range we like. 16 MB is plenty. 50 */ 51 52 #define AUPCI_IO_START 0x1000000 53 #define AUPCI_IO_END 0x1FFFFFF 54 55 56 /* 57 * Machdep code must implement this. Stores an IRQ number in 58 * pci_intr_handle_t. See pci_intr_map(9) for more detail. Returns 0 59 * on success, non-zero on failure. 60 */ 61 int aupci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 62 63 #endif /* _MIPS_ALCHEMY_DEV_AUPCIVAR_H */ 64