1 /* $NetBSD: at91emac.c,v 1.36 2024/07/05 04:31:49 rin Exp $ */
2
3 /*
4 * Copyright (c) 2007 Embedtronics Oy
5 * All rights reserved.
6 *
7 * Based on arch/arm/ep93xx/epe.c
8 *
9 * Copyright (c) 2004 Jesse Off
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: at91emac.c,v 1.36 2024/07/05 04:31:49 rin Exp $");
36
37 #include <sys/types.h>
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/ioctl.h>
41 #include <sys/kernel.h>
42 #include <sys/proc.h>
43 #include <sys/time.h>
44 #include <sys/device.h>
45 #include <uvm/uvm_extern.h>
46
47 #include <sys/bus.h>
48 #include <machine/intr.h>
49
50 #include <arm/cpufunc.h>
51
52 #include <net/if.h>
53 #include <net/if_dl.h>
54 #include <net/if_types.h>
55 #include <net/if_media.h>
56 #include <net/if_ether.h>
57 #include <net/bpf.h>
58
59 #include <dev/mii/mii.h>
60 #include <dev/mii/miivar.h>
61
62 #ifdef INET
63 #include <netinet/in.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in_var.h>
66 #include <netinet/ip.h>
67 #include <netinet/if_inarp.h>
68 #endif
69
70 #include <arm/at91/at91var.h>
71 #include <arm/at91/at91emacreg.h>
72 #include <arm/at91/at91emacvar.h>
73
74 #define DEFAULT_MDCDIV 32
75
76 #ifndef EMAC_FAST
77 #define EMAC_FAST
78 #endif
79
80 #ifndef EMAC_FAST
81 #define EMAC_READ(x) \
82 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x))
83 #define EMAC_WRITE(x, y) \
84 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y))
85 #else
86 #define EMAC_READ(x) ETHREG(x)
87 #define EMAC_WRITE(x, y) ETHREG(x) = (y)
88 #endif /* ! EMAC_FAST */
89
90 static int emac_match(device_t, cfdata_t, void *);
91 static void emac_attach(device_t, device_t, void *);
92 static void emac_init(struct emac_softc *);
93 static int emac_intr(void* arg);
94 static int emac_gctx(struct emac_softc *);
95 int emac_mii_readreg (device_t, int, int, uint16_t *);
96 int emac_mii_writereg (device_t, int, int, uint16_t);
97 void emac_statchg (struct ifnet *);
98 void emac_tick (void *);
99 static int emac_ifioctl (struct ifnet *, u_long, void *);
100 static void emac_ifstart (struct ifnet *);
101 static void emac_ifwatchdog (struct ifnet *);
102 static int emac_ifinit (struct ifnet *);
103 static void emac_ifstop (struct ifnet *, int);
104 static void emac_setaddr (struct ifnet *);
105
106 CFATTACH_DECL_NEW(at91emac, sizeof(struct emac_softc),
107 emac_match, emac_attach, NULL, NULL);
108
109 #ifdef EMAC_DEBUG
110 int emac_debug = EMAC_DEBUG;
111 #define DPRINTFN(n, fmt) if (emac_debug >= (n)) printf fmt
112 #else
113 #define DPRINTFN(n, fmt)
114 #endif
115
116 static int
emac_match(device_t parent,cfdata_t match,void * aux)117 emac_match(device_t parent, cfdata_t match, void *aux)
118 {
119 if (strcmp(match->cf_name, "at91emac") == 0)
120 return 2;
121 return 0;
122 }
123
124 static void
emac_attach(device_t parent,device_t self,void * aux)125 emac_attach(device_t parent, device_t self, void *aux)
126 {
127 struct emac_softc *sc = device_private(self);
128 struct at91bus_attach_args *sa = aux;
129 prop_data_t enaddr;
130 uint32_t u;
131
132 printf("\n");
133 sc->sc_dev = self;
134 sc->sc_iot = sa->sa_iot;
135 sc->sc_pid = sa->sa_pid;
136 sc->sc_dmat = sa->sa_dmat;
137
138 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &sc->sc_ioh))
139 panic("%s: Cannot map registers", device_xname(self));
140
141 /* enable peripheral clock */
142 at91_peripheral_clock(sc->sc_pid, 1);
143
144 /* configure emac: */
145 EMAC_WRITE(ETH_CTL, 0); // disable everything
146 EMAC_WRITE(ETH_IDR, -1); // disable interrupts
147 EMAC_WRITE(ETH_RBQP, 0); // clear receive
148 EMAC_WRITE(ETH_CFG,
149 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG);
150 EMAC_WRITE(ETH_TCR, 0); // send nothing
151 //(void)EMAC_READ(ETH_ISR);
152 u = EMAC_READ(ETH_TSR);
153 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
154 | ETH_TSR_IDLE | ETH_TSR_RLE
155 | ETH_TSR_COL | ETH_TSR_OVR)));
156 u = EMAC_READ(ETH_RSR);
157 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
158
159 /* Fetch the Ethernet address from property if set. */
160 enaddr = prop_dictionary_get(device_properties(self), "mac-address");
161
162 if (enaddr != NULL) {
163 KASSERT(prop_object_type(enaddr) == PROP_TYPE_DATA);
164 KASSERT(prop_data_size(enaddr) == ETHER_ADDR_LEN);
165 memcpy(sc->sc_enaddr, prop_data_data_nocopy(enaddr),
166 ETHER_ADDR_LEN);
167 } else {
168 static const uint8_t hardcoded[ETHER_ADDR_LEN] = {
169 0x00, 0x0d, 0x10, 0x81, 0x0c, 0x94
170 };
171 memcpy(sc->sc_enaddr, hardcoded, ETHER_ADDR_LEN);
172 }
173
174 at91_intr_establish(sc->sc_pid, IPL_NET, INTR_HIGH_LEVEL, emac_intr,
175 sc);
176 emac_init(sc);
177 }
178
179 static int
emac_gctx(struct emac_softc * sc)180 emac_gctx(struct emac_softc *sc)
181 {
182 uint32_t tsr;
183
184 tsr = EMAC_READ(ETH_TSR);
185 if (!(tsr & ETH_TSR_BNQ)) {
186 // no space left
187 return 0;
188 }
189
190 // free sent frames
191 while (sc->txqc > (tsr & ETH_TSR_IDLE ? 0 : 1)) {
192 int i = sc->txqi % TX_QLEN;
193 bus_dmamap_sync(sc->sc_dmat, sc->txq[i].m_dmamap, 0,
194 sc->txq[i].m->m_pkthdr.len, BUS_DMASYNC_POSTWRITE);
195 bus_dmamap_unload(sc->sc_dmat, sc->txq[i].m_dmamap);
196 m_freem(sc->txq[i].m);
197 DPRINTFN(2,("%s: freed idx #%i mbuf %p (txqc=%i)\n",
198 __FUNCTION__, i, sc->txq[i].m, sc->txqc));
199 sc->txq[i].m = NULL;
200 sc->txqi = (i + 1) % TX_QLEN;
201 sc->txqc--;
202 }
203
204 // mark we're free
205 if (sc->tx_busy) {
206 sc->tx_busy = false;
207 /* Disable transmit-buffer-free interrupt */
208 /*EMAC_WRITE(ETH_IDR, ETH_ISR_TBRE);*/
209 }
210
211 return 1;
212 }
213
214 static int
emac_intr(void * arg)215 emac_intr(void *arg)
216 {
217 struct emac_softc *sc = (struct emac_softc *)arg;
218 struct ifnet * ifp = &sc->sc_ec.ec_if;
219 uint32_t imr, isr, ctl;
220 int bi;
221
222 imr = ~EMAC_READ(ETH_IMR);
223 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
224 | ETH_ISR_RBNA | ETH_ISR_ROVR))) {
225 // interrupt not enabled, can't be us
226 return 0;
227 }
228
229 isr = EMAC_READ(ETH_ISR) & imr;
230 #ifdef EMAC_DEBUG
231 uint32_t rsr =
232 #endif
233 EMAC_READ(ETH_RSR); // get receive status register
234
235 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__,
236 isr, rsr, imr));
237
238 if (isr & ETH_ISR_RBNA) { // out of receive buffers
239 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt
240 ctl = EMAC_READ(ETH_CTL); // get current control register value
241 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE); // disable receiver
242 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit
243 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE); // re-enable receiver
244 if_statinc(ifp, if_ierrors);
245 if_statinc(ifp, if_ipackets);
246 DPRINTFN(1,("%s: out of receive buffers\n", __FUNCTION__));
247 }
248 if (isr & ETH_ISR_ROVR) {
249 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt
250 if_statinc(ifp, if_ierrors);
251 if_statinc(ifp, if_ipackets);
252 DPRINTFN(1,("%s: receive overrun\n", __FUNCTION__));
253 }
254
255 if (isr & ETH_ISR_RCOM) { // packet has been received!
256 uint32_t nfo;
257 // @@@ if memory is NOT coherent, then we're in trouble @@@@
258 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
259 // printf("## RDSC[%i].ADDR=0x%08X\n", sc->rxqi % RX_QLEN, sc->RDSC[sc->rxqi % RX_QLEN].Addr);
260 DPRINTFN(2,("#2 RDSC[%i].INFO=0x%08X\n", sc->rxqi % RX_QLEN,
261 sc->RDSC[sc->rxqi % RX_QLEN].Info));
262 while (sc->RDSC[(bi = sc->rxqi % RX_QLEN)].Addr & ETH_RDSC_F_USED) {
263 int fl;
264 struct mbuf *m;
265
266 nfo = sc->RDSC[bi].Info;
267 fl = (nfo & ETH_RDSC_I_LEN) - 4;
268 DPRINTFN(2,("## nfo=0x%08X\n", nfo));
269
270 MGETHDR(m, M_DONTWAIT, MT_DATA);
271 if (m != NULL) MCLGET(m, M_DONTWAIT);
272 if (m != NULL && (m->m_flags & M_EXT)) {
273 bus_dmamap_sync(sc->sc_dmat,
274 sc->rxq[bi].m_dmamap, 0,
275 MCLBYTES, BUS_DMASYNC_POSTREAD);
276 bus_dmamap_unload(sc->sc_dmat,
277 sc->rxq[bi].m_dmamap);
278 m_set_rcvif(sc->rxq[bi].m, ifp);
279 sc->rxq[bi].m->m_pkthdr.len =
280 sc->rxq[bi].m->m_len = fl;
281 DPRINTFN(2,("received %u bytes packet\n", fl));
282 if_percpuq_enqueue(ifp->if_percpuq, sc->rxq[bi].m);
283 if (mtod(m, intptr_t) & 3) {
284 m_adj(m, mtod(m, intptr_t) & 3);
285 }
286 sc->rxq[bi].m = m;
287 bus_dmamap_load(sc->sc_dmat,
288 sc->rxq[bi].m_dmamap,
289 m->m_ext.ext_buf, MCLBYTES,
290 NULL, BUS_DMA_NOWAIT);
291 bus_dmamap_sync(sc->sc_dmat,
292 sc->rxq[bi].m_dmamap, 0,
293 MCLBYTES, BUS_DMASYNC_PREREAD);
294 sc->RDSC[bi].Info = 0;
295 sc->RDSC[bi].Addr =
296 sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr
297 | (bi == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0);
298 } else {
299 /* Drop packets until we can get replacement
300 * empty mbufs for the RXDQ.
301 */
302 m_freem(m);
303 if_statinc(ifp, if_ierrors);
304 }
305 sc->rxqi++;
306 }
307 // bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
308 }
309
310 if (emac_gctx(sc) > 0)
311 if_schedule_deferred_start(ifp);
312 #if 0 // reloop
313 irq = EMAC_READ(IntStsC);
314 if ((irq & (IntSts_RxSQ | IntSts_ECI)) != 0)
315 goto begin;
316 #endif
317
318 return (1);
319 }
320
321
322 static void
emac_init(struct emac_softc * sc)323 emac_init(struct emac_softc *sc)
324 {
325 bus_dma_segment_t segs;
326 void *addr;
327 int rsegs, err, i;
328 struct ifnet * ifp = &sc->sc_ec.ec_if;
329 struct mii_data * const mii = &sc->sc_mii;
330 uint32_t u;
331 #if 0
332 int mdcdiv = DEFAULT_MDCDIV;
333 #endif
334
335 callout_init(&sc->emac_tick_ch, 0);
336
337 // ok...
338 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
339 EMAC_WRITE(ETH_IDR, -1); // disable interrupts
340 EMAC_WRITE(ETH_RBQP, 0); // clear receive
341 EMAC_WRITE(ETH_CFG,
342 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG);
343 EMAC_WRITE(ETH_TCR, 0); // send nothing
344 // (void)EMAC_READ(ETH_ISR);
345 u = EMAC_READ(ETH_TSR);
346 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
347 | ETH_TSR_IDLE | ETH_TSR_RLE
348 | ETH_TSR_COL | ETH_TSR_OVR)));
349 u = EMAC_READ(ETH_RSR);
350 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
351
352 /* configure EMAC */
353 EMAC_WRITE(ETH_CFG,
354 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG);
355 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE);
356 #if 0
357 if (device_cfdata(sc->sc_dev)->cf_flags)
358 mdcdiv = device_cfdata(sc->sc_dev)->cf_flags;
359 #endif
360 /* set ethernet address */
361 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24)
362 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8)
363 | (sc->sc_enaddr[0]));
364 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8)
365 | (sc->sc_enaddr[4]));
366 EMAC_WRITE(ETH_SA2L, 0);
367 EMAC_WRITE(ETH_SA2H, 0);
368 EMAC_WRITE(ETH_SA3L, 0);
369 EMAC_WRITE(ETH_SA3H, 0);
370 EMAC_WRITE(ETH_SA4L, 0);
371 EMAC_WRITE(ETH_SA4H, 0);
372
373 /* Allocate a page of memory for receive queue descriptors */
374 sc->rbqlen = (ETH_RDSC_SIZE * (RX_QLEN + 1) * 2 + PAGE_SIZE - 1) / PAGE_SIZE;
375 sc->rbqlen *= PAGE_SIZE;
376 DPRINTFN(1,("%s: rbqlen=%i\n", __FUNCTION__, sc->rbqlen));
377
378 err = bus_dmamem_alloc(sc->sc_dmat, sc->rbqlen, 0,
379 MAX(16384, PAGE_SIZE), // see EMAC errata why forced to 16384 byte boundary
380 &segs, 1, &rsegs, BUS_DMA_WAITOK);
381 if (err == 0) {
382 DPRINTFN(1,("%s: -> bus_dmamem_map\n", __FUNCTION__));
383 err = bus_dmamem_map(sc->sc_dmat, &segs, 1, sc->rbqlen,
384 &sc->rbqpage, (BUS_DMA_WAITOK | BUS_DMA_COHERENT));
385 }
386 if (err == 0) {
387 DPRINTFN(1,("%s: -> bus_dmamap_create\n", __FUNCTION__));
388 err = bus_dmamap_create(sc->sc_dmat, sc->rbqlen, 1,
389 sc->rbqlen, MAX(16384, PAGE_SIZE), BUS_DMA_WAITOK,
390 &sc->rbqpage_dmamap);
391 }
392 if (err == 0) {
393 DPRINTFN(1,("%s: -> bus_dmamap_load\n", __FUNCTION__));
394 err = bus_dmamap_load(sc->sc_dmat, sc->rbqpage_dmamap,
395 sc->rbqpage, sc->rbqlen, NULL, BUS_DMA_WAITOK);
396 }
397 if (err != 0) {
398 panic("%s: Cannot get DMA memory", device_xname(sc->sc_dev));
399 }
400 sc->rbqpage_dsaddr = sc->rbqpage_dmamap->dm_segs[0].ds_addr;
401
402 memset(sc->rbqpage, 0, sc->rbqlen);
403
404 /* Set up pointers to start of each queue in kernel addr space.
405 * Each descriptor queue or status queue entry uses 2 words
406 */
407 sc->RDSC = (void*)sc->rbqpage;
408
409 /* Populate the RXQ with mbufs */
410 sc->rxqi = 0;
411 for (i = 0; i < RX_QLEN; i++) {
412 struct mbuf *m;
413
414 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
415 PAGE_SIZE, BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap);
416 if (err)
417 panic("%s: dmamap_create failed: %i\n",
418 __FUNCTION__, err);
419
420 MGETHDR(m, M_WAIT, MT_DATA);
421 MCLGET(m, M_WAIT);
422 sc->rxq[i].m = m;
423 if (mtod(m, intptr_t) & 3) {
424 m_adj(m, mtod(m, intptr_t) & 3);
425 }
426 err = bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap,
427 m->m_ext.ext_buf, MCLBYTES, NULL,
428 BUS_DMA_WAITOK);
429 if (err)
430 panic("%s: dmamap_load failed: %i\n",
431 __FUNCTION__, err);
432
433 sc->RDSC[i].Addr = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr
434 | (i == (RX_QLEN-1) ? ETH_RDSC_F_WRAP : 0);
435 sc->RDSC[i].Info = 0;
436 bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0,
437 MCLBYTES, BUS_DMASYNC_PREREAD);
438 }
439
440 /* prepare transmit queue */
441 for (i = 0; i < TX_QLEN; i++) {
442 err = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
443 (BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW),
444 &sc->txq[i].m_dmamap);
445 if (err)
446 panic("ARGH #1");
447 sc->txq[i].m = NULL;
448 }
449
450 /* Program each queue's start addr, cur addr, and len registers
451 * with the physical addresses.
452 */
453 bus_dmamap_sync(sc->sc_dmat, sc->rbqpage_dmamap, 0, sc->rbqlen,
454 BUS_DMASYNC_PREREAD);
455 addr = (void *)sc->rbqpage_dmamap->dm_segs[0].ds_addr;
456 EMAC_WRITE(ETH_RBQP, (uint32_t)addr);
457
458 /* Divide HCLK by 32 for MDC clock */
459 mii->mii_ifp = ifp;
460 mii->mii_readreg = emac_mii_readreg;
461 mii->mii_writereg = emac_mii_writereg;
462 mii->mii_statchg = emac_statchg;
463 sc->sc_ec.ec_mii = mii;
464 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
465 ether_mediastatus);
466 mii_attach((device_t )sc, mii, 0xffffffff, MII_PHY_ANY,
467 MII_OFFSET_ANY, 0);
468 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
469
470 // enable / disable interrupts
471
472 #if 0
473 // enable / disable interrupts
474 EMAC_WRITE(ETH_IDR, -1);
475 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
476 | ETH_ISR_RBNA | ETH_ISR_ROVR);
477 // (void)EMAC_READ(ETH_ISR); // why
478
479 // enable transmitter / receiver
480 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
481 | ETH_CTL_CSR | ETH_CTL_MPE);
482 #endif
483 /*
484 * We can support 802.1Q VLAN-sized frames.
485 */
486 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
487
488 strcpy(ifp->if_xname, device_xname(sc->sc_dev));
489 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
490 ifp->if_ioctl = emac_ifioctl;
491 ifp->if_start = emac_ifstart;
492 ifp->if_watchdog = emac_ifwatchdog;
493 ifp->if_init = emac_ifinit;
494 ifp->if_stop = emac_ifstop;
495 ifp->if_timer = 0;
496 ifp->if_softc = sc;
497 IFQ_SET_READY(&ifp->if_snd);
498 if_attach(ifp);
499 if_deferred_start_init(ifp, NULL);
500 ether_ifattach(ifp, (sc)->sc_enaddr);
501 }
502
503 int
emac_mii_readreg(device_t self,int phy,int reg,uint16_t * val)504 emac_mii_readreg(device_t self, int phy, int reg, uint16_t *val)
505 {
506 #ifndef EMAC_FAST
507 struct emac_softc *sc = device_private(self);
508 #endif
509
510 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_RD
511 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA)
512 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA)
513 | ETH_MAN_CODE_IEEE802_3));
514 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE))
515 ;
516 *val = EMAC_READ(ETH_MAN) & ETH_MAN_DATA;
517
518 return 0;
519 }
520
521 int
emac_mii_writereg(device_t self,int phy,int reg,uint16_t val)522 emac_mii_writereg(device_t self, int phy, int reg, uint16_t val)
523 {
524 #ifndef EMAC_FAST
525 struct emac_softc *sc = device_private(self);
526 #endif
527
528 EMAC_WRITE(ETH_MAN, (ETH_MAN_HIGH | ETH_MAN_RW_WR
529 | ((phy << ETH_MAN_PHYA_SHIFT) & ETH_MAN_PHYA)
530 | ((reg << ETH_MAN_REGA_SHIFT) & ETH_MAN_REGA)
531 | ETH_MAN_CODE_IEEE802_3
532 | (val & ETH_MAN_DATA)));
533 while (!(EMAC_READ(ETH_SR) & ETH_SR_IDLE))
534 ;
535
536 return 0;
537 }
538
539 void
emac_statchg(struct ifnet * ifp)540 emac_statchg(struct ifnet *ifp)
541 {
542 struct emac_softc *sc = ifp->if_softc;
543 uint32_t reg;
544
545 /*
546 * We must keep the MAC and the PHY in sync as
547 * to the status of full-duplex!
548 */
549 reg = EMAC_READ(ETH_CFG);
550 if (sc->sc_mii.mii_media_active & IFM_FDX)
551 reg |= ETH_CFG_FD;
552 else
553 reg &= ~ETH_CFG_FD;
554 EMAC_WRITE(ETH_CFG, reg);
555 }
556
557 void
emac_tick(void * arg)558 emac_tick(void *arg)
559 {
560 struct emac_softc* sc = (struct emac_softc *)arg;
561 struct ifnet * ifp = &sc->sc_ec.ec_if;
562 int s;
563 uint32_t misses;
564
565 if_statadd(ifp, if_collisions, EMAC_READ(ETH_SCOL) + EMAC_READ(ETH_MCOL));
566 /* These misses are ok, they will happen if the RAM/CPU can't keep up */
567 misses = EMAC_READ(ETH_DRFC);
568 if (misses > 0)
569 printf("%s: %d rx misses\n", device_xname(sc->sc_dev), misses);
570
571 s = splnet();
572 if (emac_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
573 emac_ifstart(ifp);
574 }
575 splx(s);
576
577 mii_tick(&sc->sc_mii);
578 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
579 }
580
581
582 static int
emac_ifioctl(struct ifnet * ifp,u_long cmd,void * data)583 emac_ifioctl(struct ifnet *ifp, u_long cmd, void *data)
584 {
585 int s, error;
586
587 s = splnet();
588 switch (cmd) {
589 default:
590 error = ether_ioctl(ifp, cmd, data);
591 if (error == ENETRESET) {
592 if (ifp->if_flags & IFF_RUNNING)
593 emac_setaddr(ifp);
594 error = 0;
595 }
596 }
597 splx(s);
598 return error;
599 }
600
601 static void
emac_ifstart(struct ifnet * ifp)602 emac_ifstart(struct ifnet *ifp)
603 {
604 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc;
605 struct mbuf *m;
606 bus_dma_segment_t *segs;
607 int s, bi, err, nsegs;
608
609 s = splnet();
610 start:
611 if (emac_gctx(sc) == 0) {
612 /* Enable transmit-buffer-free interrupt */
613 EMAC_WRITE(ETH_IER, ETH_ISR_TBRE);
614 sc->tx_busy = true;
615 ifp->if_timer = 10;
616 splx(s);
617 return;
618 }
619
620 ifp->if_timer = 0;
621
622 IFQ_POLL(&ifp->if_snd, m);
623 if (m == NULL) {
624 splx(s);
625 return;
626 }
627 //more:
628 bi = (sc->txqi + sc->txqc) % TX_QLEN;
629 if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
630 BUS_DMA_NOWAIT)) ||
631 sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 ||
632 sc->txq[bi].m_dmamap->dm_nsegs > 1) {
633 /* Copy entire mbuf chain to new single */
634 struct mbuf *mn;
635
636 if (err == 0)
637 bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap);
638
639 MGETHDR(mn, M_DONTWAIT, MT_DATA);
640 if (mn == NULL) goto stop;
641 if (m->m_pkthdr.len > MHLEN) {
642 MCLGET(mn, M_DONTWAIT);
643 if ((mn->m_flags & M_EXT) == 0) {
644 m_freem(mn);
645 goto stop;
646 }
647 }
648 m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, void *));
649 mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len;
650 IFQ_DEQUEUE(&ifp->if_snd, m);
651 m_freem(m);
652 m = mn;
653 bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
654 BUS_DMA_NOWAIT);
655 } else {
656 IFQ_DEQUEUE(&ifp->if_snd, m);
657 }
658
659 bpf_mtap(ifp, m, BPF_D_OUT);
660
661 nsegs = sc->txq[bi].m_dmamap->dm_nsegs;
662 segs = sc->txq[bi].m_dmamap->dm_segs;
663 if (nsegs > 1) {
664 panic("#### ARGH #2");
665 }
666
667 sc->txq[bi].m = m;
668 sc->txqc++;
669
670 DPRINTFN(2,("%s: start sending idx #%i mbuf %p (txqc=%i, phys %p), len=%u\n", __FUNCTION__, bi, sc->txq[bi].m, sc->txqc, (void*)segs->ds_addr,
671 (unsigned)m->m_pkthdr.len));
672 #ifdef DIAGNOSTIC
673 if (sc->txqc > TX_QLEN) {
674 panic("%s: txqc %i > %i", __FUNCTION__, sc->txqc, TX_QLEN);
675 }
676 #endif
677
678 bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0,
679 sc->txq[bi].m_dmamap->dm_mapsize,
680 BUS_DMASYNC_PREWRITE);
681
682 EMAC_WRITE(ETH_TAR, segs->ds_addr);
683 EMAC_WRITE(ETH_TCR, m->m_pkthdr.len);
684 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
685 goto start;
686 stop:
687
688 splx(s);
689 return;
690 }
691
692 static void
emac_ifwatchdog(struct ifnet * ifp)693 emac_ifwatchdog(struct ifnet *ifp)
694 {
695 struct emac_softc *sc = (struct emac_softc *)ifp->if_softc;
696
697 if ((ifp->if_flags & IFF_RUNNING) == 0)
698 return;
699 printf("%s: device timeout, CTL = 0x%08x, CFG = 0x%08x\n",
700 device_xname(sc->sc_dev), EMAC_READ(ETH_CTL), EMAC_READ(ETH_CFG));
701 }
702
703 static int
emac_ifinit(struct ifnet * ifp)704 emac_ifinit(struct ifnet *ifp)
705 {
706 struct emac_softc *sc = ifp->if_softc;
707 int s = splnet();
708
709 callout_stop(&sc->emac_tick_ch);
710
711 // enable interrupts
712 EMAC_WRITE(ETH_IDR, -1);
713 EMAC_WRITE(ETH_IER, ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
714 | ETH_ISR_RBNA | ETH_ISR_ROVR);
715
716 // enable transmitter / receiver
717 EMAC_WRITE(ETH_CTL, ETH_CTL_TE | ETH_CTL_RE | ETH_CTL_ISR
718 | ETH_CTL_CSR | ETH_CTL_MPE);
719
720 mii_mediachg(&sc->sc_mii);
721 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
722 ifp->if_flags |= IFF_RUNNING;
723 splx(s);
724 return 0;
725 }
726
727 static void
emac_ifstop(struct ifnet * ifp,int disable)728 emac_ifstop(struct ifnet *ifp, int disable)
729 {
730 // uint32_t u;
731 struct emac_softc *sc = ifp->if_softc;
732
733 #if 0
734 EMAC_WRITE(ETH_CTL, ETH_CTL_MPE); // disable everything
735 EMAC_WRITE(ETH_IDR, -1); // disable interrupts
736 // EMAC_WRITE(ETH_RBQP, 0); // clear receive
737 EMAC_WRITE(ETH_CFG,
738 ETH_CFG_CLK_32 | ETH_CFG_SPD | ETH_CFG_FD | ETH_CFG_BIG);
739 EMAC_WRITE(ETH_TCR, 0); // send nothing
740 // (void)EMAC_READ(ETH_ISR);
741 u = EMAC_READ(ETH_TSR);
742 EMAC_WRITE(ETH_TSR, (u & (ETH_TSR_UND | ETH_TSR_COMP | ETH_TSR_BNQ
743 | ETH_TSR_IDLE | ETH_TSR_RLE
744 | ETH_TSR_COL | ETH_TSR_OVR)));
745 u = EMAC_READ(ETH_RSR);
746 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
747 #endif
748 callout_stop(&sc->emac_tick_ch);
749
750 /* Down the MII. */
751 mii_down(&sc->sc_mii);
752
753 ifp->if_flags &= ~IFF_RUNNING;
754 ifp->if_timer = 0;
755 sc->sc_mii.mii_media_status &= ~IFM_ACTIVE;
756 }
757
758 static void
emac_setaddr(struct ifnet * ifp)759 emac_setaddr(struct ifnet *ifp)
760 {
761 struct emac_softc *sc = ifp->if_softc;
762 struct ethercom *ec = &sc->sc_ec;
763 struct ether_multi *enm;
764 struct ether_multistep step;
765 uint8_t ias[3][ETHER_ADDR_LEN];
766 uint32_t h, nma = 0, hashes[2] = { 0, 0 };
767 uint32_t ctl = EMAC_READ(ETH_CTL);
768 uint32_t cfg = EMAC_READ(ETH_CFG);
769
770 /* disable receiver temporarily */
771 EMAC_WRITE(ETH_CTL, ctl & ~ETH_CTL_RE);
772
773 cfg &= ~(ETH_CFG_MTI | ETH_CFG_UNI | ETH_CFG_CAF);
774
775 if (ifp->if_flags & IFF_PROMISC) {
776 cfg |= ETH_CFG_CAF;
777 } else {
778 cfg &= ~ETH_CFG_CAF;
779 }
780
781 // ETH_CFG_BIG?
782
783 ifp->if_flags &= ~IFF_ALLMULTI;
784
785 ETHER_LOCK(ec);
786 ETHER_FIRST_MULTI(step, ec, enm);
787 while (enm != NULL) {
788 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
789 /*
790 * We must listen to a range of multicast addresses.
791 * For now, just accept all multicasts, rather than
792 * trying to set only those filter bits needed to match
793 * the range. (At this time, the only use of address
794 * ranges is for IP multicast routing, for which the
795 * range is big enough to require all bits set.)
796 */
797 cfg |= ETH_CFG_CAF;
798 hashes[0] = 0xffffffffUL;
799 hashes[1] = 0xffffffffUL;
800 ifp->if_flags |= IFF_ALLMULTI;
801 nma = 0;
802 break;
803 }
804
805 if (nma < 3) {
806 /* We can program 3 perfect address filters for mcast */
807 memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN);
808 } else {
809 /*
810 * XXX: Datasheet is not very clear here, I'm not sure
811 * if I'm doing this right. --joff
812 */
813 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
814
815 /* Just want the 6 most-significant bits. */
816 h = h >> 26;
817
818 hashes[ h / 32 ] |= (1 << (h % 32));
819 cfg |= ETH_CFG_MTI;
820 }
821 ETHER_NEXT_MULTI(step, enm);
822 nma++;
823 }
824 ETHER_UNLOCK(ec);
825
826 // program...
827 DPRINTFN(1,("%s: en0 %02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__,
828 sc->sc_enaddr[0], sc->sc_enaddr[1], sc->sc_enaddr[2],
829 sc->sc_enaddr[3], sc->sc_enaddr[4], sc->sc_enaddr[5]));
830 EMAC_WRITE(ETH_SA1L, (sc->sc_enaddr[3] << 24)
831 | (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[1] << 8)
832 | (sc->sc_enaddr[0]));
833 EMAC_WRITE(ETH_SA1H, (sc->sc_enaddr[5] << 8)
834 | (sc->sc_enaddr[4]));
835 if (nma > 1) {
836 DPRINTFN(1,("%s: en1 %02x:%02x:%02x:%02x:%02x:%02x\n",
837 __FUNCTION__,
838 ias[0][0], ias[0][1], ias[0][2],
839 ias[0][3], ias[0][4], ias[0][5]));
840 EMAC_WRITE(ETH_SA2L, (ias[0][3] << 24)
841 | (ias[0][2] << 16) | (ias[0][1] << 8)
842 | (ias[0][0]));
843 EMAC_WRITE(ETH_SA2H, (ias[0][4] << 8)
844 | (ias[0][5]));
845 }
846 if (nma > 2) {
847 DPRINTFN(1,("%s: en2 %02x:%02x:%02x:%02x:%02x:%02x\n",
848 __FUNCTION__,
849 ias[1][0], ias[1][1], ias[1][2],
850 ias[1][3], ias[1][4], ias[1][5]));
851 EMAC_WRITE(ETH_SA3L, (ias[1][3] << 24)
852 | (ias[1][2] << 16) | (ias[1][1] << 8)
853 | (ias[1][0]));
854 EMAC_WRITE(ETH_SA3H, (ias[1][4] << 8)
855 | (ias[1][5]));
856 }
857 if (nma > 3) {
858 DPRINTFN(1,("%s: en3 %02x:%02x:%02x:%02x:%02x:%02x\n",
859 __FUNCTION__,
860 ias[2][0], ias[2][1], ias[2][2],
861 ias[2][3], ias[2][4], ias[2][5]));
862 EMAC_WRITE(ETH_SA3L, (ias[2][3] << 24)
863 | (ias[2][2] << 16) | (ias[2][1] << 8)
864 | (ias[2][0]));
865 EMAC_WRITE(ETH_SA3H, (ias[2][4] << 8)
866 | (ias[2][5]));
867 }
868 EMAC_WRITE(ETH_HSH, hashes[0]);
869 EMAC_WRITE(ETH_HSL, hashes[1]);
870 EMAC_WRITE(ETH_CFG, cfg);
871 EMAC_WRITE(ETH_CTL, ctl | ETH_CTL_RE);
872 }
873