1 /* $NetBSD: dpclock.c,v 1.7 2020/01/02 23:51:48 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2001 Erik Reid
5 * Copyright (c) 2001 Rafal K. Boni
6 * Copyright (c) 2001 Christopher Sekiya
7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
8 * All rights reserved.
9 *
10 * Portions of this code are derived from software contributed to The
11 * NetBSD Foundation by Jason R. Thorpe of the Numerical Aerospace
12 * Simulation Facility, NASA Ames Research Center.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/systm.h>
40 #include <sys/device.h>
41
42 #include <sys/bus.h>
43 #include <machine/autoconf.h>
44 #include <machine/sysconf.h>
45 #include <machine/machtype.h>
46
47 #include <dev/clock_subr.h>
48 #include <sgimips/dev/dp8573areg.h>
49
50 #include <sgimips/sgimips/clockvar.h>
51
52 struct dpclock_softc {
53 struct todr_chip_handle sc_todrch;
54
55 /* RTC registers */
56 bus_space_tag_t sc_rtct;
57 bus_space_handle_t sc_rtch;
58 int sc_offset;
59 };
60
61 static int dpclock_match(device_t, cfdata_t, void *);
62 static void dpclock_attach(device_t, device_t, void *);
63 static int dpclock_gettime_ymdhms(struct todr_chip_handle *,
64 struct clock_ymdhms *);
65 static int dpclock_settime_ymdhms(struct todr_chip_handle *,
66 struct clock_ymdhms *);
67
68 CFATTACH_DECL_NEW(dpclock, sizeof(struct dpclock_softc),
69 dpclock_match, dpclock_attach, NULL, NULL);
70
71 static int
dpclock_match(device_t parent,cfdata_t cf,void * aux)72 dpclock_match(device_t parent, cfdata_t cf, void *aux)
73 {
74 struct mainbus_attach_args *ma = aux;
75
76 switch (mach_type) {
77 case MACH_SGI_IP6 | MACH_SGI_IP10:
78 if (ma->ma_addr == 0x1fbc0000)
79 return (1);
80 break;
81
82 case MACH_SGI_IP12:
83 case MACH_SGI_IP20:
84 if (ma->ma_addr == 0x1fb80e00)
85 return (1);
86 break;
87 }
88
89 return (0);
90 }
91
92 static void
writereg(struct dpclock_softc * sc,uint32_t reg,uint8_t val)93 writereg(struct dpclock_softc *sc, uint32_t reg, uint8_t val)
94 {
95 bus_space_write_1(sc->sc_rtct, sc->sc_rtch,
96 (reg << 2) + sc->sc_offset, val);
97 }
98
99 static uint8_t
readreg(struct dpclock_softc * sc,uint32_t reg)100 readreg(struct dpclock_softc *sc, uint32_t reg)
101 {
102 return bus_space_read_1(sc->sc_rtct, sc->sc_rtch,
103 (reg << 2) + sc->sc_offset);
104 }
105
106 static void
dpclock_attach(device_t parent,device_t self,void * aux)107 dpclock_attach(device_t parent, device_t self, void *aux)
108 {
109 struct dpclock_softc *sc = device_private(self);
110 struct mainbus_attach_args *ma = aux;
111 int err;
112
113 printf("\n");
114
115 sc->sc_rtct = normal_memt;
116 /*
117 * All machines have one byte register per word. IP6/IP10 use
118 * the MSB, others the LSB.
119 */
120 if (mach_type == MACH_SGI_IP12 || mach_type == MACH_SGI_IP20)
121 sc->sc_offset = 3;
122 else
123 sc->sc_offset = 0;
124
125 if ((err = bus_space_map(sc->sc_rtct, ma->ma_addr, 0x1ffff,
126 BUS_SPACE_MAP_LINEAR, &sc->sc_rtch)) != 0) {
127 printf(": unable to map RTC registers, error = %d\n", err);
128 return;
129 }
130
131 sc->sc_todrch.cookie = sc;
132 sc->sc_todrch.todr_gettime = NULL;
133 sc->sc_todrch.todr_settime = NULL;
134 sc->sc_todrch.todr_gettime_ymdhms = dpclock_gettime_ymdhms;
135 sc->sc_todrch.todr_settime_ymdhms = dpclock_settime_ymdhms;
136 sc->sc_todrch.todr_setwen = NULL;
137
138 todr_attach(&sc->sc_todrch);
139 }
140
141 /*
142 * Get the time of day, based on the clock's value and/or the base value.
143 */
144 static int
dpclock_gettime_ymdhms(struct todr_chip_handle * todrch,struct clock_ymdhms * dt)145 dpclock_gettime_ymdhms(struct todr_chip_handle *todrch, struct clock_ymdhms *dt)
146 {
147 struct dpclock_softc *sc = (struct dpclock_softc *)todrch->cookie;
148 int s;
149 u_int8_t i, j;
150 u_int8_t regs[32];
151
152 s = splhigh();
153 i = readreg(sc, DP8573A_TIMESAVE_CTL);
154 j = i | DP8573A_TIMESAVE_CTL_EN;
155 writereg(sc, DP8573A_TIMESAVE_CTL, j);
156 writereg(sc, DP8573A_TIMESAVE_CTL, i);
157 splx(s);
158
159 for (i = 0; i < 32; i++)
160 regs[i] = readreg(sc, i);
161
162 dt->dt_sec = bcdtobin(regs[DP8573A_SAVE_SEC]);
163 dt->dt_min = bcdtobin(regs[DP8573A_SAVE_MIN]);
164
165 if (regs[DP8573A_RT_MODE] & DP8573A_RT_MODE_1224) {
166 dt->dt_hour = bcdtobin(regs[DP8573A_SAVE_HOUR] &
167 DP8573A_HOUR_12HR_MASK) +
168 ((regs[DP8573A_SAVE_HOUR] & DP8573A_RT_MODE_1224) ? 0 : 12);
169
170 /*
171 * In AM/PM mode, hour range is 01-12, so adding in 12 hours
172 * for PM gives us 01-24, whereas we want 00-23, so map hour
173 * 24 to hour 0.
174 */
175
176 if (dt->dt_hour == 24)
177 dt->dt_hour = 0;
178 } else {
179 dt->dt_hour = bcdtobin(regs[DP8573A_SAVE_HOUR] &
180 DP8573A_HOUR_24HR_MASK);
181 }
182
183 dt->dt_wday = bcdtobin(regs[DP8573A_DOW]); /* Not from time saved */
184 dt->dt_day = bcdtobin(regs[DP8573A_SAVE_DOM]);
185 dt->dt_mon = bcdtobin(regs[DP8573A_SAVE_MONTH]);
186 dt->dt_year = FROM_IRIX_YEAR(bcdtobin(regs[DP8573A_YEAR]));
187
188 return (0);
189 }
190
191 /*
192 * Reset the TODR based on the time value.
193 */
194 static int
dpclock_settime_ymdhms(struct todr_chip_handle * todrch,struct clock_ymdhms * dt)195 dpclock_settime_ymdhms(struct todr_chip_handle *todrch, struct clock_ymdhms *dt)
196 {
197 struct dpclock_softc *sc = (struct dpclock_softc *)todrch->cookie;
198 int s;
199 u_int8_t i, j;
200 u_int8_t regs[32];
201
202 s = splhigh();
203 i = readreg(sc, DP8573A_TIMESAVE_CTL);
204 j = i | DP8573A_TIMESAVE_CTL_EN;
205 writereg(sc, DP8573A_TIMESAVE_CTL, j);
206 writereg(sc, DP8573A_TIMESAVE_CTL, i);
207 splx(s);
208
209 for (i = 0; i < 32; i++)
210 regs[i] = readreg(sc, i);
211
212 regs[DP8573A_SUBSECOND] = 0;
213 regs[DP8573A_SECOND] = bintobcd(dt->dt_sec);
214 regs[DP8573A_MINUTE] = bintobcd(dt->dt_min);
215 regs[DP8573A_HOUR] = bintobcd(dt->dt_hour) & DP8573A_HOUR_24HR_MASK;
216 regs[DP8573A_DOW] = bintobcd(dt->dt_wday);
217 regs[DP8573A_DOM] = bintobcd(dt->dt_day);
218 regs[DP8573A_MONTH] = bintobcd(dt->dt_mon);
219 regs[DP8573A_YEAR] = bintobcd(TO_IRIX_YEAR(dt->dt_year));
220
221 s = splhigh();
222 i = readreg(sc, DP8573A_RT_MODE);
223 j = i & ~DP8573A_RT_MODE_CLKSS;
224 writereg(sc, DP8573A_RT_MODE, j);
225
226 for (i = 0; i < 10; i++)
227 writereg(sc, DP8573A_COUNTERS +i, regs[DP8573A_COUNTERS + i]);
228
229 writereg(sc, DP8573A_RT_MODE, i);
230 splx(s);
231
232 return (0);
233 }
234