1 /* $NetBSD: if_we_vme.c,v 1.4 2014/10/18 08:33:25 snj Exp $ */
2
3 /*-
4 * Copyright (c) 1997, 1998, 2010 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
35 * adapters.
36 *
37 * Copyright (c) 1994, 1995 Charles M. Hannum. All rights reserved.
38 *
39 * Copyright (C) 1993, David Greenman. This software may be used, modified,
40 * copied, distributed, and sold, in both source and binary form provided that
41 * the above copyright and these terms are retained. Under no circumstances is
42 * the author responsible for the proper functioning of this software, nor does
43 * the author assume any responsibility for damages incurred with its use.
44 */
45
46 /*
47 * Device driver for the SMC Elite Ultra (8216) with SMC_TT VME-ISA bridge.
48 * Based on:
49 * NetBSD: if_we_isa.c,v 1.20 2008/04/28 20:23:52 martin Exp
50 */
51
52 #include <sys/cdefs.h>
53 __KERNEL_RCSID(0, "$NetBSD: if_we_vme.c,v 1.4 2014/10/18 08:33:25 snj Exp $");
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/device.h>
58 #include <sys/socket.h>
59 #include <sys/mbuf.h>
60 #include <sys/syslog.h>
61
62 #include <net/if.h>
63 #include <net/if_dl.h>
64 #include <net/if_types.h>
65 #include <net/if_media.h>
66
67 #include <net/if_ether.h>
68
69 #include <sys/bus.h>
70 #include <sys/intr.h>
71
72 #include <machine/cpu.h>
73 #include <machine/iomap.h>
74 #include <machine/scu.h>
75
76 #include <atari/vme/vmevar.h>
77
78 #include <dev/ic/dp8390reg.h>
79 #include <dev/ic/dp8390var.h>
80 #include <dev/ic/wereg.h>
81 #include <dev/ic/wevar.h>
82
83 /* #define WE_DEBUG */
84 #ifdef WE_DEBUG
85 #define DPRINTF(x) printf x
86 #else
87 #define DPRINTF(x) /**/
88 #endif
89
90 /* VME space mapped by SMC_TT VME-ISA bridge */
91 #define SMCTT_MEM_BASE 0xFE000000 /* base for shared memory space */
92 #define SMCTT_IOE_BASE 0xFE200000 /* base for I/O ports at even address */
93 #define SMCTT_IOO_BASE 0xFE300000 /* base for I/O ports at odd address */
94
95 #define SMCTT_IO_OFFSET (SMCTT_IOO_BASE - SMCTT_IOE_BASE)
96
97 /* default SMC8216 settings for SMC_TT specified by a jumper switch at No.2 */
98 #define SMCTT_MEM_ADDR 0xD0000
99 #define SMCTT_IO_ADDR 0x280
100
101 /* SMC_TT uses IRQ4 on VME, IRQ3 on ISA, and interrupt vector 0xAA */
102 #define SMCTT_VME_IRQ 4
103 #define SMCTT_ISA_IRQ 3
104 #define SMCTT_VECTOR 0xAA
105
106 static int we_vme_probe(device_t, cfdata_t , void *);
107 static void we_vme_attach(device_t, device_t, void *);
108
109 static uint8_t smctt_bus_space_read_1(bus_space_tag_t, bus_space_handle_t,
110 bus_size_t);
111 static void smctt_bus_space_write_1(bus_space_tag_t, bus_space_handle_t,
112 bus_size_t, uint8_t);
113 static int smctt_bus_space_peek_1(bus_space_tag_t, bus_space_handle_t,
114 bus_size_t);
115
116 struct we_vme_softc {
117 struct we_softc sc_we;
118 struct atari_bus_space sc_bs;
119 };
120
121 CFATTACH_DECL_NEW(we_vme, sizeof(struct we_vme_softc),
122 we_vme_probe, we_vme_attach, NULL, NULL);
123
124 static const int we_790_irq[] = {
125 -1, 9, 3, 5, 7, 10, 11, 15,
126 };
127
128 static int
we_vme_probe(device_t parent,cfdata_t cf,void * aux)129 we_vme_probe(device_t parent, cfdata_t cf, void *aux)
130 {
131 struct vme_attach_args *va = aux;
132 struct atari_bus_space t;
133 bus_space_tag_t asict, memt;
134 bus_space_handle_t asich, asich1, memh;
135 bus_size_t memsize = 0;
136 bool asich_valid, asich1_valid, memh_valid;
137 int i, rv;
138 uint8_t sum, reg, type, hwr;
139
140 rv = 0;
141 asich_valid = false;
142 asich1_valid = false;
143 memh_valid = false;
144
145 if (va->va_iobase != IOBASEUNK &&
146 va->va_iobase != SMCTT_IOE_BASE + SMCTT_IO_ADDR)
147 return 0;
148 if (va->va_maddr != IOBASEUNK &&
149 va->va_maddr != SMCTT_MEM_BASE + SMCTT_MEM_ADDR)
150 return 0;
151 if (va->va_irq != IRQUNK &&
152 va->va_irq != SMCTT_VME_IRQ)
153 return 0;
154
155 /* SMC_TT has a bit weird I/O address mappings */
156 asict = beb_alloc_bus_space_tag(&t);
157 /* XXX setup only simple byte functions used in MI we(4) driver */
158 asict->abs_r_1 = smctt_bus_space_read_1;
159 asict->abs_w_1 = smctt_bus_space_write_1;
160 asict->abs_p_1 = smctt_bus_space_peek_1;
161
162 /*
163 * Only 16 bit accesses are allowed for memory space on SMC_TT,
164 * but MI we(4) uses them on 16 bit mode.
165 */
166 memt = va->va_memt;
167
168 /* Attempt to map the device. */
169 if (bus_space_map(asict, SMCTT_IOE_BASE + SMCTT_IO_ADDR, WE_NPORTS,
170 0, &asich) != 0) {
171 DPRINTF(("%s: failed to map even I/O space", __func__));
172 goto out;
173 }
174 asich_valid = true;
175
176 if (bus_space_map(asict, SMCTT_IOO_BASE + SMCTT_IO_ADDR, WE_NPORTS,
177 0, &asich1) != 0) {
178 DPRINTF(("%s: failed to map odd I/O space", __func__));
179 goto out;
180 }
181 asich1_valid = true;
182
183 /* XXX abuse stride for offset of odd ports from even ones */
184 asict->stride =
185 (vaddr_t)bus_space_vaddr(asict, asich1) -
186 (vaddr_t)bus_space_vaddr(asict, asich);
187
188 /* check if register regions are valid */
189 if (bus_space_peek_1(asict, asich, WE_PROM + 0) == 0 ||
190 bus_space_peek_1(asict, asich, WE_PROM + 1) == 0)
191 goto out;
192
193 /*
194 * Attempt to do a checksum over the station address PROM.
195 * If it fails, it's probably not an SMC_TT board.
196 */
197 DPRINTF(("%s: WE_PROM: ", __func__));
198 sum = 0;
199 for (i = 0; i < 8; i++) {
200 reg = bus_space_read_1(asict, asich, WE_PROM + i);
201 DPRINTF(("%02x ", reg));
202 sum += reg;
203 }
204 DPRINTF(("\n"));
205 DPRINTF(("%s: WE_ROM_SUM: 0x%02x\n", __func__, sum));
206
207 if (sum != WE_ROM_CHECKSUM_TOTAL)
208 goto out;
209
210 /*
211 * Reset the card to force it into a known state.
212 */
213 bus_space_write_1(asict, asich, WE_MSR, WE_MSR_RST);
214 delay(100);
215
216 bus_space_write_1(asict, asich, WE_MSR,
217 bus_space_read_1(asict, asich, WE_MSR) & ~WE_MSR_RST);
218
219 /* Wait in case the card is reading its EEPROM. */
220 delay(5000);
221
222 /*
223 * Check card type.
224 */
225 type = bus_space_read_1(asict, asich, WE_CARD_ID);
226 /* Assume SMT_TT has only 8216 */
227 if (type != WE_TYPE_SMC8216C && type != WE_TYPE_SMC8216T)
228 goto out;
229
230 hwr = bus_space_read_1(asict, asich, WE790_HWR);
231 bus_space_write_1(asict, asich, WE790_HWR, hwr | WE790_HWR_SWH);
232 switch (bus_space_read_1(asict, asich, WE790_RAR) & WE790_RAR_SZ64) {
233 case WE790_RAR_SZ64:
234 memsize = 65536;
235 break;
236 case WE790_RAR_SZ32:
237 memsize = 32768;
238 break;
239 case WE790_RAR_SZ16:
240 memsize = 16384;
241 break;
242 case WE790_RAR_SZ8:
243 memsize = 8192;
244 break;
245 default:
246 memsize = 16384;
247 break;
248 }
249 bus_space_write_1(asict, asich, WE790_HWR, hwr);
250
251 /* Attempt to map the memory space. */
252 if (bus_space_map(memt, SMCTT_MEM_BASE + SMCTT_MEM_ADDR, memsize,
253 0, &memh) != 0) {
254 DPRINTF(("%s: failed to map shared memory", __func__));
255 goto out;
256 }
257 memh_valid = true;
258
259 /* check if memory region is valid */
260 if (bus_space_peek_2(memt, memh, 0) == 0)
261 goto out;
262
263 /*
264 * Check the assigned interrupt number from the card.
265 */
266
267 /* Assemble together the encoded interrupt number. */
268 hwr = bus_space_read_1(asict, asich, WE790_HWR);
269 bus_space_write_1(asict, asich, WE790_HWR, hwr | WE790_HWR_SWH);
270
271 reg = bus_space_read_1(asict, asich, WE790_GCR);
272 i = ((reg & WE790_GCR_IR2) >> 4) |
273 ((reg & (WE790_GCR_IR1|WE790_GCR_IR0)) >> 2);
274 bus_space_write_1(asict, asich, WE790_HWR, hwr & ~WE790_HWR_SWH);
275
276 if (we_790_irq[i] != SMCTT_ISA_IRQ) {
277 DPRINTF(("%s: wrong IRQ (%d); check jumper settings\n",
278 __func__, we_790_irq[i]));
279 goto out;
280 }
281
282 /* So, we say we've found it! */
283 va->va_iobase = SMCTT_IOE_BASE + SMCTT_IO_ADDR;
284 va->va_iosize = WE_NPORTS;
285 va->va_maddr = SMCTT_MEM_BASE + SMCTT_MEM_ADDR;
286 va->va_msize = memsize;
287 va->va_irq = SMCTT_VME_IRQ;
288
289 rv = 1;
290
291 out:
292 if (asich_valid)
293 bus_space_unmap(asict, asich, WE_NPORTS);
294 if (asich1_valid)
295 bus_space_unmap(asict, asich1, WE_NPORTS);
296 if (memh_valid)
297 bus_space_unmap(memt, memh, memsize);
298 return rv;
299 }
300
301 void
we_vme_attach(device_t parent,device_t self,void * aux)302 we_vme_attach(device_t parent, device_t self, void *aux)
303 {
304 struct we_vme_softc *wvsc = device_private(self);
305 struct we_softc *wsc = &wvsc->sc_we;
306 struct dp8390_softc *sc = &wsc->sc_dp8390;
307 struct vme_attach_args *va = aux;
308 bus_space_tag_t nict, asict, memt;
309 bus_space_handle_t nich, asich, asich1, memh;
310 const char *typestr;
311
312 aprint_normal("\n");
313
314 sc->sc_dev = self;
315
316 /* See comments in the above probe function */
317 asict = beb_alloc_bus_space_tag(&wvsc->sc_bs);
318 asict->abs_r_1 = smctt_bus_space_read_1;
319 asict->abs_w_1 = smctt_bus_space_write_1;
320 nict = asict;
321
322 memt = va->va_memt;
323
324 /* Map the device. */
325 if (bus_space_map(asict, va->va_iobase, WE_NPORTS, 0, &asich) != 0) {
326 aprint_error_dev(self, "can't map even I/O space\n");
327 return;
328 }
329 if (bus_space_map(asict, va->va_iobase + SMCTT_IO_OFFSET, WE_NPORTS,
330 0, &asich1) != 0) {
331 aprint_error_dev(self, "can't map odd I/O space\n");
332 goto out;
333 }
334 asict->stride =
335 (vaddr_t)bus_space_vaddr(asict, asich1) -
336 (vaddr_t)bus_space_vaddr(asict, asich);
337
338 if (bus_space_subregion(asict, asich, WE_NIC_OFFSET, WE_NIC_NPORTS,
339 &nich) != 0) {
340 aprint_error_dev(self, "can't subregion I/O space\n");
341 goto out1;
342 }
343
344 /* Map memory space. */
345 if (bus_space_map(memt, va->va_maddr, va->va_msize, 0, &memh) != 0) {
346 aprint_error_dev(self, "can't map shared memory\n");
347 goto out1;
348 }
349
350 wsc->sc_asict = asict;
351 wsc->sc_asich = asich;
352
353 sc->sc_regt = nict;
354 sc->sc_regh = nich;
355
356 sc->sc_buft = memt;
357 sc->sc_bufh = memh;
358
359 wsc->sc_maddr = va->va_maddr & 0xfffff;
360 sc->mem_size = va->va_msize;
361
362 /* Interface is always enabled. */
363 sc->sc_enabled = 1;
364
365 /* SMC_TT assumes SMC8216 */
366 sc->is790 = 1;
367
368 /* SMC_TT supports only 16 bit access for shared memory */
369 wsc->sc_flags |= WE_16BIT_ENABLE;
370
371 /* Appeal the Atari spirit :-) */
372 typestr = "SMC8216 with SMC_TT VME-ISA bridge";
373
374 if (we_config(self, wsc, typestr) != 0)
375 goto out2;
376
377 /*
378 * Enable the configured interrupt.
379 */
380 bus_space_write_1(asict, asich, WE790_ICR,
381 bus_space_read_1(asict, asich, WE790_ICR) | WE790_ICR_EIL);
382
383 /* Establish interrupt handler. */
384 wsc->sc_ih = intr_establish(SMCTT_VECTOR - 64, USER_VEC, 0,
385 (hw_ifun_t)dp8390_intr, sc);
386 if (wsc->sc_ih == NULL) {
387 aprint_error_dev(self, "can't establish interrupt\n");
388 goto out2;
389 }
390 /*
391 * Unmask the VME interrupt we're on.
392 */
393 if ((machineid & ATARI_TT) != 0)
394 SCU->vme_mask |= 1 << va->va_irq;
395
396 return;
397
398 out2:
399 bus_space_unmap(memt, memh, va->va_msize);
400 out1:
401 bus_space_unmap(asict, asich1, WE_NPORTS);
402 out:
403 bus_space_unmap(asict, asich, WE_NPORTS);
404 }
405
406 static uint8_t
smctt_bus_space_read_1(bus_space_tag_t bt,bus_space_handle_t bh,bus_size_t reg)407 smctt_bus_space_read_1(bus_space_tag_t bt, bus_space_handle_t bh,
408 bus_size_t reg)
409 {
410 uint8_t rv;
411
412 if ((reg & 0x01) != 0) {
413 /* odd address space */
414 rv = *(volatile uint8_t *)(bh + bt->stride + (reg & ~0x01));
415 } else {
416 /* even address space */
417 rv = *(volatile uint8_t *)(bh + reg);
418 }
419
420 return rv;
421 }
422
423 static void
smctt_bus_space_write_1(bus_space_tag_t bt,bus_space_handle_t bh,bus_size_t reg,uint8_t val)424 smctt_bus_space_write_1(bus_space_tag_t bt, bus_space_handle_t bh,
425 bus_size_t reg, uint8_t val)
426 {
427
428 if ((reg & 0x01) != 0) {
429 /* odd address space */
430 *(volatile uint8_t *)(bh + bt->stride + (reg & ~0x01)) = val;
431 } else {
432 /* even address space */
433 *(volatile uint8_t *)(bh + reg) = val;
434 }
435 }
436
437 static int
smctt_bus_space_peek_1(bus_space_tag_t bt,bus_space_handle_t bh,bus_size_t reg)438 smctt_bus_space_peek_1(bus_space_tag_t bt, bus_space_handle_t bh,
439 bus_size_t reg)
440 {
441 uint8_t *va;
442
443 if ((reg & 0x01) != 0) {
444 /* odd address space */
445 va = (uint8_t *)(bh + bt->stride + (reg & ~0x01));
446 } else {
447 /* even address space */
448 va = (uint8_t *)(bh + reg);
449 }
450
451 return !badbaddr(va, sizeof(uint8_t));
452 }
453