1 /* $NetBSD: zynq_gpio.c,v 1.4 2022/10/31 23:04:50 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: zynq_gpio.c,v 1.4 2022/10/31 23:04:50 jmcneill Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bitops.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/gpio.h>
37 #include <sys/intr.h>
38 #include <sys/kmem.h>
39 #include <sys/lwp.h>
40 #include <sys/mutex.h>
41 #include <sys/systm.h>
42
43 #include <dev/fdt/fdtvar.h>
44 #include <dev/gpio/gpiovar.h>
45
46 #define ZYNQ_GPIO_NPINS (4 * 32)
47
48 #define MASK_DATA_REG(pin) (0x000 + 0x4 * ((pin) / 16))
49 #define DATA_RO_REG(pin) (0x060 + 0x4 * ((pin) / 32))
50 #define DATA_RO_BIT(pin) __BIT((pin) % 32)
51 #define DIRM_REG(pin) (0x204 + 0x40 * ((pin) / 32))
52 #define DIRM_BIT(pin) __BIT((pin) % 32)
53 #define OEN_REG(pin) (0x208 + 0x40 * ((pin) / 32))
54 #define OEN_BIT(pin) __BIT((pin) % 32)
55
56 static const struct device_compatible_entry compat_data[] = {
57 { .compat = "xlnx,zynq-gpio-1.0" },
58 DEVICE_COMPAT_EOL
59 };
60
61 struct zynq_gpio_softc {
62 device_t sc_dev;
63 bus_space_tag_t sc_bst;
64 bus_space_handle_t sc_bsh;
65 kmutex_t sc_lock;
66 struct gpio_chipset_tag sc_gp;
67 gpio_pin_t sc_pins[ZYNQ_GPIO_NPINS];
68 device_t sc_gpiodev;
69 };
70
71 struct zynq_gpio_pin {
72 struct zynq_gpio_softc *pin_sc;
73 u_int pin_nr;
74 int pin_flags;
75 bool pin_actlo;
76 };
77
78 #define RD4(sc, reg) \
79 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
80 #define WR4(sc, reg, val) \
81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
82
83 static int zynq_gpio_match(device_t, cfdata_t, void *);
84 static void zynq_gpio_attach(device_t, device_t, void *);
85
86 static int zynq_gpio_pin_read(void *, int);
87 static void zynq_gpio_pin_write(void *, int, int);
88
89 CFATTACH_DECL_NEW(zynqgpio, sizeof(struct zynq_gpio_softc),
90 zynq_gpio_match, zynq_gpio_attach, NULL, NULL);
91
92 static int
zynq_gpio_ctl(struct zynq_gpio_softc * sc,u_int pin,int flags)93 zynq_gpio_ctl(struct zynq_gpio_softc *sc, u_int pin, int flags)
94 {
95 uint32_t dirm, oen;
96
97 KASSERT(mutex_owned(&sc->sc_lock));
98
99 dirm = RD4(sc, DIRM_REG(pin));
100 oen = RD4(sc, OEN_REG(pin));
101 if ((flags & GPIO_PIN_INPUT) != 0) {
102 dirm &= ~DIRM_BIT(pin);
103 oen &= ~OEN_BIT(pin);
104 } else if ((flags & GPIO_PIN_OUTPUT) != 0) {
105 dirm |= DIRM_BIT(pin);
106 oen |= OEN_BIT(pin);
107 }
108 WR4(sc, OEN_REG(pin), oen);
109 WR4(sc, DIRM_REG(pin), dirm);
110
111 return 0;
112 }
113
114 static void *
zynq_gpio_acquire(device_t dev,const void * data,size_t len,int flags)115 zynq_gpio_acquire(device_t dev, const void *data, size_t len, int flags)
116 {
117 struct zynq_gpio_softc * const sc = device_private(dev);
118 struct zynq_gpio_pin *gpin;
119 const u_int *gpio = data;
120 int error;
121
122 if (len != 12)
123 return NULL;
124
125 const uint8_t pin = be32toh(gpio[1]) & 0xff;
126 const bool actlo = be32toh(gpio[2]) & 1;
127
128 if (pin >= __arraycount(sc->sc_pins))
129 return NULL;
130
131 mutex_enter(&sc->sc_lock);
132 error = zynq_gpio_ctl(sc, pin, flags);
133 mutex_exit(&sc->sc_lock);
134
135 if (error != 0)
136 return NULL;
137
138 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP);
139 gpin->pin_sc = sc;
140 gpin->pin_nr = pin;
141 gpin->pin_flags = flags;
142 gpin->pin_actlo = actlo;
143
144 return gpin;
145 }
146
147 static void
zynq_gpio_release(device_t dev,void * priv)148 zynq_gpio_release(device_t dev, void *priv)
149 {
150 struct zynq_gpio_softc * const sc = device_private(dev);
151 struct zynq_gpio_pin *pin = priv;
152
153 mutex_enter(&sc->sc_lock);
154 zynq_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT);
155 mutex_exit(&sc->sc_lock);
156
157 kmem_free(pin, sizeof(*pin));
158 }
159
160 static int
zynq_gpio_read(device_t dev,void * priv,bool raw)161 zynq_gpio_read(device_t dev, void *priv, bool raw)
162 {
163 struct zynq_gpio_softc * const sc = device_private(dev);
164 struct zynq_gpio_pin *pin = priv;
165 int val;
166
167 KASSERT(sc == pin->pin_sc);
168
169 val = zynq_gpio_pin_read(sc, pin->pin_nr);
170 if (!raw && pin->pin_actlo)
171 val = !val;
172
173 return val;
174 }
175
176 static void
zynq_gpio_write(device_t dev,void * priv,int val,bool raw)177 zynq_gpio_write(device_t dev, void *priv, int val, bool raw)
178 {
179 struct zynq_gpio_softc * const sc = device_private(dev);
180 struct zynq_gpio_pin *pin = priv;
181
182 KASSERT(sc == pin->pin_sc);
183
184 if (!raw && pin->pin_actlo)
185 val = !val;
186
187 zynq_gpio_pin_write(sc, pin->pin_nr, val);
188 }
189
190 static struct fdtbus_gpio_controller_func zynq_gpio_funcs = {
191 .acquire = zynq_gpio_acquire,
192 .release = zynq_gpio_release,
193 .read = zynq_gpio_read,
194 .write = zynq_gpio_write,
195 };
196
197 static int
zynq_gpio_pin_read(void * priv,int pin)198 zynq_gpio_pin_read(void *priv, int pin)
199 {
200 struct zynq_gpio_softc * const sc = priv;
201 uint32_t data;
202 int val;
203
204 KASSERT(pin < __arraycount(sc->sc_pins));
205
206 data = RD4(sc, DATA_RO_REG(pin));
207 val = __SHIFTOUT(data, DATA_RO_BIT(pin));
208
209 return val;
210 }
211
212 static void
zynq_gpio_pin_write(void * priv,int pin,int val)213 zynq_gpio_pin_write(void *priv, int pin, int val)
214 {
215 struct zynq_gpio_softc * const sc = priv;
216 uint32_t mask_data;
217
218 KASSERT(pin < __arraycount(sc->sc_pins));
219
220 mask_data = (0xffff & ~__BIT(pin % 16)) << 16;
221 if (val) {
222 mask_data |= __BIT(pin % 16);
223 }
224 WR4(sc, MASK_DATA_REG(pin), mask_data);
225 }
226
227 static void
zynq_gpio_pin_ctl(void * priv,int pin,int flags)228 zynq_gpio_pin_ctl(void *priv, int pin, int flags)
229 {
230 struct zynq_gpio_softc * const sc = priv;
231
232 KASSERT(pin < __arraycount(sc->sc_pins));
233
234 mutex_enter(&sc->sc_lock);
235 zynq_gpio_ctl(sc, pin, flags);
236 mutex_exit(&sc->sc_lock);
237 }
238
239 static void
zynq_gpio_attach_ports(struct zynq_gpio_softc * sc)240 zynq_gpio_attach_ports(struct zynq_gpio_softc *sc)
241 {
242 struct gpio_chipset_tag *gp = &sc->sc_gp;
243 struct gpiobus_attach_args gba;
244 u_int pin;
245
246 gp->gp_cookie = sc;
247 gp->gp_pin_read = zynq_gpio_pin_read;
248 gp->gp_pin_write = zynq_gpio_pin_write;
249 gp->gp_pin_ctl = zynq_gpio_pin_ctl;
250
251 for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) {
252 sc->sc_pins[pin].pin_num = pin;
253 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
254 sc->sc_pins[pin].pin_state = zynq_gpio_pin_read(sc, pin);
255 }
256
257 memset(&gba, 0, sizeof(gba));
258 gba.gba_gc = gp;
259 gba.gba_pins = sc->sc_pins;
260 gba.gba_npins = __arraycount(sc->sc_pins);
261 sc->sc_gpiodev = config_found(sc->sc_dev, &gba, NULL, CFARGS_NONE);
262 }
263
264 static int
zynq_gpio_match(device_t parent,cfdata_t cf,void * aux)265 zynq_gpio_match(device_t parent, cfdata_t cf, void *aux)
266 {
267 struct fdt_attach_args * const faa = aux;
268
269 return of_compatible_match(faa->faa_phandle, compat_data);
270 }
271
272 static void
zynq_gpio_attach(device_t parent,device_t self,void * aux)273 zynq_gpio_attach(device_t parent, device_t self, void *aux)
274 {
275 struct zynq_gpio_softc * const sc = device_private(self);
276 struct fdt_attach_args * const faa = aux;
277 const int phandle = faa->faa_phandle;
278 bus_addr_t addr;
279 bus_size_t size;
280
281 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
282 aprint_error(": couldn't get registers\n");
283 return;
284 }
285
286 sc->sc_dev = self;
287 sc->sc_bst = faa->faa_bst;
288 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
289 aprint_error(": couldn't map registers\n");
290 return;
291 }
292 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
293
294 aprint_naive("\n");
295 aprint_normal(": XGPIOPS\n");
296
297 fdtbus_register_gpio_controller(self, phandle, &zynq_gpio_funcs);
298
299 zynq_gpio_attach_ports(sc);
300 }
301