1 /* $NetBSD: s3c2800_intr.c,v 1.14 2022/09/27 06:36:43 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2002 Fujitsu Component Limited
5 * Copyright (c) 2002 Genetec Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of The Fujitsu Component Limited nor the name of
17 * Genetec corporation may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35 /*
36 * IRQ handler for Samsung S3C2800 processor.
37 * It has integrated interrupt controller.
38 */
39
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.14 2022/09/27 06:36:43 skrll Exp $");
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45
46 #include <sys/bus.h>
47 #include <machine/intr.h>
48
49 #include <arm/cpufunc.h>
50
51 #include <arm/s3c2xx0/s3c2800reg.h>
52 #include <arm/s3c2xx0/s3c2800var.h>
53
54 /*
55 * interrupt dispatch table.
56 */
57
58 struct s3c2xx0_intr_dispatch handler[ICU_LEN];
59
60 volatile int intr_mask; /* XXX: does this need to be volatile? */
61 volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */
62
63 /* interrupt masks for each level */
64 int s3c2xx0_imask[NIPL];
65 int s3c2xx0_ilevel[ICU_LEN];
66
67 vaddr_t intctl_base; /* interrupt controller registers */
68 #define icreg(offset) \
69 (*(volatile uint32_t *)(intctl_base+(offset)))
70
71 /*
72 * Clearing interrupt pending bits affects some built-in
73 * peripherals. For example, IIC starts transmitting next data when
74 * its interrupt pending bit is cleared.
75 * We need to leave those bits to peripheral handlers.
76 */
77 #define PENDING_CLEAR_MASK (~((1<<S3C2800_INT_IIC0)|(1<<S3C2800_INT_IIC1)))
78
79 /*
80 * called from irq_entry.
81 */
82 void s3c2800_irq_handler(struct clockframe *);
83 void
s3c2800_irq_handler(struct clockframe * frame)84 s3c2800_irq_handler(struct clockframe *frame)
85 {
86 uint32_t irqbits;
87 int irqno;
88 int saved_spl_level;
89
90 saved_spl_level = curcpl();
91
92 while ((irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK) != 0) {
93
94 for (irqno = ICU_LEN-1; irqno >= 0; --irqno)
95 if (irqbits & (1<<irqno))
96 break;
97
98 if (irqno < 0)
99 break;
100
101 /* raise spl to stop interrupts of lower priorities */
102 if (saved_spl_level < handler[irqno].level)
103 s3c2xx0_setipl(handler[irqno].level);
104
105 /* clear pending bit */
106 icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno);
107
108 enable_interrupts(I32_bit); /* allow nested interrupts */
109
110 (*handler[irqno].func) (
111 handler[irqno].cookie == 0
112 ? frame : handler[irqno].cookie);
113
114 disable_interrupts(I32_bit);
115
116 /* restore spl to that was when this interrupt happen */
117 s3c2xx0_setipl(saved_spl_level);
118 }
119
120 #ifdef __HAVE_FAST_SOFTINTS
121 cpu_dosoftints();
122 #endif
123 }
124
125 static const u_char s3c2800_ist[] = {
126 EXTINTR_LOW, /* NONE */
127 EXTINTR_FALLING, /* PULSE */
128 EXTINTR_FALLING, /* EDGE */
129 EXTINTR_LOW, /* LEVEL */
130 EXTINTR_HIGH,
131 EXTINTR_RISING,
132 EXTINTR_BOTH,
133 };
134
135 void *
s3c2800_intr_establish(int irqno,int level,int type,int (* func)(void *),void * cookie)136 s3c2800_intr_establish(int irqno, int level, int type,
137 int (* func) (void *), void *cookie)
138 {
139 int save;
140
141 if (irqno < 0 || irqno >= ICU_LEN ||
142 type < IST_NONE || IST_EDGE_BOTH < type)
143 panic("intr_establish: bogus irq or type");
144
145 save = disable_interrupts(I32_bit);
146
147 handler[irqno].cookie = cookie;
148 handler[irqno].func = func;
149 handler[irqno].level = level;
150
151 s3c2xx0_update_intr_masks(irqno, level);
152
153 if (irqno <= S3C2800_INT_EXT(7)) {
154 /*
155 * Update external interrupt control
156 */
157 uint32_t reg;
158 u_int trig;
159
160 trig = s3c2800_ist[type];
161
162 reg = bus_space_read_4(s3c2xx0_softc->sc_iot,
163 s3c2xx0_softc->sc_gpio_ioh,
164 GPIO_EXTINTR);
165
166 reg = reg & ~(0x0f << (4*irqno));
167 reg |= trig << (4*irqno);
168
169 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
170 GPIO_EXTINTR, reg);
171 }
172
173 s3c2xx0_setipl(curcpl());
174
175 restore_interrupts(save);
176
177 return (&handler[irqno]);
178 }
179
180
181 static void
init_interrupt_masks(void)182 init_interrupt_masks(void)
183 {
184 int i;
185
186 for (i = 0; i < NIPL; i++)
187 s3c2xx0_imask[i] = 0;
188 }
189
190 void
s3c2800_intr_init(struct s3c2800_softc * sc)191 s3c2800_intr_init(struct s3c2800_softc *sc)
192 {
193 intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot,
194 sc->sc_sx.sc_intctl_ioh);
195
196 s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK);
197
198 /* clear all pending interrupt */
199 icreg(INTCTL_SRCPND) = 0xffffffff;
200
201 init_interrupt_masks();
202
203 s3c2xx0_intr_init(handler, ICU_LEN);
204
205 }
206