1 /* $NetBSD: rk_spi.c,v 1.7 2021/05/15 08:46:00 mrg Exp $ */
2
3 /*
4 * Copyright (c) 2019 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Tobias Nygren.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: rk_spi.c,v 1.7 2021/05/15 08:46:00 mrg Exp $");
34
35 #include <sys/param.h>
36 #include <sys/device.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/intr.h>
40 #include <sys/kernel.h>
41 #include <sys/bitops.h>
42 #include <dev/spi/spivar.h>
43 #include <dev/fdt/fdtvar.h>
44 #include <arm/fdt/arm_fdtvar.h>
45
46 #define SPI_CTRLR0 0x00
47 #define SPI_CTRLR0_MTM __BIT(21)
48 #define SPI_CTRLR0_OPM __BIT(20)
49 #define SPI_CTRLR0_XFM __BITS(19, 18)
50 #define SPI_CTRLR0_FRF __BITS(17, 16)
51 #define SPI_CTRLR0_RSD __BITS(15, 14)
52 #define SPI_CTRLR0_BHT __BIT(13)
53 #define SPI_CTRLR0_FBM __BIT(12)
54 #define SPI_CTRLR0_EM __BIT(11)
55 #define SPI_CTRLR0_RW __BIT(10)
56 #define SPI_CTRLR0_CSM __BITS(9, 8)
57 #define SPI_CTRLR0_SCPOL __BIT(7)
58 #define SPI_CTRLR0_SCPH __BIT(6)
59 #define SPI_CTRLR0_CFS __BITS(5, 2)
60 #define SPI_CTRLR0_DFS __BITS(1, 0)
61 #define SPI_CTRLR0_DFS_4BIT 0x0
62 #define SPI_CTRLR0_DFS_8BIT 0x1
63 #define SPI_CTRLR0_DFS_16BIT 0x2
64
65 #define SPI_CTRLR1 0x04
66 #define SPI_CTRLR1_NDM __BITS(15, 0)
67
68 #define SPI_ENR 0x08
69 #define SPI_ENR_ENR __BIT(0)
70
71 #define SPI_SER 0x0c
72 #define SPI_SER_SER1 __BIT(1)
73 #define SPI_SER_SER0 __BIT(0)
74
75 #define SPI_BAUDR 0x10
76 #define SPI_BAUDR_BAUDR __BITS(15, 0)
77
78 #define SPI_TXFTLR 0x14
79 #define SPI_TXFTLR_TXFLTR __BITS(4, 0)
80
81 #define SPI_RXFTLR 0x18
82 #define SPI_RXFLTR_RXFLTR __BITS(4, 0)
83
84 #define SPI_TXFLR 0x1c
85 #define SPI_TXFLR_TXFLR __BITS(5, 0)
86
87 #define SPI_RXFLR 0x20
88 #define SPI_RXFLR_RXFLR __BITS(5, 0)
89
90 #define SPI_SR 0x24
91 #define SPI_SR_RFF __BIT(4)
92 #define SPI_SR_RFE __BIT(3)
93 #define SPI_SR_TFE __BIT(2)
94 #define SPI_SR_TFF __BIT(1)
95 #define SPI_SR_BSF __BIT(0)
96
97 #define SPI_IPR 0x28
98 #define SPI_IPR_IPR __BIT(0)
99
100 #define SPI_IMR 0x2c
101 #define SPI_IMR_RFFIM __BIT(4)
102 #define SPI_IMR_RFOIM __BIT(3)
103 #define SPI_IMR_RFUIM __BIT(2)
104 #define SPI_IMR_TFOIM __BIT(1)
105 #define SPI_IMR_TFEIM __BIT(0)
106
107 #define SPI_ISR 0x30
108 #define SPI_ISR_RFFIS __BIT(4)
109 #define SPI_ISR_RFOIS __BIT(3)
110 #define SPI_ISR_RFUIS __BIT(2)
111 #define SPI_ISR_TFOIS __BIT(1)
112 #define SPI_ISR_TFEIS __BIT(0)
113
114 #define SPI_RISR 0x34
115 #define SPI_RISR_RFFRIS __BIT(4)
116 #define SPI_RISR_RFORIS __BIT(3)
117 #define SPI_RISR_RFURIS __BIT(2)
118 #define SPI_RISR_TFORIS __BIT(1)
119 #define SPI_RISR_TFERIS __BIT(0)
120
121 #define SPI_ICR 0x38
122 #define SPI_ICR_CTFOI __BIT(3)
123 #define SPI_ICR_CRFOI __BIT(2)
124 #define SPI_ICR_CRFUI __BIT(1)
125 #define SPI_ICR_CCI __BIT(0)
126 #define SPI_ICR_ALL __BITS(3, 0)
127
128 #define SPI_DMACR 0x3c
129 #define SPI_DMACR_TDE __BIT(1)
130 #define SPI_DMACR_RDE __BIT(0)
131
132 #define SPI_DMATDLR 0x40
133 #define SPI_DMATDLR_TDL __BITS(4, 0)
134
135 #define SPI_DMARDLR 0x44
136 #define SPI_DMARDLR_RDL __BITS(4, 0)
137
138 #define SPI_TXDR 0x400
139 #define SPI_TXDR_TXDR __BITS(15, 0)
140
141 #define SPI_RXDR 0x800
142 #define SPI_RXDR_RXDR __BITS(15, 0)
143
144 #define SPI_FIFOLEN 32
145
146 static const struct device_compatible_entry compat_data[] = {
147 { .compat = "rockchip,rk3066-spi" },
148 { .compat = "rockchip,rk3328-spi" },
149 { .compat = "rockchip,rk3399-spi" },
150 DEVICE_COMPAT_EOL
151 };
152
153 struct rk_spi_softc {
154 device_t sc_dev;
155 bus_space_tag_t sc_bst;
156 bus_space_handle_t sc_bsh;
157 void *sc_ih;
158 u_int sc_spi_freq;
159 struct spi_controller sc_spi;
160 SIMPLEQ_HEAD(,spi_transfer) sc_q;
161 struct spi_transfer *sc_transfer;
162 struct spi_chunk *sc_rchunk, *sc_wchunk;
163 volatile bool sc_running;
164 };
165
166 #define SPIREG_READ(sc, reg) \
167 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
168 #define SPIREG_WRITE(sc, reg, val) \
169 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
170
171 static struct spi_controller *rk_spi_get_controller(device_t);
172 static int rk_spi_match(device_t, cfdata_t, void *);
173 static void rk_spi_attach(device_t, device_t, void *);
174
175 static int rk_spi_configure(void *, int, int, int);
176 static int rk_spi_transfer(void *, struct spi_transfer *);
177
178 static void rk_spi_txfifo_fill(struct rk_spi_softc * const, size_t);
179 static void rk_spi_rxfifo_drain(struct rk_spi_softc * const, size_t);
180 static void rk_spi_rxtx(struct rk_spi_softc * const);
181 static void rk_spi_set_interrupt_mask(struct rk_spi_softc * const);
182 static void rk_spi_start(struct rk_spi_softc * const);
183 static int rk_spi_intr(void *);
184
185 CFATTACH_DECL_NEW(rk_spi, sizeof(struct rk_spi_softc),
186 rk_spi_match, rk_spi_attach, NULL, NULL);
187
188 static const struct fdtbus_spi_controller_func rk_spi_funcs = {
189 .get_controller = rk_spi_get_controller
190 };
191
192 static struct spi_controller *
rk_spi_get_controller(device_t dev)193 rk_spi_get_controller(device_t dev)
194 {
195 struct rk_spi_softc * const sc = device_private(dev);
196
197 return &sc->sc_spi;
198 }
199
200 static int
rk_spi_match(device_t parent,cfdata_t cf,void * aux)201 rk_spi_match(device_t parent, cfdata_t cf, void *aux)
202 {
203 struct fdt_attach_args * const faa = aux;
204
205 return of_compatible_match(faa->faa_phandle, compat_data);
206 }
207
208 static void
rk_spi_attach(device_t parent,device_t self,void * aux)209 rk_spi_attach(device_t parent, device_t self, void *aux)
210 {
211 struct rk_spi_softc * const sc = device_private(self);
212 struct fdt_attach_args * const faa = aux;
213 const int phandle = faa->faa_phandle;
214 bus_addr_t addr;
215 bus_size_t size;
216 struct clk *sclk, *pclk;
217 char intrstr[128];
218
219 sc->sc_dev = self;
220 sc->sc_bst = faa->faa_bst;
221 SIMPLEQ_INIT(&sc->sc_q);
222
223 if ((sclk = fdtbus_clock_get(phandle, "spiclk")) == NULL
224 || clk_enable(sclk) != 0) {
225 aprint_error(": couldn't enable sclk\n");
226 return;
227 }
228
229 if ((pclk = fdtbus_clock_get(phandle, "apb_pclk")) == NULL
230 || clk_enable(pclk) != 0) {
231 aprint_error(": couldn't enable pclk\n");
232 return;
233 }
234
235 sc->sc_spi_freq = clk_get_rate(sclk);
236
237 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0
238 || bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
239 aprint_error(": couldn't map registers\n");
240 return;
241 }
242
243 SPIREG_WRITE(sc, SPI_ENR, 0);
244 SPIREG_WRITE(sc, SPI_IMR, 0);
245
246 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
247 aprint_error(": failed to decode interrupt\n");
248 return;
249 }
250
251 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 0,
252 rk_spi_intr, sc, device_xname(self));
253 if (sc->sc_ih == NULL) {
254 aprint_error(": unable to establish interrupt\n");
255 return;
256 }
257
258 aprint_naive("\n");
259 aprint_normal(": SPI\n");
260 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
261
262 sc->sc_spi.sct_cookie = sc;
263 sc->sc_spi.sct_configure = rk_spi_configure;
264 sc->sc_spi.sct_transfer = rk_spi_transfer;
265 sc->sc_spi.sct_nslaves = 2;
266
267 fdtbus_register_spi_controller(self, phandle, &rk_spi_funcs);
268 (void) fdtbus_attach_spibus(self, phandle, spibus_print);
269 }
270
271 static int
rk_spi_configure(void * cookie,int slave,int mode,int speed)272 rk_spi_configure(void *cookie, int slave, int mode, int speed)
273 {
274 struct rk_spi_softc * const sc = cookie;
275 uint32_t ctrlr0;
276 uint16_t divider;
277
278 divider = (sc->sc_spi_freq / speed) & ~1;
279 if (divider < 2) {
280 aprint_error_dev(sc->sc_dev,
281 "spi_clk %u is too low for speed %u, using speed %u\n",
282 sc->sc_spi_freq, speed, sc->sc_spi_freq / 2);
283 divider = 2;
284 }
285
286 if (slave >= sc->sc_spi.sct_nslaves)
287 return EINVAL;
288
289 ctrlr0 = SPI_CTRLR0_BHT | __SHIFTIN(SPI_CTRLR0_DFS_8BIT, SPI_CTRLR0_DFS);
290
291 switch (mode) {
292 case SPI_MODE_0:
293 ctrlr0 |= 0;
294 break;
295 case SPI_MODE_1:
296 ctrlr0 |= SPI_CTRLR0_SCPH;
297 break;
298 case SPI_MODE_2:
299 ctrlr0 |= SPI_CTRLR0_SCPOL;
300 break;
301 case SPI_MODE_3:
302 ctrlr0 |= SPI_CTRLR0_SCPH | SPI_CTRLR0_SCPOL;
303 break;
304 default:
305 return EINVAL;
306 }
307
308 SPIREG_WRITE(sc, SPI_ENR, 0);
309 SPIREG_WRITE(sc, SPI_SER, 0);
310 SPIREG_WRITE(sc, SPI_CTRLR0, ctrlr0);
311 SPIREG_WRITE(sc, SPI_BAUDR, divider);
312
313 SPIREG_WRITE(sc, SPI_DMACR, 0);
314 SPIREG_WRITE(sc, SPI_DMATDLR, 0);
315 SPIREG_WRITE(sc, SPI_DMARDLR, 0);
316
317 SPIREG_WRITE(sc, SPI_IPR, 0);
318 SPIREG_WRITE(sc, SPI_IMR, 0);
319 SPIREG_WRITE(sc, SPI_ICR, SPI_ICR_ALL);
320
321 SPIREG_WRITE(sc, SPI_ENR, 1);
322
323 return 0;
324 }
325
326 static int
rk_spi_transfer(void * cookie,struct spi_transfer * st)327 rk_spi_transfer(void *cookie, struct spi_transfer *st)
328 {
329 struct rk_spi_softc * const sc = cookie;
330 int s;
331
332 s = splbio();
333 spi_transq_enqueue(&sc->sc_q, st);
334 if (sc->sc_running == false) {
335 rk_spi_start(sc);
336 }
337 splx(s);
338
339 return 0;
340 }
341
342 static void
rk_spi_txfifo_fill(struct rk_spi_softc * const sc,size_t maxlen)343 rk_spi_txfifo_fill(struct rk_spi_softc * const sc, size_t maxlen)
344 {
345 struct spi_chunk *chunk = sc->sc_wchunk;
346 size_t len;
347 uint8_t b;
348
349 if (chunk == NULL)
350 return;
351
352 len = MIN(maxlen, chunk->chunk_wresid);
353 chunk->chunk_wresid -= len;
354 while (len--) {
355 if (chunk->chunk_wptr) {
356 b = *chunk->chunk_wptr++;
357 } else {
358 b = 0;
359 }
360 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SPI_TXDR, b);
361 }
362 if (sc->sc_wchunk->chunk_wresid == 0) {
363 sc->sc_wchunk = sc->sc_wchunk->chunk_next;
364 }
365 }
366
367 static void
rk_spi_rxfifo_drain(struct rk_spi_softc * const sc,size_t maxlen)368 rk_spi_rxfifo_drain(struct rk_spi_softc * const sc, size_t maxlen)
369 {
370 struct spi_chunk *chunk = sc->sc_rchunk;
371 size_t len;
372 uint8_t b;
373
374 if (chunk == NULL)
375 return;
376
377 len = MIN(maxlen, chunk->chunk_rresid);
378 chunk->chunk_rresid -= len;
379
380 while (len--) {
381 b = bus_space_read_1(sc->sc_bst, sc->sc_bsh, SPI_RXDR);
382 if (chunk->chunk_rptr) {
383 *chunk->chunk_rptr++ = b;
384 }
385 }
386 if (sc->sc_rchunk->chunk_rresid == 0) {
387 sc->sc_rchunk = sc->sc_rchunk->chunk_next;
388 }
389 }
390
391 static void
rk_spi_rxtx(struct rk_spi_softc * const sc)392 rk_spi_rxtx(struct rk_spi_softc * const sc)
393 {
394 bool again;
395 uint32_t reg;
396 size_t avail;
397
398 /* Service both FIFOs until no more progress can be made. */
399 again = true;
400 while (again) {
401 again = false;
402 reg = SPIREG_READ(sc, SPI_RXFLR);
403 avail = __SHIFTOUT(reg, SPI_RXFLR_RXFLR);
404 if (avail > 0) {
405 KASSERT(sc->sc_rchunk != NULL);
406 rk_spi_rxfifo_drain(sc, avail);
407 again = true;
408 }
409 reg = SPIREG_READ(sc, SPI_TXFLR);
410 avail = SPI_FIFOLEN - __SHIFTOUT(reg, SPI_TXFLR_TXFLR);
411 if (avail > 0 && sc->sc_wchunk != NULL) {
412 rk_spi_txfifo_fill(sc, avail);
413 again = true;
414 }
415 }
416 }
417
418 static void
rk_spi_set_interrupt_mask(struct rk_spi_softc * const sc)419 rk_spi_set_interrupt_mask(struct rk_spi_softc * const sc)
420 {
421 uint32_t imr = SPI_IMR_RFOIM | SPI_IMR_RFUIM | SPI_IMR_TFOIM;
422 int len;
423
424 /*
425 * Delay rx interrupts until the FIFO has the # of bytes we'd
426 * ideally like to receive, or FIFO is half full.
427 */
428 len = sc->sc_rchunk != NULL
429 ? MIN(sc->sc_rchunk->chunk_rresid, SPI_FIFOLEN / 2) : 0;
430 if (len > 0) {
431 SPIREG_WRITE(sc, SPI_RXFTLR, len - 1);
432 imr |= SPI_IMR_RFFIM;
433 }
434
435 /*
436 * Delay tx interrupts until the FIFO can accept the # of bytes we'd
437 * ideally like to transmit, or the FIFO is half empty.
438 */
439 len = sc->sc_wchunk != NULL
440 ? MIN(sc->sc_wchunk->chunk_wresid, SPI_FIFOLEN / 2) : 0;
441 if (len > 0) {
442 SPIREG_WRITE(sc, SPI_TXFTLR, SPI_FIFOLEN - len);
443 imr |= SPI_IMR_TFEIM;
444 }
445
446 /* If xfer is done, then interrupt as soon as the tx fifo is empty. */
447 if (!ISSET(imr, (SPI_IMR_RFFIM | SPI_IMR_TFEIM))) {
448 SPIREG_WRITE(sc, SPI_TXFTLR, 0);
449 imr |= SPI_IMR_TFEIM;
450 }
451
452 SPIREG_WRITE(sc, SPI_IMR, imr);
453 }
454
455 static void
rk_spi_start(struct rk_spi_softc * const sc)456 rk_spi_start(struct rk_spi_softc * const sc)
457 {
458 struct spi_transfer *st;
459
460 while ((st = spi_transq_first(&sc->sc_q)) != NULL) {
461 spi_transq_dequeue(&sc->sc_q);
462 KASSERT(sc->sc_transfer == NULL);
463 sc->sc_transfer = st;
464 sc->sc_rchunk = sc->sc_wchunk = st->st_chunks;
465 sc->sc_running = true;
466
467 KASSERT(st->st_slave < sc->sc_spi.sct_nslaves);
468 SPIREG_WRITE(sc, SPI_SER, 1 << st->st_slave);
469
470 rk_spi_rxtx(sc);
471 rk_spi_set_interrupt_mask(sc);
472
473 if (!cold)
474 return;
475
476 for (;;) {
477 (void) rk_spi_intr(sc);
478 if (ISSET(st->st_flags, SPI_F_DONE))
479 break;
480 }
481 }
482 sc->sc_running = false;
483 }
484
485 static int
rk_spi_intr(void * cookie)486 rk_spi_intr(void *cookie)
487 {
488 struct rk_spi_softc * const sc = cookie;
489 struct spi_transfer *st;
490 uint32_t isr;
491 uint32_t sr;
492 uint32_t icr = SPI_ICR_CCI;
493
494 isr = SPIREG_READ(sc, SPI_ISR);
495 if (!isr)
496 return 0;
497
498 if (ISSET(isr, SPI_ISR_RFOIS)) {
499 device_printf(sc->sc_dev, "RXFIFO overflow\n");
500 icr |= SPI_ICR_CRFOI;
501 }
502 if (ISSET(isr, SPI_ISR_RFUIS)) {
503 device_printf(sc->sc_dev, "RXFIFO underflow\n");
504 icr |= SPI_ICR_CRFUI;
505 }
506 if (ISSET(isr, SPI_ISR_TFOIS)) {
507 device_printf(sc->sc_dev, "TXFIFO overflow\n");
508 icr |= SPI_ICR_CTFOI;
509 }
510
511 rk_spi_rxtx(sc);
512
513 if (sc->sc_rchunk == NULL && sc->sc_wchunk == NULL) {
514 do {
515 sr = SPIREG_READ(sc, SPI_SR);
516 } while (ISSET(sr, SPI_SR_BSF));
517 SPIREG_WRITE(sc, SPI_IMR, 0);
518 SPIREG_WRITE(sc, SPI_SER, 0);
519 st = sc->sc_transfer;
520 sc->sc_transfer = NULL;
521 KASSERT(st != NULL);
522 spi_done(st, 0);
523 sc->sc_running = false;
524 } else {
525 rk_spi_set_interrupt_mask(sc);
526 }
527
528 SPIREG_WRITE(sc, SPI_ICR, icr);
529
530 return 1;
531 }
532