1 /* $NetBSD: rk3399_cru.c,v 1.25 2022/08/23 05:33:39 ryo Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.25 2022/08/23 05:33:39 ryo Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/systm.h>
37
38 #include <dev/fdt/fdtvar.h>
39
40 #include <arm/rockchip/rk_cru.h>
41 #include <arm/rockchip/rk3399_cru.h>
42
43 #define PLL_CON(n) (0x0000 + (n) * 4)
44 #define CLKSEL_CON(n) (0x0100 + (n) * 4)
45 #define CLKGATE_CON(n) (0x0300 + (n) * 4)
46 #define SOFTRST_CON(n) (0x0400 + (n) * 4)
47
48 static int rk3399_cru_match(device_t, cfdata_t, void *);
49 static void rk3399_cru_attach(device_t, device_t, void *);
50
51 static const struct device_compatible_entry compat_data[] = {
52 { .compat = "rockchip,rk3399-cru" },
53 DEVICE_COMPAT_EOL
54 };
55
56 CFATTACH_DECL_NEW(rk3399_cru, sizeof(struct rk_cru_softc),
57 rk3399_cru_match, rk3399_cru_attach, NULL, NULL);
58
59 static const struct rk_cru_pll_rate pll_rates[] = {
60 RK_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
61 RK_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
62 RK_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
63 RK_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
64 RK_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
65 RK_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
66 RK_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
67 RK_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
68 RK_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
69 RK_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
70 RK_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
71 RK_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
72 RK_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
73 RK_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
74 RK_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
75 RK_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
76 RK_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
77 RK_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
78 RK_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
79 RK_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
80 RK_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
81 RK_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
82 RK_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
83 RK_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
84 RK_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
85 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
86 RK_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
87 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
88 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
89 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
90 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
91 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
92 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
93 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
94 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
95 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
96 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
97 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
98 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
99 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
100 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
101 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
102 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
103 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
104 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
105 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
106 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
107 RK_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
108 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
109 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
110 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
111 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
112 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
113 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
114 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
115 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
116 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
117 RK_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
118 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
119 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
120 RK_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
121 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
122 RK_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
123 RK_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
124 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
125 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
126 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
127 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
128 RK_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
129 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
130 RK_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
131 RK_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
132 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
133 RK_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
134 RK_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
135 RK_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
136 RK_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
137 };
138
139 static const struct rk_cru_pll_rate pll_norates[] = {
140 };
141
142 #define RK3399_ACLKM_MASK __BITS(12,8)
143 #define RK3399_ATCLK_MASK __BITS(4,0)
144 #define RK3399_PDBG_MASK __BITS(12,8)
145
146 #define RK3399_CPU_RATE(_rate, _reg0, _reg0_mask, _reg0_val, _reg1, _reg1_mask, _reg1_val)\
147 { \
148 .rate = (_rate), \
149 .divs[0] = { .reg = (_reg0), .mask = (_reg0_mask), .val = (_reg0_val) },\
150 .divs[1] = { .reg = (_reg1), .mask = (_reg1_mask), .val = (_reg1_val) },\
151 }
152
153 #define RK3399_CPUL_RATE(_rate, _aclkm, _atclk, _pdbg) \
154 RK3399_CPU_RATE(_rate, \
155 CLKSEL_CON(0), RK3399_ACLKM_MASK, \
156 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \
157 CLKSEL_CON(1), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \
158 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK))
159
160 #define RK3399_CPUB_RATE(_rate, _aclkm, _atclk, _pdbg) \
161 RK3399_CPU_RATE(_rate, \
162 CLKSEL_CON(2), RK3399_ACLKM_MASK, \
163 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \
164 CLKSEL_CON(3), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \
165 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK))
166
167 static const struct rk_cru_cpu_rate armclkl_rates[] = {
168 RK3399_CPUL_RATE(1800000000, 1, 8, 8),
169 RK3399_CPUL_RATE(1704000000, 1, 8, 8),
170 RK3399_CPUL_RATE(1608000000, 1, 7, 7),
171 RK3399_CPUL_RATE(1512000000, 1, 7, 7),
172 RK3399_CPUL_RATE(1488000000, 1, 6, 6),
173 RK3399_CPUL_RATE(1416000000, 1, 6, 6),
174 RK3399_CPUL_RATE(1200000000, 1, 5, 5),
175 RK3399_CPUL_RATE(1008000000, 1, 5, 5),
176 RK3399_CPUL_RATE( 816000000, 1, 4, 4),
177 RK3399_CPUL_RATE( 696000000, 1, 3, 3),
178 RK3399_CPUL_RATE( 600000000, 1, 3, 3),
179 RK3399_CPUL_RATE( 408000000, 1, 2, 2),
180 RK3399_CPUL_RATE( 312000000, 1, 1, 1),
181 RK3399_CPUL_RATE( 216000000, 1, 1, 1),
182 RK3399_CPUL_RATE( 96000000, 1, 1, 1),
183 };
184
185 static const struct rk_cru_cpu_rate armclkb_rates[] = {
186 RK3399_CPUB_RATE(2208000000, 1, 11, 11),
187 RK3399_CPUB_RATE(2184000000, 1, 11, 11),
188 RK3399_CPUB_RATE(2088000000, 1, 10, 10),
189 RK3399_CPUB_RATE(2040000000, 1, 10, 10),
190 RK3399_CPUB_RATE(2016000000, 1, 9, 9),
191 RK3399_CPUB_RATE(2000000000, 1, 9, 9),
192 RK3399_CPUB_RATE(1992000000, 1, 9, 9),
193 RK3399_CPUB_RATE(1896000000, 1, 9, 9),
194 RK3399_CPUB_RATE(1800000000, 1, 8, 8),
195 RK3399_CPUB_RATE(1704000000, 1, 8, 8),
196 RK3399_CPUB_RATE(1608000000, 1, 7, 7),
197 RK3399_CPUB_RATE(1512000000, 1, 7, 7),
198 RK3399_CPUB_RATE(1488000000, 1, 6, 6),
199 RK3399_CPUB_RATE(1416000000, 1, 6, 6),
200 RK3399_CPUB_RATE(1200000000, 1, 5, 5),
201 RK3399_CPUB_RATE(1008000000, 1, 5, 5),
202 RK3399_CPUB_RATE( 816000000, 1, 4, 4),
203 RK3399_CPUB_RATE( 696000000, 1, 3, 3),
204 RK3399_CPUB_RATE( 600000000, 1, 3, 3),
205 RK3399_CPUB_RATE( 408000000, 1, 2, 2),
206 RK3399_CPUB_RATE( 312000000, 1, 1, 1),
207 RK3399_CPUB_RATE( 216000000, 1, 1, 1),
208 RK3399_CPUB_RATE( 96000000, 1, 1, 1),
209 };
210
211 #define PLL_CON0 0x00
212 #define PLL_FBDIV __BITS(11,0)
213
214 #define PLL_CON1 0x04
215 #define PLL_POSTDIV2 __BITS(14,12)
216 #define PLL_POSTDIV1 __BITS(10,8)
217 #define PLL_REFDIV __BITS(5,0)
218
219 #define PLL_CON2 0x08
220 #define PLL_LOCK __BIT(31)
221 #define PLL_FRACDIV __BITS(23,0)
222
223 #define PLL_CON3 0x0c
224 #define PLL_WORK_MODE __BITS(9,8)
225 #define PLL_WORK_MODE_SLOW 0
226 #define PLL_WORK_MODE_NORMAL 1
227 #define PLL_WORK_MODE_DEEP_SLOW 2
228 #define PLL_DSMPD __BIT(3)
229
230 #define PLL_WRITE_MASK 0xffff0000
231
232 static u_int
rk3399_cru_pll_get_rate(struct rk_cru_softc * sc,struct rk_cru_clk * clk)233 rk3399_cru_pll_get_rate(struct rk_cru_softc *sc,
234 struct rk_cru_clk *clk)
235 {
236 struct rk_cru_pll *pll = &clk->u.pll;
237 struct clk *clkp, *clkp_parent;
238 u_int foutvco, foutpostdiv;
239
240 KASSERT(clk->type == RK_CRU_PLL);
241
242 clkp = &clk->base;
243 clkp_parent = clk_get_parent(clkp);
244 if (clkp_parent == NULL)
245 return 0;
246
247 const u_int fref = clk_get_rate(clkp_parent);
248 if (fref == 0)
249 return 0;
250
251 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
252 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
253 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
254 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
255
256 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);
257 const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2);
258 const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1);
259 const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV);
260 const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV);
261 const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD);
262
263 if (dsmpd == 1) {
264 /* integer mode */
265 foutvco = fref / refdiv * fbdiv;
266 } else {
267 /* fractional mode */
268 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
269 }
270 foutpostdiv = foutvco / postdiv1 / postdiv2;
271
272 return foutpostdiv;
273 }
274
275 static int
rk3399_cru_pll_set_rate(struct rk_cru_softc * sc,struct rk_cru_clk * clk,u_int rate)276 rk3399_cru_pll_set_rate(struct rk_cru_softc *sc,
277 struct rk_cru_clk *clk, u_int rate)
278 {
279 struct rk_cru_pll *pll = &clk->u.pll;
280 const struct rk_cru_pll_rate *pll_rate = NULL;
281 uint32_t val;
282 int retry, best_diff;
283
284 KASSERT(clk->type == RK_CRU_PLL);
285
286 if (pll->rates == NULL || rate == 0)
287 return EIO;
288
289 best_diff = INT_MAX;
290 for (int i = 0; i < pll->nrates; i++) {
291 int diff;
292
293 if (rate > pll->rates[i].rate)
294 diff = rate - pll->rates[i].rate;
295 else
296 diff = pll->rates[i].rate - rate;
297 if (diff < best_diff) {
298 pll_rate = &pll->rates[i];
299 best_diff = diff;
300 }
301 }
302
303 val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);
304 CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
305
306 CRU_WRITE(sc, pll->con_base + PLL_CON0,
307 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16));
308
309 CRU_WRITE(sc, pll->con_base + PLL_CON1,
310 __SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) |
311 __SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) |
312 __SHIFTIN(pll_rate->refdiv, PLL_REFDIV) |
313 ((PLL_POSTDIV2 | PLL_POSTDIV1 | PLL_REFDIV) << 16));
314
315 val = CRU_READ(sc, pll->con_base + PLL_CON2);
316 val &= ~PLL_FRACDIV;
317 val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV);
318 CRU_WRITE(sc, pll->con_base + PLL_CON2, val);
319
320 val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16);
321 CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
322
323 for (retry = 1000; retry > 0; retry--) {
324 if (CRU_READ(sc, pll->con_base + PLL_CON2) & pll->lock_mask)
325 break;
326 delay(1);
327 }
328
329 if (retry == 0)
330 device_printf(sc->sc_dev, "WARNING: %s failed to lock\n",
331 clk->base.name);
332
333 /* Set PLL work mode to normal */
334 val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16);
335 CRU_WRITE(sc, pll->con_base + PLL_CON3, val);
336
337 return 0;
338 }
339
340 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \
341 { \
342 .id = (_id), \
343 .type = RK_CRU_PLL, \
344 .base.name = (_name), \
345 .base.flags = 0, \
346 .u.pll.parents = (_parents), \
347 .u.pll.nparents = __arraycount(_parents), \
348 .u.pll.con_base = (_con_base), \
349 .u.pll.mode_reg = (_mode_reg), \
350 .u.pll.mode_mask = (_mode_mask), \
351 .u.pll.lock_mask = (_lock_mask), \
352 .u.pll.rates = (_rates), \
353 .u.pll.nrates = __arraycount(_rates), \
354 .get_rate = rk3399_cru_pll_get_rate, \
355 .set_rate = rk3399_cru_pll_set_rate, \
356 .get_parent = rk_cru_pll_get_parent, \
357 }
358
359 static const char * pll_parents[] = { "xin24m", "xin32k" };
360 static const char * armclkl_parents[] = { "clk_core_l_lpll_src", "clk_core_l_bpll_src", "clk_core_l_dpll_src", "clk_core_l_gpll_src" };
361 static const char * armclkb_parents[] = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" };
362 static const char * mux_clk_tsadc_parents[] = { "xin24m", "xin32k" };
363 static const char * mux_pll_src_cpll_gpll_parents[] = { "cpll", "gpll" };
364 static const char * mux_pll_src_cpll_gpll_npll_parents[] = { "cpll", "gpll", "npll" };
365 static const char * mux_pll_src_cpll_gpll_ppll_parents[] = { "cpll", "gpll", "ppll" };
366 static const char * mux_pll_src_cpll_gpll_upll_parents[] = { "cpll", "gpll", "upll" };
367 static const char * mux_pll_src_cpll_gpll_npll_24m_parents[] = { "cpll", "gpll", "npll", "xin24m" };
368 static const char * mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents[] = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
369 static const char * mux_pll_src_npll_cpll_gpll_parents[] = { "npll", "cpll", "gpll" };
370 static const char * mux_pll_src_vpll_cpll_gpll_parents[] = { "vpll", "cpll", "gpll" };
371 static const char * mux_pll_src_vpll_cpll_gpll_npll_parents[] = { "vpll", "cpll", "gpll", "npll" };
372 static const char * mux_aclk_perilp0_parents[] = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" };
373 static const char * mux_hclk_perilp1_parents[] = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" };
374 static const char * mux_aclk_perihp_parents[] = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
375 static const char * mux_aclk_cci_parents[] = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" };
376 static const char * mux_dclk_vop0_parents[] = { "dclk_vop0_div", "dclk_vop0_frac" };
377 static const char * mux_dclk_vop1_parents[] = { "dclk_vop1_div", "dclk_vop1_frac" };
378 static const char * mux_i2s0_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "clkin_i2s", "xin12m" };
379 static const char * mux_i2s1_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s", "xin12m" };
380 static const char * mux_i2s2_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s", "xin12m" };
381 static const char * mux_i2sch_parents[] = { "clk_i2s0", "clk_i2s1", "clk_i2s2" };
382 static const char * mux_i2sout_parents[] = { "clk_i2sout_src", "xin12m" };
383 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
384 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
385 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
386 static const char * mux_uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
387 static const char * mux_rmii_parents[] = { "clk_gmac", "clkin_gmac" };
388 static const char * mux_aclk_gmac_parents[] = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" };
389 static const char * mux_aclk_emmc_parents[] = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" };
390 static const char * mux_pll_src_24m_pciephy_parents[] = { "xin24m", "clk_pciephy_ref100m" };
391 static const char * mux_pciecore_cru_phy_parents[] = { "clk_pcie_core_cru", "clk_pcie_core_phy" };
392
393 static struct rk_cru_clk rk3399_cru_clks[] = {
394 RK3399_PLL(RK3399_PLL_APLLL, "lpll", pll_parents,
395 PLL_CON(0), /* con_base */
396 PLL_CON(3), /* mode_reg */
397 __BIT(8), /* mode_mask */
398 __BIT(31), /* lock_mask */
399 pll_rates),
400 RK3399_PLL(RK3399_PLL_APLLB, "bpll", pll_parents,
401 PLL_CON(8), /* con_base */
402 PLL_CON(11), /* mode_reg */
403 __BIT(8), /* mode_mask */
404 __BIT(31), /* lock_mask */
405 pll_rates),
406 RK3399_PLL(RK3399_PLL_DPLL, "dpll", pll_parents,
407 PLL_CON(16), /* con_base */
408 PLL_CON(19), /* mode_reg */
409 __BIT(8), /* mode_mask */
410 __BIT(31), /* lock_mask */
411 pll_norates),
412 RK3399_PLL(RK3399_PLL_CPLL, "cpll", pll_parents,
413 PLL_CON(24), /* con_base */
414 PLL_CON(27), /* mode_reg */
415 __BIT(8), /* mode_mask */
416 __BIT(31), /* lock_mask */
417 pll_rates),
418 RK3399_PLL(RK3399_PLL_GPLL, "gpll", pll_parents,
419 PLL_CON(32), /* con_base */
420 PLL_CON(35), /* mode_reg */
421 __BIT(8), /* mode_mask */
422 __BIT(31), /* lock_mask */
423 pll_rates),
424 RK3399_PLL(RK3399_PLL_NPLL, "npll", pll_parents,
425 PLL_CON(40), /* con_base */
426 PLL_CON(43), /* mode_reg */
427 __BIT(8), /* mode_mask */
428 __BIT(31), /* lock_mask */
429 pll_rates),
430 RK3399_PLL(RK3399_PLL_VPLL, "vpll", pll_parents,
431 PLL_CON(48), /* con_base */
432 PLL_CON(51), /* mode_reg */
433 __BIT(8), /* mode_mask */
434 __BIT(31), /* lock_mask */
435 pll_rates),
436
437 RK_GATE(0, "clk_core_l_lpll_src", "lpll", CLKGATE_CON(0), 0),
438 RK_GATE(0, "clk_core_l_bpll_src", "bpll", CLKGATE_CON(0), 1),
439 RK_GATE(0, "clk_core_l_dpll_src", "dpll", CLKGATE_CON(0), 2),
440 RK_GATE(0, "clk_core_l_gpll_src", "gpll", CLKGATE_CON(0), 3),
441
442 RK_CPU(RK3399_ARMCLKL, "armclkl", armclkl_parents,
443 CLKSEL_CON(0), /* mux_reg */
444 __BITS(7,6), 0, 3, /* mux_mask, mux_main, mux_alt */
445 CLKSEL_CON(0), /* div_reg */
446 __BITS(4,0), /* div_mask */
447 armclkl_rates),
448
449 RK_GATE(0, "clk_core_b_lpll_src", "lpll", CLKGATE_CON(1), 0),
450 RK_GATE(0, "clk_core_b_bpll_src", "bpll", CLKGATE_CON(1), 1),
451 RK_GATE(0, "clk_core_b_dpll_src", "dpll", CLKGATE_CON(1), 2),
452 RK_GATE(0, "clk_core_b_gpll_src", "gpll", CLKGATE_CON(1), 3),
453
454 RK_CPU(RK3399_ARMCLKB, "armclkb", armclkb_parents,
455 CLKSEL_CON(2), /* mux_reg */
456 __BITS(7,6), 1, 3, /* mux_mask, mux_main, mux_alt */
457 CLKSEL_CON(2), /* div_reg */
458 __BITS(4,0), /* div_mask */
459 armclkb_rates),
460
461 /*
462 * perilp0
463 */
464 RK_GATE(0, "gpll_aclk_perilp0_src", "gpll", CLKGATE_CON(7), 0),
465 RK_GATE(0, "cpll_aclk_perilp0_src", "cpll", CLKGATE_CON(7), 1),
466 RK_COMPOSITE(RK3399_ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_parents,
467 CLKSEL_CON(23), /* muxdiv_reg */
468 __BIT(7), /* mux_mask */
469 __BITS(4,0), /* div_mask */
470 CLKGATE_CON(7), /* gate_reg */
471 __BIT(2), /* gate_mask */
472 0),
473 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0",
474 CLKSEL_CON(23), /* div_reg */
475 __BITS(10,8), /* div_mask */
476 CLKGATE_CON(7), /* gate_reg */
477 __BIT(3), /* gate_mask */
478 0),
479 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0",
480 CLKSEL_CON(23), /* div_reg */
481 __BITS(14,12), /* div_mask */
482 CLKGATE_CON(7), /* gate_reg */
483 __BIT(4), /* gate_mask */
484 0),
485
486 /*
487 * perilp1
488 */
489 RK_GATE(0, "gpll_hclk_perilp1_src", "gpll", CLKGATE_CON(8), 0),
490 RK_GATE(0, "cpll_hclk_perilp1_src", "cpll", CLKGATE_CON(8), 1),
491 RK_COMPOSITE_NOGATE(RK3399_HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_parents,
492 CLKSEL_CON(25), /* muxdiv_reg */
493 __BITS(10,8), /* mux_mask */
494 __BITS(4,0), /* div_mask */
495 0),
496 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1",
497 CLKSEL_CON(25), /* div_reg */
498 __BITS(10,8), /* div_mask */
499 CLKGATE_CON(8), /* gate_reg */
500 __BIT(2), /* gate_mask */
501 0),
502
503 /*
504 * perihp
505 */
506 RK_GATE(0, "gpll_aclk_perihp_src", "gpll", CLKGATE_CON(5), 0),
507 RK_GATE(0, "cpll_aclk_perihp_src", "cpll", CLKGATE_CON(5), 1),
508 RK_COMPOSITE(RK3399_ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_parents,
509 CLKSEL_CON(14), /* muxdiv_reg */
510 __BIT(7), /* mux_mask */
511 __BITS(4,0), /* div_mask */
512 CLKGATE_CON(5), /* gate_reg */
513 __BIT(2), /* gate_mask */
514 0),
515 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERIHP, "hclk_perihp", "aclk_perihp",
516 CLKSEL_CON(14), /* div_reg */
517 __BITS(10,8), /* div_mask */
518 CLKGATE_CON(5), /* gate_reg */
519 __BIT(3), /* gate_mask */
520 0),
521 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERIHP, "pclk_perihp", "aclk_perihp",
522 CLKSEL_CON(14), /* div_reg */
523 __BITS(14,12), /* div_mask */
524 CLKGATE_CON(5), /* gate_reg */
525 __BIT(4), /* gate_mask */
526 0),
527
528 /*
529 * CCI
530 */
531 RK_GATE(0, "cpll_aclk_cci_src", "cpll", CLKGATE_CON(2), 0),
532 RK_GATE(0, "gpll_aclk_cci_src", "gpll", CLKGATE_CON(2), 1),
533 RK_GATE(0, "npll_aclk_cci_src", "npll", CLKGATE_CON(2), 2),
534 RK_GATE(0, "vpll_aclk_cci_src", "vpll", CLKGATE_CON(2), 3),
535 RK_COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_parents,
536 CLKSEL_CON(5), /* muxdiv_reg */
537 __BITS(7,6), /* mux_mask */
538 __BITS(4,0), /* div_mask */
539 CLKGATE_CON(2), /* gate_reg */
540 __BIT(4), /* gate_mask */
541 0),
542 RK_GATE(RK3399_ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLKGATE_CON(15), 2),
543
544 /*
545 * GIC
546 */
547 RK_COMPOSITE(RK3399_ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_parents,
548 CLKSEL_CON(56), /* muxdiv_reg */
549 __BIT(15), /* mux_mask */
550 __BITS(12,8), /* div_mask */
551 CLKGATE_CON(12), /* gate_reg */
552 __BIT(12), /* gate_mask */
553 0),
554
555 /*
556 * DDR
557 */
558 RK_COMPOSITE(RK3399_PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_parents,
559 CLKSEL_CON(6), /* muxdiv_reg */
560 __BIT(15), /* mux_mask */
561 __BITS(12,8), /* div_mask */
562 CLKGATE_CON(3), /* gate_reg */
563 __BIT(4), /* gate_mask */
564 0),
565
566 /*
567 * alive
568 */
569 RK_DIV(RK3399_PCLK_ALIVE, "pclk_alive", "gpll", CLKSEL_CON(57), __BITS(4,0), 0),
570
571 /*
572 * GPIO
573 */
574 RK_GATE(RK3399_PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLKGATE_CON(31), 3),
575 RK_GATE(RK3399_PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLKGATE_CON(31), 4),
576 RK_GATE(RK3399_PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLKGATE_CON(31), 5),
577
578 /*
579 * UART
580 */
581 RK_MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_parents, CLKSEL_CON(33), __BITS(13,12)),
582 RK_MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_parents, CLKSEL_CON(33), __BIT(15)),
583 RK_COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src",
584 CLKSEL_CON(33), /* div_reg */
585 __BITS(6,0), /* div_mask */
586 CLKGATE_CON(9), /* gate_reg */
587 __BIT(0), /* gate_mask */
588 0),
589 RK_COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src",
590 CLKSEL_CON(34), /* div_reg */
591 __BITS(6,0), /* div_mask */
592 CLKGATE_CON(9), /* gate_reg */
593 __BIT(2), /* gate_mask */
594 0),
595 RK_COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src",
596 CLKSEL_CON(35), /* div_reg */
597 __BITS(6,0), /* div_mask */
598 CLKGATE_CON(9), /* gate_reg */
599 __BIT(4), /* gate_mask */
600 0),
601 RK_COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src",
602 CLKSEL_CON(36), /* div_reg */
603 __BITS(6,0), /* div_mask */
604 CLKGATE_CON(9), /* gate_reg */
605 __BIT(6), /* gate_mask */
606 0),
607 RK_MUX(RK3399_SCLK_UART0, "clk_uart0", mux_uart0_parents, CLKSEL_CON(33), __BITS(9,8)),
608 RK_MUX(RK3399_SCLK_UART1, "clk_uart1", mux_uart1_parents, CLKSEL_CON(34), __BITS(9,8)),
609 RK_MUX(RK3399_SCLK_UART2, "clk_uart2", mux_uart2_parents, CLKSEL_CON(35), __BITS(9,8)),
610 RK_MUX(RK3399_SCLK_UART3, "clk_uart3", mux_uart3_parents, CLKSEL_CON(36), __BITS(9,8)),
611 RK_GATE(RK3399_PCLK_UART0, "pclk_uart0", "pclk_perilp1", CLKGATE_CON(22), 0),
612 RK_GATE(RK3399_PCLK_UART1, "pclk_uart1", "pclk_perilp1", CLKGATE_CON(22), 1),
613 RK_GATE(RK3399_PCLK_UART2, "pclk_uart2", "pclk_perilp1", CLKGATE_CON(22), 2),
614 RK_GATE(RK3399_PCLK_UART3, "pclk_uart3", "pclk_perilp1", CLKGATE_CON(22), 3),
615
616 /*
617 * SDMMC/SDIO
618 */
619 RK_COMPOSITE(RK3399_HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_parents,
620 CLKSEL_CON(13), /* muxdiv_reg */
621 __BIT(15), /* mux_mask */
622 __BITS(12,8), /* div_mask */
623 CLKGATE_CON(12), /* gate_reg */
624 __BIT(13), /* gate_mask */
625 RK_COMPOSITE_ROUND_DOWN),
626 RK_COMPOSITE(RK3399_SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents,
627 CLKSEL_CON(15), /* muxdiv_reg */
628 __BITS(10,8), /* mux_mask */
629 __BITS(6,0), /* div_mask */
630 CLKGATE_CON(6), /* gate_reg */
631 __BIT(0), /* gate_mask */
632 RK_COMPOSITE_ROUND_DOWN),
633 RK_COMPOSITE(RK3399_SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents,
634 CLKSEL_CON(16), /* muxdiv_reg */
635 __BITS(10,8), /* mux_mask */
636 __BITS(6,0), /* div_mask */
637 CLKGATE_CON(6), /* gate_reg */
638 __BIT(1), /* gate_mask */
639 RK_COMPOSITE_ROUND_DOWN),
640 RK_GATE(RK3399_HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLKGATE_CON(33), 8),
641 RK_GATE(RK3399_HCLK_SDIO, "hclk_sdio", "pclk_perilp1", CLKGATE_CON(34), 4),
642
643 /*
644 * eMMC
645 */
646 RK_COMPOSITE(RK3399_SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents,
647 CLKSEL_CON(22), /* muxdiv_reg */
648 __BITS(10,8), /* mux_mask */
649 __BITS(6,0), /* div_mask */
650 CLKGATE_CON(6), /* gate_reg */
651 __BIT(14), /* gate_mask */
652 RK_COMPOSITE_ROUND_DOWN),
653 RK_GATE(0, "cpll_aclk_emmc_src", "cpll", CLKGATE_CON(6), 13),
654 RK_GATE(0, "gpll_aclk_emmc_src", "gpll", CLKGATE_CON(6), 12),
655 RK_COMPOSITE_NOGATE(RK3399_ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_parents,
656 CLKSEL_CON(21), /* muxdiv_reg */
657 __BIT(7), /* mux_mask */
658 __BITS(4,0), /* div_mask */
659 0),
660 RK_GATE(RK3399_ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLKGATE_CON(32), 8),
661 RK_GATE(RK3399_ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLKGATE_CON(32), 9),
662 RK_GATE(RK3399_ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLKGATE_CON(32), 10),
663
664 /*
665 * GMAC
666 */
667 RK_COMPOSITE(RK3399_SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_parents,
668 CLKSEL_CON(20), /* muxdiv_reg */
669 __BITS(15,14), /* mux_mask */
670 __BITS(12,8), /* div_mask */
671 CLKGATE_CON(5), /* gate_reg */
672 __BIT(5), /* gate_mask */
673 0),
674 RK_MUX(RK3399_SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_parents, CLKSEL_CON(19), __BIT(4)),
675 RK_GATE(RK3399_SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLKGATE_CON(5), 6),
676 RK_GATE(RK3399_SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLKGATE_CON(5), 7),
677 RK_GATE(RK3399_SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLKGATE_CON(5), 8),
678 RK_GATE(RK3399_SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLKGATE_CON(5), 9),
679 RK_GATE(0, "gpll_aclk_gmac_src", "gpll", CLKGATE_CON(6), 8),
680 RK_GATE(0, "cpll_aclk_gmac_src", "cpll", CLKGATE_CON(6), 9),
681 RK_COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_parents,
682 CLKSEL_CON(20), /* muxdiv_reg */
683 __BIT(17), /* mux_mask */
684 __BITS(4,0), /* div_mask */
685 CLKGATE_CON(6), /* gate_reg */
686 __BIT(10), /* gate_mask */
687 0),
688 RK_GATE(RK3399_ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLKGATE_CON(32), 0),
689 RK_COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre",
690 CLKSEL_CON(19), /* div_reg */
691 __BITS(10,8), /* div_mask */
692 CLKGATE_CON(6), /* gate_reg */
693 __BIT(11), /* gate_mask */
694 0),
695 RK_GATE(RK3399_PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLKGATE_CON(32), 2),
696
697 /*
698 * USB2
699 */
700 RK_GATE(RK3399_HCLK_HOST0, "hclk_host0", "hclk_perihp", CLKGATE_CON(20), 5),
701 RK_GATE(RK3399_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLKGATE_CON(20), 6),
702 RK_GATE(RK3399_HCLK_HOST1, "hclk_host1", "hclk_perihp", CLKGATE_CON(20), 7),
703 RK_GATE(RK3399_HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLKGATE_CON(20), 8),
704 RK_GATE(RK3399_SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLKGATE_CON(6), 5),
705 RK_GATE(RK3399_SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLKGATE_CON(6), 6),
706
707 /*
708 * USB3
709 */
710 RK_GATE(RK3399_SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLKGATE_CON(12), 1),
711 RK_GATE(RK3399_SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLKGATE_CON(12), 2),
712 RK_COMPOSITE(RK3399_SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", pll_parents,
713 CLKSEL_CON(40), /* muxdiv_reg */
714 __BIT(15), /* mux_mask */
715 __BITS(9,0), /* div_mask */
716 CLKGATE_CON(12), /* gate_reg */
717 __BIT(3), /* gate_mask */
718 0),
719 RK_COMPOSITE(RK3399_SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", pll_parents,
720 CLKSEL_CON(41), /* muxdiv_reg */
721 __BIT(15), /* mux_mask */
722 __BITS(9,0), /* div_mask */
723 CLKGATE_CON(12), /* gate_reg */
724 __BIT(4), /* gate_mask */
725 0),
726 RK_COMPOSITE(RK3399_ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_parents,
727 CLKSEL_CON(39), /* muxdiv_reg */
728 __BITS(7,6), /* mux_mask */
729 __BITS(4,0), /* div_mask */
730 CLKGATE_CON(12), /* gate_reg */
731 __BIT(0), /* gate_mask */
732 0),
733 RK_GATE(RK3399_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLKGATE_CON(30), 1),
734 RK_GATE(RK3399_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLKGATE_CON(30), 2),
735 RK_GATE(RK3399_ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLKGATE_CON(30), 3),
736 RK_GATE(RK3399_ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLKGATE_CON(30), 4),
737
738 /*
739 * I2C
740 */
741 RK_COMPOSITE(RK3399_SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_parents,
742 CLKSEL_CON(61), /* muxdiv_reg */
743 __BIT(7), /* mux_mask */
744 __BITS(6,0), /* div_mask */
745 CLKGATE_CON(10), /* gate_reg */
746 __BIT(0), /* gate_mask */
747 0),
748 RK_COMPOSITE(RK3399_SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_parents,
749 CLKSEL_CON(62), /* muxdiv_reg */
750 __BIT(7), /* mux_mask */
751 __BITS(6,0), /* div_mask */
752 CLKGATE_CON(10), /* gate_reg */
753 __BIT(2), /* gate_mask */
754 0),
755 RK_COMPOSITE(RK3399_SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_parents,
756 CLKSEL_CON(63), /* muxdiv_reg */
757 __BIT(7), /* mux_mask */
758 __BITS(6,0), /* div_mask */
759 CLKGATE_CON(10), /* gate_reg */
760 __BIT(4), /* gate_mask */
761 0),
762 RK_COMPOSITE(RK3399_SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_parents,
763 CLKSEL_CON(61), /* muxdiv_reg */
764 __BIT(15), /* mux_mask */
765 __BITS(14,8), /* div_mask */
766 CLKGATE_CON(10), /* gate_reg */
767 __BIT(1), /* gate_mask */
768 0),
769 RK_COMPOSITE(RK3399_SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_parents,
770 CLKSEL_CON(62), /* muxdiv_reg */
771 __BIT(15), /* mux_mask */
772 __BITS(14,8), /* div_mask */
773 CLKGATE_CON(10), /* gate_reg */
774 __BIT(3), /* gate_mask */
775 0),
776 RK_COMPOSITE(RK3399_SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_parents,
777 CLKSEL_CON(63), /* muxdiv_reg */
778 __BIT(15), /* mux_mask */
779 __BITS(14,8), /* div_mask */
780 CLKGATE_CON(10), /* gate_reg */
781 __BIT(5), /* gate_mask */
782 0),
783 RK_GATE(RK3399_PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", CLKGATE_CON(22), 5),
784 RK_GATE(RK3399_PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", CLKGATE_CON(22), 6),
785 RK_GATE(RK3399_PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", CLKGATE_CON(22), 7),
786 RK_GATE(RK3399_PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", CLKGATE_CON(22), 8),
787 RK_GATE(RK3399_PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", CLKGATE_CON(22), 9),
788 RK_GATE(RK3399_PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", CLKGATE_CON(22), 10),
789
790 /*
791 * SPI
792 */
793 RK_COMPOSITE(RK3399_SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_parents,
794 CLKSEL_CON(59), /* muxdiv_reg */
795 __BIT(7), /* mux_mask */
796 __BITS(6,0), /* div_mask */
797 CLKGATE_CON(9), /* gate_reg */
798 __BIT(12), /* gate_mask */
799 0),
800 RK_COMPOSITE(RK3399_SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_parents,
801 CLKSEL_CON(59), /* muxdiv_reg */
802 __BIT(15), /* mux_mask */
803 __BITS(14,8), /* div_mask */
804 CLKGATE_CON(9), /* gate_reg */
805 __BIT(13), /* gate_mask */
806 0),
807 RK_COMPOSITE(RK3399_SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_parents,
808 CLKSEL_CON(60), /* muxdiv_reg */
809 __BIT(7), /* mux_mask */
810 __BITS(6,0), /* div_mask */
811 CLKGATE_CON(9), /* gate_reg */
812 __BIT(14), /* gate_mask */
813 0),
814 RK_COMPOSITE(RK3399_SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_parents,
815 CLKSEL_CON(60), /* muxdiv_reg */
816 __BIT(15), /* mux_mask */
817 __BITS(14,8), /* div_mask */
818 CLKGATE_CON(9), /* gate_reg */
819 __BIT(15), /* gate_mask */
820 0),
821 RK_COMPOSITE(RK3399_SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_parents,
822 CLKSEL_CON(58), /* muxdiv_reg */
823 __BIT(15), /* mux_mask */
824 __BITS(14,8), /* div_mask */
825 CLKGATE_CON(13), /* gate_reg */
826 __BIT(13), /* gate_mask */
827 0),
828 RK_GATE(RK3399_PCLK_SPI0, "pclk_rkspi0", "pclk_perilp1", CLKGATE_CON(23), 10),
829 RK_GATE(RK3399_PCLK_SPI1, "pclk_rkspi1", "pclk_perilp1", CLKGATE_CON(23), 11),
830 RK_GATE(RK3399_PCLK_SPI2, "pclk_rkspi2", "pclk_perilp1", CLKGATE_CON(23), 12),
831 RK_GATE(RK3399_PCLK_SPI4, "pclk_rkspi4", "pclk_perilp1", CLKGATE_CON(23), 13),
832 RK_GATE(RK3399_PCLK_SPI5, "pclk_rkspi5", "hclk_perilp1", CLKGATE_CON(34), 5),
833
834 /* Watchdog */
835 RK_SECURE_GATE(RK3399_PCLK_WDT, "pclk_wdt", "pclk_alive" /*, SECURE_CLKGATE_CON(3), 8 */),
836
837 /* PCIe */
838 RK_GATE(RK3399_ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLKGATE_CON(20), 2),
839 RK_GATE(RK3399_ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLKGATE_CON(20), 10),
840 RK_GATE(RK3399_PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLKGATE_CON(20), 11),
841 RK_COMPOSITE(RK3399_SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_parents,
842 CLKSEL_CON(17), /* muxdiv_reg */
843 __BITS(10,8), /* mux_mask */
844 __BITS(6,0), /* div_mask */
845 CLKGATE_CON(6), /* gate_reg */
846 __BIT(2), /* gate_mask */
847 0),
848 RK_COMPOSITE_NOMUX(RK3399_SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll",
849 CLKSEL_CON(18), /* div_reg */
850 __BITS(15,11), /* div_mask */
851 CLKGATE_CON(12), /* gate_reg */
852 __BIT(6), /* gate_mask */
853 0),
854 RK_MUX(RK3399_SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_parents, CLKSEL_CON(18), __BIT(10)),
855 RK_COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_parents,
856 CLKSEL_CON(18), /* muxdiv_reg */
857 __BITS(9,8), /* mux_mask */
858 __BITS(6,0), /* div_mask */
859 CLKGATE_CON(6), /* gate_reg */
860 __BIT(3), /* gate_mask */
861 0),
862 RK_MUX(RK3399_SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_parents, CLKSEL_CON(18), __BIT(7)),
863
864 /* Crypto */
865 RK_COMPOSITE(RK3399_SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_parents,
866 CLKSEL_CON(24), /* muxdiv_reg */
867 __BITS(7,6), /* mux_mask */
868 __BITS(4,0), /* div_mask */
869 CLKGATE_CON(7), /* gate_reg */
870 __BIT(7), /* gate_mask */
871 RK_COMPOSITE_ROUND_DOWN /*???*/),
872 RK_COMPOSITE(RK3399_SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_parents,
873 CLKSEL_CON(26), /* muxdiv_reg */
874 __BITS(7,6), /* mux_mask */
875 __BITS(4,0), /* div_mask */
876 CLKGATE_CON(8), /* gate_reg */
877 __BIT(7), /* gate_mask */
878 RK_COMPOSITE_ROUND_DOWN /*???*/),
879 RK_GATE(RK3399_HCLK_M_CRYPTO0, "hclk_m_crypto0", "pclk_perilp0", CLKGATE_CON(24), 5),
880 RK_GATE(RK3399_HCLK_S_CRYPTO0, "hclk_s_crypto0", "pclk_perilp0", CLKGATE_CON(24), 6),
881 RK_GATE(RK3399_HCLK_M_CRYPTO1, "hclk_m_crypto1", "pclk_perilp0", CLKGATE_CON(24), 14),
882 RK_GATE(RK3399_HCLK_S_CRYPTO1, "hclk_s_crypto1", "pclk_perilp0", CLKGATE_CON(24), 15),
883 RK_GATE(RK3399_ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "pclk_perilp", CLKGATE_CON(25), 6),
884
885 /* TSADC */
886 RK_COMPOSITE(RK3399_SCLK_TSADC, "clk_tsadc", mux_clk_tsadc_parents,
887 CLKSEL_CON(27), /* muxdiv_reg */
888 __BIT(15), /* mux_mask */
889 __BITS(9,0), /* div_mask */
890 CLKGATE_CON(9), /* gate_reg */
891 __BIT(1), /* gate_mask */
892 RK_COMPOSITE_ROUND_DOWN),
893 RK_GATE(RK3399_PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", CLKGATE_CON(22), 13),
894
895 /* VOP0 */
896 RK_COMPOSITE(RK3399_ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_parents,
897 CLKSEL_CON(47), /* muxdiv_reg */
898 __BITS(7,6), /* mux_mask */
899 __BITS(4,0), /* div_mask */
900 CLKGATE_CON(10), /* gate_reg */
901 __BIT(8), /* gate_mask */
902 0),
903 RK_COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre",
904 CLKSEL_CON(47), /* div_reg */
905 __BITS(12,8), /* div_mask */
906 CLKGATE_CON(10), /* gate_reg */
907 __BIT(9), /* gate_mask */
908 0),
909 RK_COMPOSITE(RK3399_DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_parents,
910 CLKSEL_CON(49), /* muxdiv_reg */
911 __BITS(9,8), /* mux_mask */
912 __BITS(7,0), /* div_mask */
913 CLKGATE_CON(10), /* gate_reg */
914 __BIT(12), /* gate_mask */
915 RK_COMPOSITE_SET_RATE_PARENT),
916 RK_GATE(RK3399_ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLKGATE_CON(28), 3),
917 RK_GATE(RK3399_HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLKGATE_CON(28), 2),
918 RK_COMPOSITE_FRAC(RK3399_DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div",
919 CLKSEL_CON(106), /* frac_reg */
920 0),
921 RK_MUX(RK3399_DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_parents, CLKSEL_CON(49), __BIT(11)),
922
923 /* VOP1 */
924 RK_COMPOSITE(RK3399_ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_parents,
925 CLKSEL_CON(48), /* muxdiv_reg */
926 __BITS(7,6), /* mux_mask */
927 __BITS(4,0), /* div_mask */
928 CLKGATE_CON(10), /* gate_reg */
929 __BIT(10), /* gate_mask */
930 0),
931 RK_COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre",
932 CLKSEL_CON(48), /* div_reg */
933 __BITS(12,8), /* div_mask */
934 CLKGATE_CON(10), /* gate_reg */
935 __BIT(11), /* gate_mask */
936 0),
937 RK_COMPOSITE(RK3399_DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_parents,
938 CLKSEL_CON(50), /* muxdiv_reg */
939 __BITS(9,8), /* mux_mask */
940 __BITS(7,0), /* div_mask */
941 CLKGATE_CON(10), /* gate_reg */
942 __BIT(13), /* gate_mask */
943 RK_COMPOSITE_SET_RATE_PARENT),
944 RK_GATE(RK3399_ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLKGATE_CON(28), 7),
945 RK_GATE(RK3399_HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLKGATE_CON(28), 6),
946 RK_COMPOSITE_FRAC(RK3399_DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div",
947 CLKSEL_CON(107), /* frac_reg */
948 0),
949 RK_MUX(RK3399_DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_parents, CLKSEL_CON(50), __BIT(11)),
950
951 /* VIO */
952 RK_COMPOSITE(RK3399_ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_parents,
953 CLKSEL_CON(42), /* muxdiv_reg */
954 __BITS(7,6), /* mux_mask */
955 __BITS(4,0), /* div_mask */
956 CLKGATE_CON(11), /* gate_reg */
957 __BIT(0), /* gate_mask */
958 0),
959 RK_COMPOSITE_NOMUX(RK3399_PCLK_VIO, "pclk_vio", "aclk_vio",
960 CLKSEL_CON(43), /* div_reg */
961 __BITS(4,0), /* div_mask */
962 CLKGATE_CON(11), /* gate_reg */
963 __BIT(1), /* gate_mask */
964 0),
965 RK_GATE(RK3399_PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLKGATE_CON(29), 12),
966
967 /* HDMI */
968 RK_COMPOSITE(RK3399_ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_parents,
969 CLKSEL_CON(42), /* muxdiv_reg */
970 __BITS(15,14), /* mux_mask */
971 __BITS(12,8), /* div_mask */
972 CLKGATE_CON(11), /* gate_reg */
973 __BIT(12), /* gate_mask */
974 0),
975 RK_COMPOSITE_NOMUX(RK3399_PCLK_HDCP, "pclk_hdcp", "aclk_hdcp",
976 CLKSEL_CON(43), /* div_reg */
977 __BITS(14,10), /* div_mask */
978 CLKGATE_CON(11), /* gate_reg */
979 __BIT(10), /* gate_mask */
980 0),
981 RK_COMPOSITE(RK3399_SCLK_HDMI_CEC, "clk_hdmi_cec", pll_parents,
982 CLKSEL_CON(45), /* muxdiv_reg */
983 __BIT(15), /* mux_mask */
984 __BITS(9,0), /* div_mask */
985 CLKGATE_CON(11), /* gate_reg */
986 __BIT(7), /* gate_mask */
987 0),
988 RK_GATE(RK3399_PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLKGATE_CON(29), 6),
989 RK_GATE(RK3399_SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLKGATE_CON(11), 6),
990
991 /* I2S2 */
992 RK_COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_parents,
993 CLKSEL_CON(28), /* muxdiv_reg */
994 __BIT(7), /* mux_mask */
995 __BITS(6,0), /* div_mask */
996 CLKGATE_CON(8), /* gate_reg */
997 __BIT(3), /* gate_mask */
998 0),
999 RK_COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_parents,
1000 CLKSEL_CON(29), /* muxdiv_reg */
1001 __BIT(7), /* mux_mask */
1002 __BITS(6,0), /* div_mask */
1003 CLKGATE_CON(8), /* gate_reg */
1004 __BIT(6), /* gate_mask */
1005 0),
1006 RK_COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_parents,
1007 CLKSEL_CON(30), /* muxdiv_reg */
1008 __BIT(7), /* mux_mask */
1009 __BITS(6,0), /* div_mask */
1010 CLKGATE_CON(8), /* gate_reg */
1011 __BIT(9), /* gate_mask */
1012 0),
1013 RK_COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div",
1014 CLKSEL_CON(96), /* frac_reg */
1015 0),
1016 RK_COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div",
1017 CLKSEL_CON(97), /* frac_reg */
1018 0),
1019 RK_COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div",
1020 CLKSEL_CON(98), /* frac_reg */
1021 0),
1022 RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(28), __BITS(9,8)),
1023 RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(29), __BITS(9,8)),
1024 RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(30), __BITS(9,8)),
1025 RK_GATE(RK3399_SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(8), 5),
1026 RK_GATE(RK3399_SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(8), 8),
1027 RK_GATE(RK3399_SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(8), 11),
1028 RK_GATE(RK3399_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLKGATE_CON(34), 0),
1029 RK_GATE(RK3399_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLKGATE_CON(34), 1),
1030 RK_GATE(RK3399_HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLKGATE_CON(34), 2),
1031 RK_MUX(0, "clk_i2sout_src", mux_i2sch_parents, CLKSEL_CON(31), __BITS(1,0)),
1032 RK_COMPOSITE(RK3399_SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_parents,
1033 CLKSEL_CON(31), /* muxdiv_reg */
1034 __BIT(2), /* mux_mask */
1035 0, /* div_mask */
1036 CLKGATE_CON(8), /* gate_reg */
1037 __BIT(12), /* gate_mask */
1038 RK_COMPOSITE_SET_RATE_PARENT),
1039
1040 /* eDP */
1041 RK_COMPOSITE(RK3399_PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_parents,
1042 CLKSEL_CON(44), /* muxdiv_reg */
1043 __BIT(15), /* mux_mask */
1044 __BITS(13,8), /* div_mask */
1045 CLKGATE_CON(11), /* gate_reg */
1046 __BIT(11), /* gate_mask */
1047 0),
1048 RK_GATE(RK3399_PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLKGATE_CON(32), 12),
1049 RK_GATE(RK3399_PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLKGATE_CON(32), 13),
1050
1051 RK_COMPOSITE(RK3399_SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_parents,
1052 CLKSEL_CON(46), /* muxdiv_reg */
1053 __BITS(7,6), /* mux_mask */
1054 __BITS(4,0), /* div_mask */
1055 CLKGATE_CON(11), /* gate_reg */
1056 __BIT(8), /* gate_mask */
1057 0),
1058 RK_GATE(RK3399_PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLKGATE_CON(29), 7),
1059
1060 };
1061
1062 static const struct rk3399_init_param {
1063 const char *clk;
1064 const char *parent;
1065 } rk3399_init_params[] = {
1066 { .clk = "clk_i2s0_mux", .parent = "clk_i2s0_frac" },
1067 { .clk = "clk_i2s1_mux", .parent = "clk_i2s1_frac" },
1068 { .clk = "clk_i2s2_mux", .parent = "clk_i2s2_frac" },
1069 { .clk = "dclk_vop0_div", .parent = "gpll" },
1070 { .clk = "dclk_vop1_div", .parent = "gpll" },
1071 { .clk = "dclk_vop0", .parent = "dclk_vop0_frac" },
1072 { .clk = "dclk_vop1", .parent = "dclk_vop1_frac" },
1073 };
1074
1075 static void
rk3399_cru_init(struct rk_cru_softc * sc)1076 rk3399_cru_init(struct rk_cru_softc *sc)
1077 {
1078 struct rk_cru_clk *clk, *pclk;
1079 uint32_t write_mask, write_val;
1080 int error;
1081 u_int n;
1082
1083 /*
1084 * Force an update of BPLL to bring it out of slow mode.
1085 */
1086 clk = rk_cru_clock_find(sc, "armclkb");
1087 clk_set_rate(&clk->base, clk_get_rate(&clk->base));
1088
1089 /*
1090 * Set DCLK_VOP0 and DCLK_VOP1 dividers to 1.
1091 */
1092 write_mask = __BITS(7,0) << 16;
1093 write_val = 0;
1094 CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val);
1095 CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val);
1096
1097 /*
1098 * Set defaults
1099 */
1100 for (n = 0; n < __arraycount(rk3399_init_params); n++) {
1101 const struct rk3399_init_param *param = &rk3399_init_params[n];
1102 clk = rk_cru_clock_find(sc, param->clk);
1103 KASSERTMSG(clk != NULL, "couldn't find clock %s", param->clk);
1104 if (param->parent != NULL) {
1105 pclk = rk_cru_clock_find(sc, param->parent);
1106 KASSERTMSG(pclk != NULL, "couldn't find clock %s", param->parent);
1107 error = clk_set_parent(&clk->base, &pclk->base);
1108 if (error != 0) {
1109 aprint_error_dev(sc->sc_dev, "couldn't set %s parent to %s: %d\n",
1110 param->clk, param->parent, error);
1111 continue;
1112 }
1113 }
1114 }
1115 }
1116
1117 static int
rk3399_cru_match(device_t parent,cfdata_t cf,void * aux)1118 rk3399_cru_match(device_t parent, cfdata_t cf, void *aux)
1119 {
1120 struct fdt_attach_args * const faa = aux;
1121
1122 return of_compatible_match(faa->faa_phandle, compat_data);
1123 }
1124
1125 static void
rk3399_cru_attach(device_t parent,device_t self,void * aux)1126 rk3399_cru_attach(device_t parent, device_t self, void *aux)
1127 {
1128 struct rk_cru_softc * const sc = device_private(self);
1129 struct fdt_attach_args * const faa = aux;
1130
1131 sc->sc_dev = self;
1132 sc->sc_phandle = faa->faa_phandle;
1133 sc->sc_bst = faa->faa_bst;
1134
1135 sc->sc_clks = rk3399_cru_clks;
1136 sc->sc_nclks = __arraycount(rk3399_cru_clks);
1137
1138 sc->sc_grf_soc_status = 0x0480;
1139 sc->sc_softrst_base = SOFTRST_CON(0);
1140
1141 if (rk_cru_attach(sc) != 0)
1142 return;
1143
1144 aprint_naive("\n");
1145 aprint_normal(": RK3399 CRU\n");
1146
1147 rk3399_cru_init(sc);
1148
1149 rk_cru_print(sc);
1150 }
1151