1 /* $NetBSD: imx6_spi.c,v 1.8 2023/05/04 13:29:33 bouyer Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Genetec Corporation. All rights reserved.
5 * Written by Hashimoto Kenichi for Genetec Corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: imx6_spi.c,v 1.8 2023/05/04 13:29:33 bouyer Exp $");
31
32 #include "opt_imxspi.h"
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/kmem.h>
38 #include <sys/gpio.h>
39
40 #include <arm/imx/imxspivar.h>
41
42 #include <dev/fdt/fdtvar.h>
43
44 struct imxspi_fdt_softc {
45 struct imxspi_softc sc_imxspi; /* Must be first */
46
47 struct spi_chipset_tag sc_tag;
48 struct clk *sc_clk;
49
50 struct fdtbus_gpio_pin **sc_pin_cs;
51 };
52
53 struct imx_spi_config {
54 bool enhanced;
55 enum imxspi_type type;
56 };
57
58 static const struct imx_spi_config imx6q_spi_config = {
59 .enhanced = true,
60 .type = IMX51_ECSPI,
61 };
62
63 static const struct device_compatible_entry compat_data[] = {
64 { .compat = "fsl,imx6q-ecspi", .data = &imx6q_spi_config },
65 { .compat = "fsl,imx6sx-ecspi", .data = &imx6q_spi_config },
66 DEVICE_COMPAT_EOL
67 };
68
69 CFATTACH_DECL_NEW(imxspi_fdt, sizeof(struct imxspi_fdt_softc),
70 imxspi_match, imxspi_attach, NULL, NULL);
71
72 static int
imxspi_cs_enable(void * arg,int slave)73 imxspi_cs_enable(void *arg, int slave)
74 {
75 struct imxspi_fdt_softc * const sc = arg;
76 fdtbus_gpio_write(sc->sc_pin_cs[slave], 1);
77 return 0;
78 }
79
80 static int
imxspi_cs_disable(void * arg,int slave)81 imxspi_cs_disable(void *arg, int slave)
82 {
83 struct imxspi_fdt_softc * const sc = arg;
84 fdtbus_gpio_write(sc->sc_pin_cs[slave], 0);
85 return 0;
86 }
87
88 int
imxspi_match(device_t parent,cfdata_t cf,void * aux)89 imxspi_match(device_t parent, cfdata_t cf, void *aux)
90 {
91 struct fdt_attach_args * const faa = aux;
92
93 return of_compatible_match(faa->faa_phandle, compat_data);
94 }
95
96 void
imxspi_attach(device_t parent,device_t self,void * aux)97 imxspi_attach(device_t parent, device_t self, void *aux)
98 {
99 struct imxspi_fdt_softc * const ifsc = device_private(self);
100 struct imxspi_softc * const sc = &ifsc->sc_imxspi;
101 struct fdt_attach_args * const faa = aux;
102 char intrstr[128];
103 const int phandle = faa->faa_phandle;
104 bus_addr_t addr;
105 bus_size_t size;
106 int error;
107
108 aprint_naive("\n");
109 aprint_normal(": SPI\n");
110
111 u_int nslaves;
112 error = of_getprop_uint32(phandle, "fsl,spi-num-chipselects", &nslaves);
113 if (error)
114 nslaves = 4;
115
116 ifsc->sc_pin_cs = kmem_alloc(sizeof(struct fdtbus_gpio_pin *) * nslaves, KM_SLEEP);
117
118 for (int i = 0; i < nslaves; i++) {
119 ifsc->sc_pin_cs[i] = fdtbus_gpio_acquire_index(phandle, "cs-gpios", i,
120 GPIO_PIN_OUTPUT);
121 }
122
123 ifsc->sc_clk = fdtbus_clock_get_index(phandle, 0);
124 if (ifsc->sc_clk == NULL) {
125 aprint_error(": couldn't get clock\n");
126 return;
127 }
128
129 error = clk_enable(ifsc->sc_clk);
130 if (error) {
131 aprint_error_dev(sc->sc_dev, "couldn't enable: %d\n", error);
132 return;
133 }
134
135 ifsc->sc_tag.cookie = ifsc;
136 ifsc->sc_tag.spi_cs_enable = imxspi_cs_enable;
137 ifsc->sc_tag.spi_cs_disable = imxspi_cs_disable;
138
139 sc->sc_phandle = phandle;
140 sc->sc_iot = faa->faa_bst;
141
142 const struct imx_spi_config *config =
143 of_compatible_lookup(phandle, compat_data)->data;
144 sc->sc_enhanced = config->enhanced;
145 sc->sc_type = config->type;
146
147 sc->sc_nslaves = nslaves;
148 sc->sc_freq = clk_get_rate(ifsc->sc_clk);
149 sc->sc_tag = &ifsc->sc_tag;
150
151 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
152 aprint_error(": couldn't get iomux registers\n");
153 return;
154 }
155
156 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) {
157 aprint_error_dev(sc->sc_dev, "couldn't map registers\n");
158 return;
159 }
160
161 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) {
162 aprint_error_dev(self, "failed to decode interrupt\n");
163 return;
164 }
165
166 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM,
167 0, imxspi_intr, &ifsc->sc_imxspi, device_xname(self));
168 if (sc->sc_ih == NULL) {
169 aprint_error_dev(self, "couldn't establish interrupt on %s\n",
170 intrstr);
171 return;
172 }
173 aprint_normal_dev(self, "interrupting on %s\n", intrstr);
174
175 imxspi_attach_common(self);
176 }
177