1 /* $NetBSD: imxuart.c,v 1.30 2022/10/26 23:38:06 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec Corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30 /*
31 * derived from sys/dev/ic/com.c
32 */
33
34 /*-
35 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
36 * All rights reserved.
37 *
38 * This code is derived from software contributed to The NetBSD Foundation
39 * by Charles M. Hannum.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60 * POSSIBILITY OF SUCH DAMAGE.
61 */
62
63 /*
64 * Copyright (c) 1991 The Regents of the University of California.
65 * All rights reserved.
66 *
67 * Redistribution and use in source and binary forms, with or without
68 * modification, are permitted provided that the following conditions
69 * are met:
70 * 1. Redistributions of source code must retain the above copyright
71 * notice, this list of conditions and the following disclaimer.
72 * 2. Redistributions in binary form must reproduce the above copyright
73 * notice, this list of conditions and the following disclaimer in the
74 * documentation and/or other materials provided with the distribution.
75 * 3. Neither the name of the University nor the names of its contributors
76 * may be used to endorse or promote products derived from this software
77 * without specific prior written permission.
78 *
79 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
80 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
82 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
85 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
86 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
87 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
88 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
89 * SUCH DAMAGE.
90 *
91 * @(#)com.c 7.5 (Berkeley) 5/16/91
92 */
93
94 /*
95 * driver for UART in i.MX SoC.
96 */
97
98 #include <sys/cdefs.h>
99 __KERNEL_RCSID(0, "$NetBSD: imxuart.c,v 1.30 2022/10/26 23:38:06 riastradh Exp $");
100
101 #include "opt_imxuart.h"
102 #include "opt_ddb.h"
103 #include "opt_ddbparam.h"
104 #include "opt_kgdb.h"
105 #include "opt_lockdebug.h"
106 #include "opt_multiprocessor.h"
107 #include "opt_ntp.h"
108 #include "opt_imxuart.h"
109
110 #ifdef RND_COM
111 #include <sys/rndsource.h>
112 #endif
113
114 #ifndef IMXUART_TOLERANCE
115 #define IMXUART_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */
116 #endif
117
118 #ifndef IMXUART_FREQDIV
119 #define IMXUART_FREQDIV 2 /* XXX */
120 #endif
121
122 #ifndef IMXUART_FREQ
123 #define IMXUART_FREQ (56900000)
124 #endif
125
126 /*
127 * Override cnmagic(9) macro before including <sys/systm.h>.
128 * We need to know if cn_check_magic triggered debugger, so set a flag.
129 * Callers of cn_check_magic must declare int cn_trapped = 0;
130 * XXX: this is *ugly*!
131 */
132 #define cn_trap() \
133 do { \
134 console_debugger(); \
135 cn_trapped = 1; \
136 } while (/* CONSTCOND */ 0)
137
138 #include <sys/param.h>
139 #include <sys/systm.h>
140 #include <sys/ioctl.h>
141 #include <sys/select.h>
142 #include <sys/poll.h>
143 #include <sys/tty.h>
144 #include <sys/proc.h>
145 #include <sys/conf.h>
146 #include <sys/file.h>
147 #include <sys/uio.h>
148 #include <sys/kernel.h>
149 #include <sys/syslog.h>
150 #include <sys/device.h>
151 #include <sys/kmem.h>
152 #include <sys/timepps.h>
153 #include <sys/vnode.h>
154 #include <sys/kauth.h>
155 #include <sys/intr.h>
156
157 #include <sys/bus.h>
158
159 #include <ddb/db_active.h>
160
161 #include <arm/imx/imxuartreg.h>
162 #include <arm/imx/imxuartvar.h>
163 #include <dev/cons.h>
164
165 #ifndef IMXUART_RING_SIZE
166 #define IMXUART_RING_SIZE 2048
167 #endif
168
169 int imxuspeed(long, struct imxuart_baudrate_ratio *);
170 int imxuparam(struct tty *, struct termios *);
171 void imxustart(struct tty *);
172 int imxuhwiflow(struct tty *, int);
173
174 void imxuart_shutdown(struct imxuart_softc *);
175 void imxuart_loadchannelregs(struct imxuart_softc *);
176 void imxuart_hwiflow(struct imxuart_softc *);
177 void imxuart_break(struct imxuart_softc *, bool);
178 void imxuart_modem(struct imxuart_softc *, int);
179 void tiocm_to_imxu(struct imxuart_softc *, u_long, int);
180 int imxuart_to_tiocm(struct imxuart_softc *);
181 void imxuart_iflush(struct imxuart_softc *);
182 int imxuintr(void *);
183
184 int imxuart_common_getc(dev_t, struct imxuart_regs *);
185 void imxuart_common_putc(dev_t, struct imxuart_regs *, int);
186
187
188 int imxuart_init(struct imxuart_regs *, int, tcflag_t, int);
189
190 int imxucngetc(dev_t);
191 void imxucnputc(dev_t, int);
192 void imxucnpollc(dev_t, int);
193
194 static void imxuintr_read(struct imxuart_softc *);
195 static void imxuintr_send(struct imxuart_softc *);
196
197 static void imxuart_enable_debugport(struct imxuart_softc *);
198 static void imxuart_disable_all_interrupts(struct imxuart_softc *);
199 static void imxuart_control_rxint(struct imxuart_softc *, bool);
200 static void imxuart_control_txint(struct imxuart_softc *, bool);
201 static u_int imxuart_txfifo_space(struct imxuart_softc *sc);
202
203 static uint32_t cflag_to_ucr2(tcflag_t, uint32_t);
204
205 #define integrate static inline
206 void imxusoft(void *);
207 integrate void imxuart_rxsoft(struct imxuart_softc *, struct tty *);
208 integrate void imxuart_txsoft(struct imxuart_softc *, struct tty *);
209 integrate void imxuart_stsoft(struct imxuart_softc *, struct tty *);
210 integrate void imxuart_schedrx(struct imxuart_softc *);
211 void imxudiag(void *);
212 static void imxuart_load_speed(struct imxuart_softc *);
213 static void imxuart_load_params(struct imxuart_softc *);
214 integrate void imxuart_load_pendings(struct imxuart_softc *);
215
216
217 extern struct cfdriver imxuart_cd;
218
219 dev_type_open(imxuopen);
220 dev_type_close(imxuclose);
221 dev_type_read(imxuread);
222 dev_type_write(imxuwrite);
223 dev_type_ioctl(imxuioctl);
224 dev_type_stop(imxustop);
225 dev_type_tty(imxutty);
226 dev_type_poll(imxupoll);
227
228 const struct cdevsw imxcom_cdevsw = {
229 .d_open = imxuopen,
230 .d_close = imxuclose,
231 .d_read = imxuread,
232 .d_write = imxuwrite,
233 .d_ioctl = imxuioctl,
234 .d_stop = imxustop,
235 .d_tty = imxutty,
236 .d_poll = imxupoll,
237 .d_mmap = nommap,
238 .d_kqfilter = ttykqfilter,
239 .d_discard = nodiscard,
240 .d_flag = D_TTY
241 };
242
243 /*
244 * Make this an option variable one can patch.
245 * But be warned: this must be a power of 2!
246 */
247 u_int imxuart_rbuf_size = IMXUART_RING_SIZE;
248
249 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
250 u_int imxuart_rbuf_hiwat = (IMXUART_RING_SIZE * 1) / 4;
251 u_int imxuart_rbuf_lowat = (IMXUART_RING_SIZE * 3) / 4;
252
253 static struct imxuart_regs imxuconsregs;
254 static int imxuconsattached;
255 static int imxuconsrate;
256 static tcflag_t imxuconscflag;
257 static struct cnm_state imxuart_cnm_state;
258
259 u_int imxuart_freq = IMXUART_FREQ;
260 u_int imxuart_freqdiv = IMXUART_FREQDIV;
261
262 #ifdef KGDB
263 #include <sys/kgdb.h>
264
265 static struct imxuart_regs imxu_kgdb_regs;
266 static int imxu_kgdb_attached;
267
268 int imxuart_kgdb_getc(void *);
269 void imxuart_kgdb_putc(void *, int);
270 #endif /* KGDB */
271
272 #define IMXUART_DIALOUT_MASK TTDIALOUT_MASK
273
274 #define IMXUART_UNIT(x) TTUNIT(x)
275 #define IMXUART_DIALOUT(x) TTDIALOUT(x)
276
277 #define IMXUART_ISALIVE(sc) ((sc)->enabled != 0 && \
278 device_is_active((sc)->sc_dev))
279
280 #define BR BUS_SPACE_BARRIER_READ
281 #define BW BUS_SPACE_BARRIER_WRITE
282 #define IMXUART_BARRIER(r, f) \
283 bus_space_barrier((r)->ur_iot, (r)->ur_ioh, 0, IMX_UART_SIZE, (f))
284
285
286 void
imxuart_attach_common(device_t parent,device_t self,bus_space_tag_t iot,paddr_t iobase,size_t size,int intr,int flags)287 imxuart_attach_common(device_t parent, device_t self,
288 bus_space_tag_t iot, paddr_t iobase, size_t size, int intr, int flags)
289 {
290 struct imxuart_softc *sc = device_private(self);
291 struct imxuart_regs *regsp = &sc->sc_regs;
292 bus_space_handle_t ioh;
293
294 aprint_naive("\n");
295 aprint_normal("\n");
296
297 sc->sc_dev = self;
298
299 if (size <= 0)
300 size = IMX_UART_SIZE;
301
302 sc->sc_intr = intr;
303 regsp->ur_iot = iot;
304 regsp->ur_iobase = iobase;
305
306 if (bus_space_map(iot, regsp->ur_iobase, size, 0, &ioh)) {
307 return;
308 }
309 regsp->ur_ioh = ioh;
310
311 sc->sc_ih = intr_establish(sc->sc_intr, IPL_SERIAL, IST_LEVEL,
312 imxuintr, sc);
313 if (sc->sc_ih == NULL) {
314 aprint_error_dev(sc->sc_dev, "intr_establish failed\n");
315 return;
316 }
317
318 imxuart_attach_subr(sc);
319 }
320
321 void
imxuart_attach_subr(struct imxuart_softc * sc)322 imxuart_attach_subr(struct imxuart_softc *sc)
323 {
324 struct imxuart_regs *regsp = &sc->sc_regs;
325 bus_space_tag_t iot = regsp->ur_iot;
326 bus_space_handle_t ioh = regsp->ur_ioh;
327 struct tty *tp;
328
329 callout_init(&sc->sc_diag_callout, 0);
330 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
331
332 if (regsp->ur_iobase != imxuconsregs.ur_iobase)
333 imxuart_init(&sc->sc_regs, TTYDEF_SPEED, TTYDEF_CFLAG, false);
334
335 bus_space_read_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4);
336 sc->sc_ucr2_d = sc->sc_ucr2;
337
338 /* Disable interrupts before configuring the device. */
339 imxuart_disable_all_interrupts(sc);
340
341 if (regsp->ur_iobase == imxuconsregs.ur_iobase) {
342 imxuconsattached = 1;
343
344 /* Make sure the console is always "hardwired". */
345 #if 0
346 delay(10000); /* wait for output to finish */
347 #endif
348 SET(sc->sc_hwflags, IMXUART_HW_CONSOLE);
349 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
350 }
351
352
353 tp = tty_alloc();
354 tp->t_oproc = imxustart;
355 tp->t_param = imxuparam;
356 tp->t_hwiflow = imxuhwiflow;
357
358 sc->sc_tty = tp;
359 sc->sc_rbuf = kmem_alloc(sizeof (*sc->sc_rbuf) * imxuart_rbuf_size,
360 KM_SLEEP);
361 sc->sc_rbuf_size = imxuart_rbuf_size;
362 sc->sc_rbuf_in = sc->sc_rbuf_out = 0;
363 sc->sc_txfifo_len = 32;
364 sc->sc_txfifo_thresh = 16; /* when USR1.TRDY, fifo has space
365 * for this many characters */
366
367 tty_attach(tp);
368
369 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) {
370 int maj;
371
372 /* locate the major number */
373 maj = cdevsw_lookup_major(&imxcom_cdevsw);
374
375 if (maj != NODEVMAJOR) {
376 tp->t_dev = cn_tab->cn_dev = makedev(maj,
377 device_unit(sc->sc_dev));
378
379 aprint_normal_dev(sc->sc_dev, "console\n");
380 }
381 }
382
383 #ifdef KGDB
384 /*
385 * Allow kgdb to "take over" this port. If this is
386 * not the console and is the kgdb device, it has
387 * exclusive use. If it's the console _and_ the
388 * kgdb device, it doesn't.
389 */
390 if (regsp->ur_iobase == imxu_kgdb_regs.ur_iobase) {
391 if (!ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) {
392 imxu_kgdb_attached = 1;
393
394 SET(sc->sc_hwflags, IMXUART_HW_KGDB);
395 }
396 aprint_normal_dev(sc->sc_dev, "kgdb\n");
397 }
398 #endif
399
400 sc->sc_si = softint_establish(SOFTINT_SERIAL, imxusoft, sc);
401
402 #ifdef RND_COM
403 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
404 RND_TYPE_TTY, RND_FLAG_COLLECT_TIME |
405 RND_FLAG_ESTIMATE_TIME);
406 #endif
407
408 /* if there are no enable/disable functions, assume the device
409 is always enabled */
410 if (!sc->enable)
411 sc->enabled = 1;
412
413 imxuart_enable_debugport(sc);
414
415 SET(sc->sc_hwflags, IMXUART_HW_DEV_OK);
416
417 //shutdownhook_establish(imxuart_shutdownhook, sc);
418
419
420 #if 0
421 {
422 uint32_t reg;
423 reg = bus_space_read_4(iot, ioh, IMX_UCR1);
424 reg |= IMX_UCR1_TXDMAEN | IMX_UCR1_RXDMAEN;
425 bus_space_write_4(iot, ioh, IMX_UCR1, reg);
426 }
427 #endif
428 }
429
430 /*
431 * baudrate = RefFreq / (16 * (UMBR + 1)/(UBIR + 1))
432 *
433 * (UBIR + 1) / (UBMR + 1) = (16 * BaurdRate) / RefFreq
434 */
435
436 static long
gcd(long m,long n)437 gcd(long m, long n)
438 {
439
440 if (m < n)
441 return gcd(n, m);
442
443 if (n <= 0)
444 return m;
445 return gcd(n, m % n);
446 }
447
448 int
imxuspeed(long speed,struct imxuart_baudrate_ratio * ratio)449 imxuspeed(long speed, struct imxuart_baudrate_ratio *ratio)
450 {
451 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
452 long b = 16 * speed;
453 long f = imxuart_freq / imxuart_freqdiv;
454 long d;
455 int err = 0;
456
457 /* reduce b/f */
458 while ((f > (1<<16) || b > (1<<16)) && (d = gcd(f, b)) > 1) {
459 f /= d;
460 b /= d;
461 }
462
463
464 while (f > (1<<16) || b > (1<<16)) {
465 f /= 2;
466 b /= 2;
467 }
468 if (f <= 0 || b <= 0)
469 return -1;
470
471 #ifdef DIAGNOSTIC
472 err = divrnd(((uint64_t)imxuart_freq) * 1000 / imxuart_freqdiv,
473 (uint64_t)speed * 16 * f / b) - 1000;
474 if (err < 0)
475 err = -err;
476 #endif
477
478 ratio->numerator = b-1;
479 ratio->modulator = f-1;
480
481 if (err > IMXUART_TOLERANCE)
482 return -1;
483
484 return 0;
485 #undef divrnd
486 }
487
488 #ifdef IMXUART_DEBUG
489 int imxuart_debug = 0;
490
491 void imxustatus(struct imxuart_softc *, const char *);
492 void
imxustatus(struct imxuart_softc * sc,const char * str)493 imxustatus(struct imxuart_softc *sc, const char *str)
494 {
495 struct tty *tp = sc->sc_tty;
496
497 aprint_normal_dev(sc->sc_dev,
498 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n",
499 str,
500 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-',
501 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-',
502 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-',
503 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-',
504 sc->sc_tx_stopped ? '+' : '-');
505
506 aprint_normal_dev(sc->sc_dev,
507 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n",
508 str,
509 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-',
510 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-',
511 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-',
512 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-',
513 sc->sc_rx_flags);
514 }
515 #endif
516
517 #if 0
518 int
519 imxuart_detach(device_t self, int flags)
520 {
521 struct imxuart_softc *sc = device_private(self);
522 int maj, mn;
523
524 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE))
525 return EBUSY;
526
527 /* locate the major number */
528 maj = cdevsw_lookup_major(&imxcom_cdevsw);
529
530 /* Nuke the vnodes for any open instances. */
531 mn = device_unit(self);
532 vdevgone(maj, mn, mn, VCHR);
533
534 mn |= IMXUART_DIALOUT_MASK;
535 vdevgone(maj, mn, mn, VCHR);
536
537 if (sc->sc_rbuf == NULL) {
538 /*
539 * Ring buffer allocation failed in the imxuart_attach_subr,
540 * only the tty is allocated, and nothing else.
541 */
542 tty_free(sc->sc_tty);
543 return 0;
544 }
545
546 /* Free the receive buffer. */
547 kmem_free(sc->sc_rbuf, sizeof(*sc->sc_rbuf) * sc->sc_rbuf_size);
548
549 /* Detach and free the tty. */
550 tty_detach(sc->sc_tty);
551 tty_free(sc->sc_tty);
552
553 /* Unhook the soft interrupt handler. */
554 softint_disestablish(sc->sc_si);
555
556 #ifdef RND_COM
557 /* Unhook the entropy source. */
558 rnd_detach_source(&sc->rnd_source);
559 #endif
560 callout_destroy(&sc->sc_diag_callout);
561
562 /* Destroy the lock. */
563 mutex_destroy(&sc->sc_lock);
564
565 return (0);
566 }
567 #endif
568
569 #ifdef notyet
570 int
imxuart_activate(device_t self,enum devact act)571 imxuart_activate(device_t self, enum devact act)
572 {
573 struct imxuart_softc *sc = device_private(self);
574 int rv = 0;
575
576 switch (act) {
577 case DVACT_ACTIVATE:
578 rv = EOPNOTSUPP;
579 break;
580
581 case DVACT_DEACTIVATE:
582 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) {
583 rv = EBUSY;
584 break;
585 }
586
587 if (sc->disable != NULL && sc->enabled != 0) {
588 (*sc->disable)(sc);
589 sc->enabled = 0;
590 }
591 break;
592 }
593
594 return (rv);
595 }
596 #endif
597
598 void
imxuart_shutdown(struct imxuart_softc * sc)599 imxuart_shutdown(struct imxuart_softc *sc)
600 {
601 struct tty *tp = sc->sc_tty;
602
603 mutex_spin_enter(&sc->sc_lock);
604
605 /* If we were asserting flow control, then deassert it. */
606 SET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED);
607 imxuart_hwiflow(sc);
608
609 /* Clear any break condition set with TIOCSBRK. */
610 imxuart_break(sc, false);
611
612 /*
613 * Hang up if necessary. Wait a bit, so the other side has time to
614 * notice even if we immediately open the port again.
615 * Avoid tsleeping above splhigh().
616 */
617 if (ISSET(tp->t_cflag, HUPCL)) {
618 imxuart_modem(sc, 0);
619 mutex_spin_exit(&sc->sc_lock);
620 /* XXX will only timeout */
621 (void) kpause(ttclos, false, hz, NULL);
622 mutex_spin_enter(&sc->sc_lock);
623 }
624
625 /* Turn off interrupts. */
626 imxuart_disable_all_interrupts(sc);
627 /* re-enable recv interrupt for console or kgdb port */
628 imxuart_enable_debugport(sc);
629
630 mutex_spin_exit(&sc->sc_lock);
631
632 #ifdef notyet
633 if (sc->disable) {
634 #ifdef DIAGNOSTIC
635 if (!sc->enabled)
636 panic("imxuart_shutdown: not enabled?");
637 #endif
638 (*sc->disable)(sc);
639 sc->enabled = 0;
640 }
641 #endif
642 }
643
644 int
imxuopen(dev_t dev,int flag,int mode,struct lwp * l)645 imxuopen(dev_t dev, int flag, int mode, struct lwp *l)
646 {
647 struct imxuart_softc *sc;
648 struct tty *tp;
649 int s;
650 int error;
651
652 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev));
653 if (sc == NULL || !ISSET(sc->sc_hwflags, IMXUART_HW_DEV_OK) ||
654 sc->sc_rbuf == NULL)
655 return (ENXIO);
656
657 if (!device_is_active(sc->sc_dev))
658 return (ENXIO);
659
660 #ifdef KGDB
661 /*
662 * If this is the kgdb port, no other use is permitted.
663 */
664 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB))
665 return (EBUSY);
666 #endif
667
668 tp = sc->sc_tty;
669
670 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
671 return (EBUSY);
672
673 s = spltty();
674
675 /*
676 * Do the following iff this is a first open.
677 */
678 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
679 struct termios t;
680
681 tp->t_dev = dev;
682
683
684 #ifdef notyet
685 if (sc->enable) {
686 if ((*sc->enable)(sc)) {
687 splx(s);
688 aprint_error_dev(sc->sc_dev,
689 "device enable failed\n");
690 return (EIO);
691 }
692 sc->enabled = 1;
693 }
694 #endif
695
696 mutex_spin_enter(&sc->sc_lock);
697
698 imxuart_disable_all_interrupts(sc);
699
700 /* Fetch the current modem control status, needed later. */
701
702 #ifdef IMXUART_PPS
703 /* Clear PPS capture state on first open. */
704 mutex_spin_enter(&timecounter_lock);
705 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state));
706 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
707 pps_init(&sc->sc_pps_state);
708 mutex_spin_exit(&timecounter_lock);
709 #endif
710
711 mutex_spin_exit(&sc->sc_lock);
712
713 /*
714 * Initialize the termios status to the defaults. Add in the
715 * sticky bits from TIOCSFLAGS.
716 */
717 if (ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) {
718 t.c_ospeed = imxuconsrate;
719 t.c_cflag = imxuconscflag;
720 } else {
721 t.c_ospeed = TTYDEF_SPEED;
722 t.c_cflag = TTYDEF_CFLAG;
723 }
724 t.c_ispeed = t.c_ospeed;
725 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
726 SET(t.c_cflag, CLOCAL);
727 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
728 SET(t.c_cflag, CRTSCTS);
729 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
730 SET(t.c_cflag, MDMBUF);
731 /* Make sure imxuparam() will do something. */
732 tp->t_ospeed = 0;
733 (void) imxuparam(tp, &t);
734 tp->t_iflag = TTYDEF_IFLAG;
735 tp->t_oflag = TTYDEF_OFLAG;
736 tp->t_lflag = TTYDEF_LFLAG;
737 ttychars(tp);
738 ttsetwater(tp);
739
740 mutex_spin_enter(&sc->sc_lock);
741
742 /*
743 * Turn on DTR. We must always do this, even if carrier is not
744 * present, because otherwise we'd have to use TIOCSDTR
745 * immediately after setting CLOCAL, which applications do not
746 * expect. We always assert DTR while the device is open
747 * unless explicitly requested to deassert it.
748 */
749 imxuart_modem(sc, 1);
750
751 /* Clear the input ring, and unblock. */
752 sc->sc_rbuf_in = sc->sc_rbuf_out = 0;
753 imxuart_iflush(sc);
754 CLR(sc->sc_rx_flags, IMXUART_RX_ANY_BLOCK);
755 imxuart_hwiflow(sc);
756
757 /* Turn on interrupts. */
758 imxuart_control_rxint(sc, true);
759
760 #ifdef IMXUART_DEBUG
761 if (imxuart_debug)
762 imxustatus(sc, "imxuopen ");
763 #endif
764
765 mutex_spin_exit(&sc->sc_lock);
766 }
767
768 splx(s);
769
770 #if 0
771 error = ttyopen(tp, IMXUART_DIALOUT(dev), ISSET(flag, O_NONBLOCK));
772 #else
773 error = ttyopen(tp, 1, ISSET(flag, O_NONBLOCK));
774 #endif
775 if (error)
776 goto bad;
777
778 error = (*tp->t_linesw->l_open)(dev, tp);
779 if (error)
780 goto bad;
781
782 return (0);
783
784 bad:
785 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
786 /*
787 * We failed to open the device, and nobody else had it opened.
788 * Clean up the state as appropriate.
789 */
790 imxuart_shutdown(sc);
791 }
792
793 return (error);
794 }
795
796 int
imxuclose(dev_t dev,int flag,int mode,struct lwp * l)797 imxuclose(dev_t dev, int flag, int mode, struct lwp *l)
798 {
799 struct imxuart_softc *sc =
800 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev));
801 struct tty *tp = sc->sc_tty;
802
803 /* XXX This is for cons.c. */
804 if (!ISSET(tp->t_state, TS_ISOPEN))
805 return (0);
806
807 (*tp->t_linesw->l_close)(tp, flag);
808 ttyclose(tp);
809
810 if (IMXUART_ISALIVE(sc) == 0)
811 return (0);
812
813 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
814 /*
815 * Although we got a last close, the device may still be in
816 * use; e.g. if this was the dialout node, and there are still
817 * processes waiting for carrier on the non-dialout node.
818 */
819 imxuart_shutdown(sc);
820 }
821
822 return (0);
823 }
824
825 int
imxuread(dev_t dev,struct uio * uio,int flag)826 imxuread(dev_t dev, struct uio *uio, int flag)
827 {
828 struct imxuart_softc *sc =
829 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev));
830 struct tty *tp = sc->sc_tty;
831
832 if (IMXUART_ISALIVE(sc) == 0)
833 return (EIO);
834
835 return ((*tp->t_linesw->l_read)(tp, uio, flag));
836 }
837
838 int
imxuwrite(dev_t dev,struct uio * uio,int flag)839 imxuwrite(dev_t dev, struct uio *uio, int flag)
840 {
841 struct imxuart_softc *sc =
842 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev));
843 struct tty *tp = sc->sc_tty;
844
845 if (IMXUART_ISALIVE(sc) == 0)
846 return (EIO);
847
848 return ((*tp->t_linesw->l_write)(tp, uio, flag));
849 }
850
851 int
imxupoll(dev_t dev,int events,struct lwp * l)852 imxupoll(dev_t dev, int events, struct lwp *l)
853 {
854 struct imxuart_softc *sc =
855 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev));
856 struct tty *tp = sc->sc_tty;
857
858 if (IMXUART_ISALIVE(sc) == 0)
859 return (POLLHUP);
860
861 return ((*tp->t_linesw->l_poll)(tp, events, l));
862 }
863
864 struct tty *
imxutty(dev_t dev)865 imxutty(dev_t dev)
866 {
867 struct imxuart_softc *sc =
868 device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev));
869 struct tty *tp = sc->sc_tty;
870
871 return (tp);
872 }
873
874 int
imxuioctl(dev_t dev,u_long cmd,void * data,int flag,struct lwp * l)875 imxuioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
876 {
877 struct imxuart_softc *sc;
878 struct tty *tp;
879 int error;
880
881 sc = device_lookup_private(&imxuart_cd, IMXUART_UNIT(dev));
882 if (sc == NULL)
883 return ENXIO;
884 if (IMXUART_ISALIVE(sc) == 0)
885 return (EIO);
886
887 tp = sc->sc_tty;
888
889 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
890 if (error != EPASSTHROUGH)
891 return (error);
892
893 error = ttioctl(tp, cmd, data, flag, l);
894 if (error != EPASSTHROUGH)
895 return (error);
896
897 error = 0;
898 switch (cmd) {
899 case TIOCSFLAGS:
900 error = kauth_authorize_device_tty(l->l_cred,
901 KAUTH_DEVICE_TTY_PRIVSET, tp);
902 break;
903 default:
904 /* nothing */
905 break;
906 }
907 if (error) {
908 return error;
909 }
910
911 mutex_spin_enter(&sc->sc_lock);
912
913 switch (cmd) {
914 case TIOCSBRK:
915 imxuart_break(sc, true);
916 break;
917
918 case TIOCCBRK:
919 imxuart_break(sc, false);
920 break;
921
922 case TIOCSDTR:
923 imxuart_modem(sc, 1);
924 break;
925
926 case TIOCCDTR:
927 imxuart_modem(sc, 0);
928 break;
929
930 case TIOCGFLAGS:
931 *(int *)data = sc->sc_swflags;
932 break;
933
934 case TIOCSFLAGS:
935 sc->sc_swflags = *(int *)data;
936 break;
937
938 case TIOCMSET:
939 case TIOCMBIS:
940 case TIOCMBIC:
941 tiocm_to_imxu(sc, cmd, *(int *)data);
942 break;
943
944 case TIOCMGET:
945 *(int *)data = imxuart_to_tiocm(sc);
946 break;
947
948 #ifdef notyet
949 case PPS_IOC_CREATE:
950 case PPS_IOC_DESTROY:
951 case PPS_IOC_GETPARAMS:
952 case PPS_IOC_SETPARAMS:
953 case PPS_IOC_GETCAP:
954 case PPS_IOC_FETCH:
955 #ifdef PPS_SYNC
956 case PPS_IOC_KCBIND:
957 #endif
958 mutex_spin_enter(&timecounter_lock);
959 error = pps_ioctl(cmd, data, &sc->sc_pps_state);
960 mutex_spin_exit(&timecounter_lock);
961 break;
962
963 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */
964 mutex_spin_enter(&timecounter_lock);
965 #ifndef PPS_TRAILING_EDGE
966 TIMESPEC_TO_TIMEVAL((struct timeval *)data,
967 &sc->sc_pps_state.ppsinfo.assert_timestamp);
968 #else
969 TIMESPEC_TO_TIMEVAL((struct timeval *)data,
970 &sc->sc_pps_state.ppsinfo.clear_timestamp);
971 #endif
972 mutex_spin_exit(&timecounter_lock);
973 break;
974 #endif
975
976 default:
977 error = EPASSTHROUGH;
978 break;
979 }
980
981 mutex_spin_exit(&sc->sc_lock);
982
983 #ifdef IMXUART_DEBUG
984 if (imxuart_debug)
985 imxustatus(sc, "imxuioctl ");
986 #endif
987
988 return (error);
989 }
990
991 integrate void
imxuart_schedrx(struct imxuart_softc * sc)992 imxuart_schedrx(struct imxuart_softc *sc)
993 {
994 sc->sc_rx_ready = 1;
995
996 /* Wake up the poller. */
997 softint_schedule(sc->sc_si);
998 }
999
1000 void
imxuart_break(struct imxuart_softc * sc,bool onoff)1001 imxuart_break(struct imxuart_softc *sc, bool onoff)
1002 {
1003 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1004 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1005
1006 if (onoff)
1007 SET(sc->sc_ucr1, IMX_UCR1_SNDBRK);
1008 else
1009 CLR(sc->sc_ucr1, IMX_UCR1_SNDBRK);
1010
1011 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1);
1012 }
1013
1014 void
imxuart_modem(struct imxuart_softc * sc,int onoff)1015 imxuart_modem(struct imxuart_softc *sc, int onoff)
1016 {
1017 #ifdef notyet
1018 if (sc->sc_mcr_dtr == 0)
1019 return;
1020
1021 if (onoff)
1022 SET(sc->sc_mcr, sc->sc_mcr_dtr);
1023 else
1024 CLR(sc->sc_mcr, sc->sc_mcr_dtr);
1025
1026 if (!sc->sc_heldchange) {
1027 if (sc->sc_tx_busy) {
1028 sc->sc_heldtbc = sc->sc_tbc;
1029 sc->sc_tbc = 0;
1030 sc->sc_heldchange = 1;
1031 } else
1032 imxuart_loadchannelregs(sc);
1033 }
1034 #endif
1035 }
1036
1037 /*
1038 * RTS output is controlled by UCR2.CTS bit.
1039 * DTR output is controlled by UCR3.DSR bit.
1040 * (i.MX reference manual uses names in DCE mode)
1041 *
1042 * note: if UCR2.CTSC == 1 for automatic HW flow control, UCR2.CTS is ignored.
1043 */
1044 void
tiocm_to_imxu(struct imxuart_softc * sc,u_long how,int ttybits)1045 tiocm_to_imxu(struct imxuart_softc *sc, u_long how, int ttybits)
1046 {
1047 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1048 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1049
1050 uint32_t ucr2 = sc->sc_ucr2_d;
1051 uint32_t ucr3 = sc->sc_ucr3;
1052
1053 uint32_t ucr2_mask = 0;
1054 uint32_t ucr3_mask = 0;
1055
1056
1057 if (ISSET(ttybits, TIOCM_DTR))
1058 ucr3_mask = IMX_UCR3_DSR;
1059 if (ISSET(ttybits, TIOCM_RTS))
1060 ucr2_mask = IMX_UCR2_CTS;
1061
1062 switch (how) {
1063 case TIOCMBIC:
1064 CLR(ucr2, ucr2_mask);
1065 CLR(ucr3, ucr3_mask);
1066 break;
1067
1068 case TIOCMBIS:
1069 SET(ucr2, ucr2_mask);
1070 SET(ucr3, ucr3_mask);
1071 break;
1072
1073 case TIOCMSET:
1074 CLR(ucr2, ucr2_mask);
1075 CLR(ucr3, ucr3_mask);
1076 SET(ucr2, ucr2_mask);
1077 SET(ucr3, ucr3_mask);
1078 break;
1079 }
1080
1081 if (ucr3 != sc->sc_ucr3) {
1082 bus_space_write_4(iot, ioh, IMX_UCR3, ucr3);
1083 sc->sc_ucr3 = ucr3;
1084 }
1085
1086 if (ucr2 == sc->sc_ucr2_d)
1087 return;
1088
1089 sc->sc_ucr2_d = ucr2;
1090 /* update CTS bit only */
1091 ucr2 = (sc->sc_ucr2 & ~IMX_UCR2_CTS) |
1092 (ucr2 & IMX_UCR2_CTS);
1093
1094 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2);
1095 sc->sc_ucr2 = ucr2;
1096 }
1097
1098 int
imxuart_to_tiocm(struct imxuart_softc * sc)1099 imxuart_to_tiocm(struct imxuart_softc *sc)
1100 {
1101 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1102 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1103 int ttybits = 0;
1104 uint32_t usr[2];
1105
1106 if (ISSET(sc->sc_ucr3, IMX_UCR3_DSR))
1107 SET(ttybits, TIOCM_DTR);
1108 if (ISSET(sc->sc_ucr2, IMX_UCR2_CTS))
1109 SET(ttybits, TIOCM_RTS);
1110
1111 bus_space_read_region_4(iot, ioh, IMX_USR1, usr, 2);
1112
1113 if (ISSET(usr[0], IMX_USR1_RTSS))
1114 SET(ttybits, TIOCM_CTS);
1115
1116 if (ISSET(usr[1], IMX_USR2_DCDIN))
1117 SET(ttybits, TIOCM_CD);
1118
1119 #if 0
1120 /* XXXbsh: I couldn't find the way to read ipp_uart_dsr_dte_i signal,
1121 although there are bits in UART registers to detect delta of DSR.
1122 */
1123 if (ISSET(imxubits, MSR_DSR))
1124 SET(ttybits, TIOCM_DSR);
1125 #endif
1126
1127 if (ISSET(usr[1], IMX_USR2_RIIN))
1128 SET(ttybits, TIOCM_RI);
1129
1130
1131 #ifdef notyet
1132 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC))
1133 SET(ttybits, TIOCM_LE);
1134 #endif
1135
1136 return (ttybits);
1137 }
1138
1139 static uint32_t
cflag_to_ucr2(tcflag_t cflag,uint32_t oldval)1140 cflag_to_ucr2(tcflag_t cflag, uint32_t oldval)
1141 {
1142 uint32_t val = oldval;
1143
1144 CLR(val,IMX_UCR2_WS|IMX_UCR2_PREN|IMX_UCR2_PROE|IMX_UCR2_STPB);
1145
1146 switch (cflag & CSIZE) {
1147 case CS5:
1148 case CS6:
1149 /* not suppreted. use 7-bits */
1150 case CS7:
1151 break;
1152 case CS8:
1153 SET(val, IMX_UCR2_WS);
1154 break;
1155 }
1156
1157
1158 if (ISSET(cflag, PARENB)) {
1159 SET(val, IMX_UCR2_PREN);
1160
1161 /* odd parity */
1162 if (!ISSET(cflag, PARODD))
1163 SET(val, IMX_UCR2_PROE);
1164 }
1165
1166 if (ISSET(cflag, CSTOPB))
1167 SET(val, IMX_UCR2_STPB);
1168
1169 val |= IMX_UCR2_TXEN| IMX_UCR2_RXEN|IMX_UCR2_SRST;
1170
1171 return val;
1172 }
1173
1174 int
imxuparam(struct tty * tp,struct termios * t)1175 imxuparam(struct tty *tp, struct termios *t)
1176 {
1177 struct imxuart_softc *sc =
1178 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev));
1179 struct imxuart_baudrate_ratio ratio;
1180 uint32_t ucr2;
1181 bool change_speed = tp->t_ospeed != t->c_ospeed;
1182
1183 if (IMXUART_ISALIVE(sc) == 0)
1184 return (EIO);
1185
1186 /* Check requested parameters. */
1187 if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
1188 return (EINVAL);
1189
1190 /*
1191 * For the console, always force CLOCAL and !HUPCL, so that the port
1192 * is always active.
1193 */
1194 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
1195 ISSET(sc->sc_hwflags, IMXUART_HW_CONSOLE)) {
1196 SET(t->c_cflag, CLOCAL);
1197 CLR(t->c_cflag, HUPCL);
1198 }
1199
1200 /*
1201 * If there were no changes, don't do anything. This avoids dropping
1202 * input and improves performance when all we did was frob things like
1203 * VMIN and VTIME.
1204 */
1205 if ( !change_speed && tp->t_cflag == t->c_cflag)
1206 return (0);
1207
1208 if (change_speed) {
1209 /* calculate baudrate modulator value */
1210 if (imxuspeed(t->c_ospeed, &ratio) < 0)
1211 return (EINVAL);
1212 sc->sc_ratio = ratio;
1213 }
1214
1215 ucr2 = cflag_to_ucr2(t->c_cflag, sc->sc_ucr2_d);
1216
1217 mutex_spin_enter(&sc->sc_lock);
1218
1219 #if 0 /* flow control stuff. not yet */
1220 /*
1221 * If we're not in a mode that assumes a connection is present, then
1222 * ignore carrier changes.
1223 */
1224 if (ISSET(t->c_cflag, CLOCAL | MDMBUF))
1225 sc->sc_msr_dcd = 0;
1226 else
1227 sc->sc_msr_dcd = MSR_DCD;
1228 /*
1229 * Set the flow control pins depending on the current flow control
1230 * mode.
1231 */
1232 if (ISSET(t->c_cflag, CRTSCTS)) {
1233 sc->sc_mcr_dtr = MCR_DTR;
1234 sc->sc_mcr_rts = MCR_RTS;
1235 sc->sc_msr_cts = MSR_CTS;
1236 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS;
1237 } else if (ISSET(t->c_cflag, MDMBUF)) {
1238 /*
1239 * For DTR/DCD flow control, make sure we don't toggle DTR for
1240 * carrier detection.
1241 */
1242 sc->sc_mcr_dtr = 0;
1243 sc->sc_mcr_rts = MCR_DTR;
1244 sc->sc_msr_cts = MSR_DCD;
1245 sc->sc_efr = 0;
1246 } else {
1247 /*
1248 * If no flow control, then always set RTS. This will make
1249 * the other side happy if it mistakenly thinks we're doing
1250 * RTS/CTS flow control.
1251 */
1252 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
1253 sc->sc_mcr_rts = 0;
1254 sc->sc_msr_cts = 0;
1255 sc->sc_efr = 0;
1256 if (ISSET(sc->sc_mcr, MCR_DTR))
1257 SET(sc->sc_mcr, MCR_RTS);
1258 else
1259 CLR(sc->sc_mcr, MCR_RTS);
1260 }
1261 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd;
1262 #endif
1263
1264 /* And copy to tty. */
1265 tp->t_ispeed = t->c_ospeed;
1266 tp->t_ospeed = t->c_ospeed;
1267 tp->t_cflag = t->c_cflag;
1268
1269 if (!change_speed && ucr2 == sc->sc_ucr2_d) {
1270 /* noop */
1271 }
1272 else if (!sc->sc_pending && !sc->sc_tx_busy) {
1273 if (ucr2 != sc->sc_ucr2_d) {
1274 sc->sc_ucr2_d = ucr2;
1275 imxuart_load_params(sc);
1276 }
1277 if (change_speed)
1278 imxuart_load_speed(sc);
1279 }
1280 else {
1281 if (!sc->sc_pending) {
1282 sc->sc_heldtbc = sc->sc_tbc;
1283 sc->sc_tbc = 0;
1284 }
1285 sc->sc_pending |=
1286 (ucr2 == sc->sc_ucr2_d ? 0 : IMXUART_PEND_PARAM) |
1287 (change_speed ? 0 : IMXUART_PEND_SPEED);
1288 sc->sc_ucr2_d = ucr2;
1289 }
1290
1291 if (!ISSET(t->c_cflag, CHWFLOW)) {
1292 /* Disable the high water mark. */
1293 sc->sc_r_hiwat = 0;
1294 sc->sc_r_lowat = 0;
1295 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) {
1296 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED);
1297 imxuart_schedrx(sc);
1298 }
1299 if (ISSET(sc->sc_rx_flags,
1300 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED)) {
1301 CLR(sc->sc_rx_flags,
1302 IMXUART_RX_TTY_BLOCKED|IMXUART_RX_IBUF_BLOCKED);
1303 imxuart_hwiflow(sc);
1304 }
1305 } else {
1306 sc->sc_r_hiwat = imxuart_rbuf_hiwat;
1307 sc->sc_r_lowat = imxuart_rbuf_lowat;
1308 }
1309
1310 mutex_spin_exit(&sc->sc_lock);
1311
1312 #if 0
1313 /*
1314 * Update the tty layer's idea of the carrier bit, in case we changed
1315 * CLOCAL or MDMBUF. We don't hang up here; we only do that by
1316 * explicit request.
1317 */
1318 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD));
1319 #else
1320 /* XXX: always report that we have DCD */
1321 (void) (*tp->t_linesw->l_modem)(tp, 1);
1322 #endif
1323
1324 #ifdef IMXUART_DEBUG
1325 if (imxuart_debug)
1326 imxustatus(sc, "imxuparam ");
1327 #endif
1328
1329 if (!ISSET(t->c_cflag, CHWFLOW)) {
1330 if (sc->sc_tx_stopped) {
1331 sc->sc_tx_stopped = 0;
1332 imxustart(tp);
1333 }
1334 }
1335
1336 return (0);
1337 }
1338
1339 void
imxuart_iflush(struct imxuart_softc * sc)1340 imxuart_iflush(struct imxuart_softc *sc)
1341 {
1342 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1343 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1344 #ifdef DIAGNOSTIC
1345 uint32_t reg = 0xffff;
1346 #endif
1347 int timo;
1348
1349 timo = 50000;
1350 /* flush any pending I/O */
1351 while (ISSET(bus_space_read_4(iot, ioh, IMX_USR2), IMX_USR2_RDR)
1352 && --timo)
1353 #ifdef DIAGNOSTIC
1354 reg =
1355 #else
1356 (void)
1357 #endif
1358 bus_space_read_4(iot, ioh, IMX_URXD);
1359 #ifdef DIAGNOSTIC
1360 if (!timo)
1361 aprint_error_dev(sc->sc_dev, "imxuart_iflush timeout %02x\n", reg);
1362 #endif
1363 }
1364
1365 int
imxuhwiflow(struct tty * tp,int block)1366 imxuhwiflow(struct tty *tp, int block)
1367 {
1368 struct imxuart_softc *sc =
1369 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev));
1370
1371 if (IMXUART_ISALIVE(sc) == 0)
1372 return (0);
1373
1374 #ifdef notyet
1375 if (sc->sc_mcr_rts == 0)
1376 return (0);
1377 #endif
1378
1379 mutex_spin_enter(&sc->sc_lock);
1380
1381 if (block) {
1382 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) {
1383 SET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED);
1384 imxuart_hwiflow(sc);
1385 }
1386 } else {
1387 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED)) {
1388 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED);
1389 imxuart_schedrx(sc);
1390 }
1391 if (ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) {
1392 CLR(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED);
1393 imxuart_hwiflow(sc);
1394 }
1395 }
1396
1397 mutex_spin_exit(&sc->sc_lock);
1398 return (1);
1399 }
1400
1401 /*
1402 * (un)block input via hw flowcontrol
1403 */
1404 void
imxuart_hwiflow(struct imxuart_softc * sc)1405 imxuart_hwiflow(struct imxuart_softc *sc)
1406 {
1407 #ifdef notyet
1408 struct imxuart_regs *regsp= &sc->sc_regs;
1409
1410 if (sc->sc_mcr_rts == 0)
1411 return;
1412
1413 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) {
1414 CLR(sc->sc_mcr, sc->sc_mcr_rts);
1415 CLR(sc->sc_mcr_active, sc->sc_mcr_rts);
1416 } else {
1417 SET(sc->sc_mcr, sc->sc_mcr_rts);
1418 SET(sc->sc_mcr_active, sc->sc_mcr_rts);
1419 }
1420 UR_WRITE_1(regsp, IMXUART_REG_MCR, sc->sc_mcr_active);
1421 #endif
1422 }
1423
1424
1425 void
imxustart(struct tty * tp)1426 imxustart(struct tty *tp)
1427 {
1428 struct imxuart_softc *sc =
1429 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev));
1430 int s;
1431 u_char *tba;
1432 int tbc;
1433 u_int n;
1434 u_int space;
1435 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1436 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1437
1438 if (IMXUART_ISALIVE(sc) == 0)
1439 return;
1440
1441 s = spltty();
1442 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
1443 goto out;
1444 if (sc->sc_tx_stopped)
1445 goto out;
1446 if (!ttypull(tp))
1447 goto out;
1448
1449 /* Grab the first contiguous region of buffer space. */
1450 tba = tp->t_outq.c_cf;
1451 tbc = ndqb(&tp->t_outq, 0);
1452
1453 mutex_spin_enter(&sc->sc_lock);
1454
1455 sc->sc_tba = tba;
1456 sc->sc_tbc = tbc;
1457
1458 SET(tp->t_state, TS_BUSY);
1459 sc->sc_tx_busy = 1;
1460
1461 space = imxuart_txfifo_space(sc);
1462 n = MIN(sc->sc_tbc, space);
1463
1464 if (n > 0) {
1465 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, n);
1466 sc->sc_tbc -= n;
1467 sc->sc_tba += n;
1468 }
1469
1470 /* Enable transmit completion interrupts */
1471 imxuart_control_txint(sc, true);
1472
1473 mutex_spin_exit(&sc->sc_lock);
1474 out:
1475 splx(s);
1476 return;
1477 }
1478
1479 /*
1480 * Stop output on a line.
1481 */
1482 void
imxustop(struct tty * tp,int flag)1483 imxustop(struct tty *tp, int flag)
1484 {
1485 struct imxuart_softc *sc =
1486 device_lookup_private(&imxuart_cd, IMXUART_UNIT(tp->t_dev));
1487
1488 mutex_spin_enter(&sc->sc_lock);
1489 if (ISSET(tp->t_state, TS_BUSY)) {
1490 /* Stop transmitting at the next chunk. */
1491 sc->sc_tbc = 0;
1492 sc->sc_heldtbc = 0;
1493 if (!ISSET(tp->t_state, TS_TTSTOP))
1494 SET(tp->t_state, TS_FLUSH);
1495 }
1496 mutex_spin_exit(&sc->sc_lock);
1497 }
1498
1499 void
imxudiag(void * arg)1500 imxudiag(void *arg)
1501 {
1502 #ifdef notyet
1503 struct imxuart_softc *sc = arg;
1504 int overflows, floods;
1505
1506 mutex_spin_enter(&sc->sc_lock);
1507 overflows = sc->sc_overflows;
1508 sc->sc_overflows = 0;
1509 floods = sc->sc_floods;
1510 sc->sc_floods = 0;
1511 sc->sc_errors = 0;
1512 mutex_spin_exit(&sc->sc_lock);
1513
1514 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
1515 device_xname(sc->sc_dev),
1516 overflows, overflows == 1 ? "" : "s",
1517 floods, floods == 1 ? "" : "s");
1518 #endif
1519 }
1520
1521 integrate void
imxuart_rxsoft(struct imxuart_softc * sc,struct tty * tp)1522 imxuart_rxsoft(struct imxuart_softc *sc, struct tty *tp)
1523 {
1524 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint;
1525 u_int cc, scc, outp;
1526 uint16_t data;
1527 u_int code;
1528
1529 scc = cc = IMXUART_RBUF_AVAIL(sc);
1530
1531 #if 0
1532 if (cc == imxuart_rbuf_size-1) {
1533 sc->sc_floods++;
1534 if (sc->sc_errors++ == 0)
1535 callout_reset(&sc->sc_diag_callout, 60 * hz,
1536 imxudiag, sc);
1537 }
1538 #endif
1539
1540 /* If not yet open, drop the entire buffer content here */
1541 if (!ISSET(tp->t_state, TS_ISOPEN)) {
1542 sc->sc_rbuf_out = sc->sc_rbuf_in;
1543 cc = 0;
1544 }
1545
1546 outp = sc->sc_rbuf_out;
1547
1548 #define ERRBITS (IMX_URXD_PRERR|IMX_URXD_BRK|IMX_URXD_FRMERR|IMX_URXD_OVRRUN)
1549
1550 while (cc) {
1551 data = sc->sc_rbuf[outp];
1552 code = data & IMX_URXD_RX_DATA;
1553 if (ISSET(data, ERRBITS)) {
1554 if (sc->sc_errors.err == 0)
1555 callout_reset(&sc->sc_diag_callout,
1556 60 * hz, imxudiag, sc);
1557 if (ISSET(data, IMX_URXD_OVRRUN))
1558 sc->sc_errors.ovrrun++;
1559 if (ISSET(data, IMX_URXD_BRK)) {
1560 sc->sc_errors.brk++;
1561 SET(code, TTY_FE);
1562 }
1563 if (ISSET(data, IMX_URXD_FRMERR)) {
1564 sc->sc_errors.frmerr++;
1565 SET(code, TTY_FE);
1566 }
1567 if (ISSET(data, IMX_URXD_PRERR)) {
1568 sc->sc_errors.prerr++;
1569 SET(code, TTY_PE);
1570 }
1571 }
1572 if ((*rint)(code, tp) == -1) {
1573 /*
1574 * The line discipline's buffer is out of space.
1575 */
1576 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_BLOCKED)) {
1577 /*
1578 * We're either not using flow control, or the
1579 * line discipline didn't tell us to block for
1580 * some reason. Either way, we have no way to
1581 * know when there's more space available, so
1582 * just drop the rest of the data.
1583 */
1584 sc->sc_rbuf_out = sc->sc_rbuf_in;
1585 cc = 0;
1586 } else {
1587 /*
1588 * Don't schedule any more receive processing
1589 * until the line discipline tells us there's
1590 * space available (through imxuhwiflow()).
1591 * Leave the rest of the data in the input
1592 * buffer.
1593 */
1594 SET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED);
1595 }
1596 break;
1597 }
1598 outp = IMXUART_RBUF_INC(sc, outp, 1);
1599 cc--;
1600 }
1601
1602 if (cc != scc) {
1603 sc->sc_rbuf_out = outp;
1604 mutex_spin_enter(&sc->sc_lock);
1605
1606 cc = IMXUART_RBUF_SPACE(sc);
1607
1608 /* Buffers should be ok again, release possible block. */
1609 if (cc >= sc->sc_r_lowat) {
1610 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED)) {
1611 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_OVERFLOWED);
1612 imxuart_control_rxint(sc, true);
1613 }
1614 if (ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED)) {
1615 CLR(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED);
1616 imxuart_hwiflow(sc);
1617 }
1618 }
1619 mutex_spin_exit(&sc->sc_lock);
1620 }
1621 }
1622
1623 integrate void
imxuart_txsoft(struct imxuart_softc * sc,struct tty * tp)1624 imxuart_txsoft(struct imxuart_softc *sc, struct tty *tp)
1625 {
1626
1627 CLR(tp->t_state, TS_BUSY);
1628 if (ISSET(tp->t_state, TS_FLUSH))
1629 CLR(tp->t_state, TS_FLUSH);
1630 else
1631 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
1632 (*tp->t_linesw->l_start)(tp);
1633 }
1634
1635 integrate void
imxuart_stsoft(struct imxuart_softc * sc,struct tty * tp)1636 imxuart_stsoft(struct imxuart_softc *sc, struct tty *tp)
1637 {
1638 #ifdef notyet
1639 u_char msr, delta;
1640
1641 mutex_spin_enter(&sc->sc_lock);
1642 msr = sc->sc_msr;
1643 delta = sc->sc_msr_delta;
1644 sc->sc_msr_delta = 0;
1645 mutex_spin_exit(&sc->sc_lock);
1646
1647 if (ISSET(delta, sc->sc_msr_dcd)) {
1648 /*
1649 * Inform the tty layer that carrier detect changed.
1650 */
1651 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD));
1652 }
1653
1654 if (ISSET(delta, sc->sc_msr_cts)) {
1655 /* Block or unblock output according to flow control. */
1656 if (ISSET(msr, sc->sc_msr_cts)) {
1657 sc->sc_tx_stopped = 0;
1658 (*tp->t_linesw->l_start)(tp);
1659 } else {
1660 sc->sc_tx_stopped = 1;
1661 }
1662 }
1663
1664 #endif
1665 #ifdef IMXUART_DEBUG
1666 if (imxuart_debug)
1667 imxustatus(sc, "imxuart_stsoft");
1668 #endif
1669 }
1670
1671 void
imxusoft(void * arg)1672 imxusoft(void *arg)
1673 {
1674 struct imxuart_softc *sc = arg;
1675 struct tty *tp;
1676
1677 if (IMXUART_ISALIVE(sc) == 0)
1678 return;
1679
1680 tp = sc->sc_tty;
1681
1682 if (sc->sc_rx_ready) {
1683 sc->sc_rx_ready = 0;
1684 imxuart_rxsoft(sc, tp);
1685 }
1686
1687 if (sc->sc_st_check) {
1688 sc->sc_st_check = 0;
1689 imxuart_stsoft(sc, tp);
1690 }
1691
1692 if (sc->sc_tx_done) {
1693 sc->sc_tx_done = 0;
1694 imxuart_txsoft(sc, tp);
1695 }
1696 }
1697
1698 int
imxuintr(void * arg)1699 imxuintr(void *arg)
1700 {
1701 struct imxuart_softc *sc = arg;
1702 uint32_t usr1, usr2;
1703 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1704 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1705
1706
1707 if (IMXUART_ISALIVE(sc) == 0)
1708 return (0);
1709
1710 mutex_spin_enter(&sc->sc_lock);
1711
1712 usr2 = bus_space_read_4(iot, ioh, IMX_USR2);
1713
1714
1715 do {
1716 bus_space_write_4(iot, ioh, IMX_USR2,
1717 usr2 & (IMX_USR2_BRCD|IMX_USR2_ORE));
1718 if (usr2 & IMX_USR2_BRCD) {
1719 /* Break signal detected */
1720 int cn_trapped = 0;
1721
1722 cn_check_magic(sc->sc_tty->t_dev,
1723 CNC_BREAK, imxuart_cnm_state);
1724 if (cn_trapped)
1725 goto next;
1726 #if defined(KGDB) && !defined(DDB)
1727 if (ISSET(sc->sc_hwflags, IMXUART_HW_KGDB)) {
1728 kgdb_connect(1);
1729 goto next;
1730 }
1731 #endif
1732 }
1733
1734 if (usr2 & IMX_USR2_RDR)
1735 imxuintr_read(sc);
1736
1737 #ifdef IMXUART_PPS
1738 {
1739 u_char msr, delta;
1740
1741 msr = CSR_READ_1(regsp, IMXUART_REG_MSR);
1742 delta = msr ^ sc->sc_msr;
1743 sc->sc_msr = msr;
1744 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) &&
1745 (delta & MSR_DCD)) {
1746 mutex_spin_enter(&timecounter_lock);
1747 pps_capture(&sc->sc_pps_state);
1748 pps_event(&sc->sc_pps_state,
1749 (msr & MSR_DCD) ?
1750 PPS_CAPTUREASSERT :
1751 PPS_CAPTURECLEAR);
1752 mutex_spin_exit(&timecounter_lock);
1753 }
1754 }
1755 #endif
1756
1757 #ifdef notyet
1758 /*
1759 * Process normal status changes
1760 */
1761 if (ISSET(delta, sc->sc_msr_mask)) {
1762 SET(sc->sc_msr_delta, delta);
1763
1764 /*
1765 * Stop output immediately if we lose the output
1766 * flow control signal or carrier detect.
1767 */
1768 if (ISSET(~msr, sc->sc_msr_mask)) {
1769 sc->sc_tbc = 0;
1770 sc->sc_heldtbc = 0;
1771 #ifdef IMXUART_DEBUG
1772 if (imxuart_debug)
1773 imxustatus(sc, "imxuintr ");
1774 #endif
1775 }
1776
1777 sc->sc_st_check = 1;
1778 }
1779 #endif
1780
1781 next:
1782 usr2 = bus_space_read_4(iot, ioh, IMX_USR2);
1783 } while (usr2 & (IMX_USR2_RDR|IMX_USR2_BRCD));
1784
1785 usr1 = bus_space_read_4(iot, ioh, IMX_USR1);
1786 if (usr1 & IMX_USR1_TRDY)
1787 imxuintr_send(sc);
1788
1789 mutex_spin_exit(&sc->sc_lock);
1790
1791 /* Wake up the poller. */
1792 softint_schedule(sc->sc_si);
1793
1794 #ifdef RND_COM
1795 rnd_add_uint32(&sc->rnd_source, iir | lsr);
1796 #endif
1797
1798 return (1);
1799 }
1800
1801
1802 /*
1803 * called when there is least one character in rxfifo
1804 *
1805 */
1806
1807 static void
imxuintr_read(struct imxuart_softc * sc)1808 imxuintr_read(struct imxuart_softc *sc)
1809 {
1810 int cc;
1811 uint16_t rd;
1812 uint32_t usr2;
1813 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1814 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1815
1816 cc = IMXUART_RBUF_SPACE(sc);
1817
1818 /* clear aging timer interrupt */
1819 bus_space_write_4(iot, ioh, IMX_USR1, IMX_USR1_AGTIM);
1820
1821 while (cc > 0) {
1822 int cn_trapped = 0;
1823
1824 sc->sc_rbuf[sc->sc_rbuf_in] = rd =
1825 bus_space_read_4(iot, ioh, IMX_URXD);
1826
1827 cn_check_magic(sc->sc_tty->t_dev,
1828 rd & 0xff, imxuart_cnm_state);
1829
1830 if (!cn_trapped) {
1831 #if defined(DDB) && defined(DDB_KEYCODE)
1832 /*
1833 * Temporary hack so that I can force the kernel into
1834 * the debugger via the serial port
1835 */
1836 if ((rd & 0xff) == DDB_KEYCODE)
1837 Debugger();
1838 #endif
1839 sc->sc_rbuf_in = IMXUART_RBUF_INC(sc, sc->sc_rbuf_in, 1);
1840 cc--;
1841 }
1842
1843 usr2 = bus_space_read_4(iot, ioh, IMX_USR2);
1844 if (!(usr2 & IMX_USR2_RDR))
1845 break;
1846 }
1847
1848 /*
1849 * Current string of incoming characters ended because
1850 * no more data was available or we ran out of space.
1851 * Schedule a receive event if any data was received.
1852 * If we're out of space, turn off receive interrupts.
1853 */
1854 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_TTY_OVERFLOWED))
1855 sc->sc_rx_ready = 1;
1856 /*
1857 * See if we are in danger of overflowing a buffer. If
1858 * so, use hardware flow control to ease the pressure.
1859 */
1860 if (!ISSET(sc->sc_rx_flags, IMXUART_RX_IBUF_BLOCKED) &&
1861 cc < sc->sc_r_hiwat) {
1862 sc->sc_rx_flags |= IMXUART_RX_IBUF_BLOCKED;
1863 imxuart_hwiflow(sc);
1864 }
1865
1866 /*
1867 * If we're out of space, disable receive interrupts
1868 * until the queue has drained a bit.
1869 */
1870 if (!cc) {
1871 sc->sc_rx_flags |= IMXUART_RX_IBUF_OVERFLOWED;
1872 imxuart_control_rxint(sc, false);
1873 }
1874 }
1875
1876
1877
1878 /*
1879 * find how many chars we can put into tx-fifo
1880 */
1881 static u_int
imxuart_txfifo_space(struct imxuart_softc * sc)1882 imxuart_txfifo_space(struct imxuart_softc *sc)
1883 {
1884 uint32_t usr1, usr2;
1885 u_int cc;
1886 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1887 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1888
1889 usr2 = bus_space_read_4(iot, ioh, IMX_USR2);
1890 if (usr2 & IMX_USR2_TXFE)
1891 cc = sc->sc_txfifo_len;
1892 else {
1893 usr1 = bus_space_read_4(iot, ioh, IMX_USR1);
1894 if (usr1 & IMX_USR1_TRDY)
1895 cc = sc->sc_txfifo_thresh;
1896 else
1897 cc = 0;
1898 }
1899
1900 return cc;
1901 }
1902
1903 void
imxuintr_send(struct imxuart_softc * sc)1904 imxuintr_send(struct imxuart_softc *sc)
1905 {
1906 uint32_t usr2;
1907 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1908 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1909 int cc = 0;
1910
1911 usr2 = bus_space_read_4(iot, ioh, IMX_USR2);
1912
1913 if (sc->sc_pending) {
1914 if (usr2 & IMX_USR2_TXFE) {
1915 imxuart_load_pendings(sc);
1916 sc->sc_tbc = sc->sc_heldtbc;
1917 sc->sc_heldtbc = 0;
1918 }
1919 else {
1920 /* wait for TX fifo empty */
1921 imxuart_control_txint(sc, true);
1922 return;
1923 }
1924 }
1925
1926 cc = imxuart_txfifo_space(sc);
1927 cc = MIN(cc, sc->sc_tbc);
1928
1929 if (cc > 0) {
1930 bus_space_write_multi_1(iot, ioh, IMX_UTXD, sc->sc_tba, cc);
1931 sc->sc_tbc -= cc;
1932 sc->sc_tba += cc;
1933 }
1934
1935 if (sc->sc_tbc > 0)
1936 imxuart_control_txint(sc, true);
1937 else {
1938 /* no more chars to send.
1939 we don't need tx interrupt any more. */
1940 imxuart_control_txint(sc, false);
1941 if (sc->sc_tx_busy) {
1942 sc->sc_tx_busy = 0;
1943 sc->sc_tx_done = 1;
1944 }
1945 }
1946 }
1947
1948 static void
imxuart_disable_all_interrupts(struct imxuart_softc * sc)1949 imxuart_disable_all_interrupts(struct imxuart_softc *sc)
1950 {
1951 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1952 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1953
1954 sc->sc_ucr1 &= ~IMXUART_INTRS_UCR1;
1955 sc->sc_ucr2 &= ~IMXUART_INTRS_UCR2;
1956 sc->sc_ucr3 &= ~IMXUART_INTRS_UCR3;
1957 sc->sc_ucr4 &= ~IMXUART_INTRS_UCR4;
1958
1959
1960 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 4);
1961 }
1962
1963 static void
imxuart_control_rxint(struct imxuart_softc * sc,bool enable)1964 imxuart_control_rxint(struct imxuart_softc *sc, bool enable)
1965 {
1966 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1967 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1968 uint32_t ucr1, ucr2;
1969
1970 ucr1 = sc->sc_ucr1;
1971 ucr2 = sc->sc_ucr2;
1972
1973 if (enable) {
1974 ucr1 |= IMX_UCR1_RRDYEN;
1975 ucr2 |= IMX_UCR2_ATEN;
1976 }
1977 else {
1978 ucr1 &= ~IMX_UCR1_RRDYEN;
1979 ucr2 &= ~IMX_UCR2_ATEN;
1980 }
1981
1982 if (ucr1 != sc->sc_ucr1 || ucr2 != sc->sc_ucr2) {
1983 sc->sc_ucr1 = ucr1;
1984 sc->sc_ucr2 = ucr2;
1985 bus_space_write_region_4(iot, ioh, IMX_UCR1, sc->sc_ucr, 2);
1986 }
1987 }
1988
1989 static void
imxuart_control_txint(struct imxuart_softc * sc,bool enable)1990 imxuart_control_txint(struct imxuart_softc *sc, bool enable)
1991 {
1992 bus_space_tag_t iot = sc->sc_regs.ur_iot;
1993 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
1994 uint32_t ucr1;
1995 uint32_t mask;
1996
1997 /* if parameter change is pending, get interrupt when Tx fifo
1998 is completely empty. otherwise, get interrupt when txfifo
1999 has less characters than threshold */
2000 mask = sc->sc_pending ? IMX_UCR1_TXMPTYEN : IMX_UCR1_TRDYEN;
2001
2002 ucr1 = sc->sc_ucr1;
2003
2004 CLR(ucr1, IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN);
2005 if (enable)
2006 SET(ucr1, mask);
2007
2008 if (ucr1 != sc->sc_ucr1) {
2009 bus_space_write_4(iot, ioh, IMX_UCR1, ucr1);
2010 sc->sc_ucr1 = ucr1;
2011 }
2012 }
2013
2014
2015 static void
imxuart_load_params(struct imxuart_softc * sc)2016 imxuart_load_params(struct imxuart_softc *sc)
2017 {
2018 uint32_t ucr2;
2019 bus_space_tag_t iot = sc->sc_regs.ur_iot;
2020 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
2021
2022 ucr2 = (sc->sc_ucr2_d & ~IMX_UCR2_ATEN) |
2023 (sc->sc_ucr2 & IMX_UCR2_ATEN);
2024
2025 bus_space_write_4(iot, ioh, IMX_UCR2, ucr2);
2026 sc->sc_ucr2 = ucr2;
2027 }
2028
2029 static void
imxuart_load_speed(struct imxuart_softc * sc)2030 imxuart_load_speed(struct imxuart_softc *sc)
2031 {
2032 bus_space_tag_t iot = sc->sc_regs.ur_iot;
2033 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
2034 int n, rfdiv, ufcr;
2035
2036 #ifdef notyet
2037 /*
2038 * Set the FIFO threshold based on the receive speed.
2039 *
2040 * * If it's a low speed, it's probably a mouse or some other
2041 * interactive device, so set the threshold low.
2042 * * If it's a high speed, trim the trigger level down to prevent
2043 * overflows.
2044 * * Otherwise set it a bit higher.
2045 */
2046 if (t->c_ospeed <= 1200)
2047 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1;
2048 else if (t->c_ospeed <= 38400)
2049 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8;
2050 else
2051 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4;
2052 #endif
2053
2054 n = 32 - sc->sc_txfifo_thresh;
2055 n = MAX(2, n);
2056
2057 rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv);
2058
2059 ufcr = (n << IMX_UFCR_TXTL_SHIFT) |
2060 (rfdiv << IMX_UFCR_RFDIV_SHIFT) |
2061 (16 << IMX_UFCR_RXTL_SHIFT);
2062
2063 /* keep DCE/DTE bit */
2064 ufcr |= bus_space_read_4(iot, ioh, IMX_UFCR) & IMX_UFCR_DCEDTE;
2065
2066 bus_space_write_4(iot, ioh, IMX_UFCR, ufcr);
2067
2068 /* UBIR must updated before UBMR */
2069 bus_space_write_4(iot, ioh,
2070 IMX_UBIR, sc->sc_ratio.numerator);
2071 bus_space_write_4(iot, ioh,
2072 IMX_UBMR, sc->sc_ratio.modulator);
2073
2074
2075 }
2076
2077
2078 static void
imxuart_load_pendings(struct imxuart_softc * sc)2079 imxuart_load_pendings(struct imxuart_softc *sc)
2080 {
2081 if (sc->sc_pending & IMXUART_PEND_PARAM)
2082 imxuart_load_params(sc);
2083 if (sc->sc_pending & IMXUART_PEND_SPEED)
2084 imxuart_load_speed(sc);
2085 sc->sc_pending = 0;
2086 }
2087
2088 /*
2089 * The following functions are polled getc and putc routines, shared
2090 * by the console and kgdb glue.
2091 *
2092 * The read-ahead code is so that you can detect pending in-band
2093 * cn_magic in polled mode while doing output rather than having to
2094 * wait until the kernel decides it needs input.
2095 */
2096
2097 #define READAHEAD_RING_LEN 16
2098 static int imxuart_readahead[READAHEAD_RING_LEN];
2099 static int imxuart_readahead_in = 0;
2100 static int imxuart_readahead_out = 0;
2101 #define READAHEAD_IS_EMPTY() (imxuart_readahead_in==imxuart_readahead_out)
2102 #define READAHEAD_IS_FULL() \
2103 (((imxuart_readahead_in+1) & (READAHEAD_RING_LEN-1)) ==imxuart_readahead_out)
2104
2105 int
imxuart_common_getc(dev_t dev,struct imxuart_regs * regsp)2106 imxuart_common_getc(dev_t dev, struct imxuart_regs *regsp)
2107 {
2108 int s = splserial();
2109 u_char c;
2110 bus_space_tag_t iot = regsp->ur_iot;
2111 bus_space_handle_t ioh = regsp->ur_ioh;
2112 uint32_t usr2;
2113
2114 /* got a character from reading things earlier */
2115 if (!READAHEAD_IS_EMPTY()) {
2116 c = imxuart_readahead[imxuart_readahead_out];
2117 imxuart_readahead_out = (imxuart_readahead_out + 1) &
2118 (READAHEAD_RING_LEN-1);
2119 splx(s);
2120 return (c);
2121 }
2122
2123 /* block until a character becomes available */
2124 while (!((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR))
2125 continue;
2126
2127 c = 0xff & bus_space_read_4(iot, ioh, IMX_URXD);
2128
2129 {
2130 int cn_trapped __unused = 0;
2131 if (!db_active)
2132 cn_check_magic(dev, c, imxuart_cnm_state);
2133 }
2134 splx(s);
2135 return (c);
2136 }
2137
2138 void
imxuart_common_putc(dev_t dev,struct imxuart_regs * regsp,int c)2139 imxuart_common_putc(dev_t dev, struct imxuart_regs *regsp, int c)
2140 {
2141 int s = splserial();
2142 int cin, timo;
2143 bus_space_tag_t iot = regsp->ur_iot;
2144 bus_space_handle_t ioh = regsp->ur_ioh;
2145 uint32_t usr2;
2146
2147 if (!READAHEAD_IS_FULL() &&
2148 ((usr2 = bus_space_read_4(iot, ioh, IMX_USR2)) & IMX_USR2_RDR)) {
2149
2150 int __attribute__((__unused__))cn_trapped = 0;
2151 cin = bus_space_read_4(iot, ioh, IMX_URXD);
2152 cn_check_magic(dev, cin & 0xff, imxuart_cnm_state);
2153 imxuart_readahead[imxuart_readahead_in] = cin & 0xff;
2154 imxuart_readahead_in = (imxuart_readahead_in + 1) &
2155 (READAHEAD_RING_LEN-1);
2156 }
2157
2158 /* wait for any pending transmission to finish */
2159 timo = 150000;
2160 do {
2161 if (bus_space_read_4(iot, ioh, IMX_USR1) & IMX_USR1_TRDY) {
2162 bus_space_write_4(iot, ioh, IMX_UTXD, c);
2163 break;
2164 }
2165 } while(--timo > 0);
2166
2167 IMXUART_BARRIER(regsp, BR | BW);
2168
2169 splx(s);
2170 }
2171
2172 /*
2173 * Initialize UART
2174 */
2175 int
imxuart_init(struct imxuart_regs * regsp,int rate,tcflag_t cflag,int domap)2176 imxuart_init(struct imxuart_regs *regsp, int rate, tcflag_t cflag, int domap)
2177 {
2178 struct imxuart_baudrate_ratio ratio;
2179 int rfdiv = IMX_UFCR_DIVIDER_TO_RFDIV(imxuart_freqdiv);
2180 uint32_t ufcr;
2181 int error;
2182
2183 if (domap && (error = bus_space_map(regsp->ur_iot, regsp->ur_iobase,
2184 IMX_UART_SIZE, 0, ®sp->ur_ioh)) != 0)
2185 return error;
2186
2187 if (imxuart_freq != 0) {
2188 if (imxuspeed(rate, &ratio) < 0)
2189 return EINVAL;
2190
2191 /* UBIR must updated before UBMR */
2192 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh,
2193 IMX_UBIR, ratio.numerator);
2194 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh,
2195 IMX_UBMR, ratio.modulator);
2196 }
2197
2198 /* XXX: DTREN, DPEC */
2199 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR3,
2200 IMX_UCR3_DSR|IMX_UCR3_RXDMUXSEL);
2201
2202 ufcr = bus_space_read_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR);
2203 ufcr &= ~IMX_UFCR_TXTL;
2204 ufcr |= (8 << IMX_UFCR_TXTL_SHIFT);
2205 ufcr &= ~IMX_UFCR_RXTL;
2206 ufcr |= (1 << IMX_UFCR_RXTL_SHIFT);
2207 if (imxuart_freq != 0) {
2208 ufcr &= ~IMX_UFCR_RFDIV;
2209 ufcr |= (rfdiv << IMX_UFCR_RFDIV_SHIFT);
2210 }
2211 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UFCR, ufcr);
2212
2213 if (imxuart_freq != 0) {
2214 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_ONEMS,
2215 imxuart_freq / imxuart_freqdiv / 1000);
2216 }
2217
2218 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR2,
2219 IMX_UCR2_IRTS|
2220 IMX_UCR2_CTSC|
2221 IMX_UCR2_WS|IMX_UCR2_TXEN|
2222 IMX_UCR2_RXEN|IMX_UCR2_SRST);
2223 /* clear status registers */
2224 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR1, 0xffff);
2225 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_USR2, 0xffff);
2226
2227
2228 bus_space_write_4(regsp->ur_iot, regsp->ur_ioh, IMX_UCR1,
2229 IMX_UCR1_UARTEN);
2230
2231 return (0);
2232 }
2233
2234
2235 /*
2236 * Following are all routines needed for UART to act as console
2237 */
2238 struct consdev imxucons = {
2239 NULL, NULL, imxucngetc, imxucnputc, imxucnpollc, NULL, NULL, NULL,
2240 NODEV, CN_NORMAL
2241 };
2242
2243
2244 int
imxuart_cnattach(bus_space_tag_t iot,paddr_t iobase,u_int rate,tcflag_t cflag)2245 imxuart_cnattach(bus_space_tag_t iot, paddr_t iobase, u_int rate,
2246 tcflag_t cflag)
2247 {
2248 struct imxuart_regs regs;
2249 int res;
2250
2251 regs.ur_iot = iot;
2252 regs.ur_iobase = iobase;
2253
2254 res = imxuart_init(®s, rate, cflag, true);
2255 if (res)
2256 return (res);
2257
2258 cn_tab = &imxucons;
2259 cn_init_magic(&imxuart_cnm_state);
2260 cn_set_magic("\047\001"); /* default magic is BREAK */
2261
2262 imxuconsrate = rate;
2263 imxuconscflag = cflag;
2264
2265 imxuconsregs = regs;
2266
2267 return 0;
2268 }
2269
2270 int
imxucngetc(dev_t dev)2271 imxucngetc(dev_t dev)
2272 {
2273 return (imxuart_common_getc(dev, &imxuconsregs));
2274 }
2275
2276 /*
2277 * Console kernel output character routine.
2278 */
2279 void
imxucnputc(dev_t dev,int c)2280 imxucnputc(dev_t dev, int c)
2281 {
2282 imxuart_common_putc(dev, &imxuconsregs, c);
2283 }
2284
2285 void
imxucnpollc(dev_t dev,int on)2286 imxucnpollc(dev_t dev, int on)
2287 {
2288
2289 imxuart_readahead_in = 0;
2290 imxuart_readahead_out = 0;
2291 }
2292
2293 #ifdef KGDB
2294 int
imxuart_kgdb_attach(bus_space_tag_t iot,paddr_t iobase,u_int rate,tcflag_t cflag)2295 imxuart_kgdb_attach(bus_space_tag_t iot, paddr_t iobase, u_int rate,
2296 tcflag_t cflag)
2297 {
2298 int res;
2299
2300 if (iot == imxuconsregs.ur_iot &&
2301 iobase == imxuconsregs.ur_iobase) {
2302 #if !defined(DDB)
2303 return (EBUSY); /* cannot share with console */
2304 #else
2305 imxu_kgdb_regs.ur_iot = iot;
2306 imxu_kgdb_regs.ur_ioh = imxuconsregs.ur_ioh;
2307 imxu_kgdb_regs.ur_iobase = iobase;
2308 #endif
2309 } else {
2310 imxu_kgdb_regs.ur_iot = iot;
2311 imxu_kgdb_regs.ur_iobase = iobase;
2312
2313 res = imxuart_init(&imxu_kgdb_regs, rate, cflag, true);
2314 if (res)
2315 return (res);
2316
2317 /*
2318 * XXXfvdl this shouldn't be needed, but the cn_magic goo
2319 * expects this to be initialized
2320 */
2321 cn_init_magic(&imxuart_cnm_state);
2322 cn_set_magic("\047\001");
2323 }
2324
2325 kgdb_attach(imxuart_kgdb_getc, imxuart_kgdb_putc, &imxu_kgdb_regs);
2326 kgdb_dev = 123; /* unneeded, only to satisfy some tests */
2327
2328 return (0);
2329 }
2330
2331 /* ARGSUSED */
2332 int
imxuart_kgdb_getc(void * arg)2333 imxuart_kgdb_getc(void *arg)
2334 {
2335 struct imxuart_regs *regs = arg;
2336
2337 return (imxuart_common_getc(NODEV, regs));
2338 }
2339
2340 /* ARGSUSED */
2341 void
imxuart_kgdb_putc(void * arg,int c)2342 imxuart_kgdb_putc(void *arg, int c)
2343 {
2344 struct imxuart_regs *regs = arg;
2345
2346 imxuart_common_putc(NODEV, regs, c);
2347 }
2348 #endif /* KGDB */
2349
2350 /* helper function to identify the imxu ports used by
2351 console or KGDB (and not yet autoconf attached) */
2352 int
imxuart_is_console(bus_space_tag_t iot,bus_addr_t iobase,bus_space_handle_t * ioh)2353 imxuart_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh)
2354 {
2355 bus_space_handle_t help;
2356
2357 if (!imxuconsattached &&
2358 iot == imxuconsregs.ur_iot && iobase == imxuconsregs.ur_iobase)
2359 help = imxuconsregs.ur_ioh;
2360 #ifdef KGDB
2361 else if (!imxu_kgdb_attached &&
2362 iot == imxu_kgdb_regs.ur_iot && iobase == imxu_kgdb_regs.ur_iobase)
2363 help = imxu_kgdb_regs.ur_ioh;
2364 #endif
2365 else
2366 return (0);
2367
2368 if (ioh)
2369 *ioh = help;
2370 return (1);
2371 }
2372
2373 #ifdef notyet
2374
2375 bool
imxuart_cleanup(device_t self,int how)2376 imxuart_cleanup(device_t self, int how)
2377 {
2378 /*
2379 * this routine exists to serve as a shutdown hook for systems that
2380 * have firmware which doesn't interact properly with a imxuart device in
2381 * FIFO mode.
2382 */
2383 struct imxuart_softc *sc = device_private(self);
2384
2385 if (ISSET(sc->sc_hwflags, IMXUART_HW_FIFO))
2386 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_FIFO, 0);
2387
2388 return true;
2389 }
2390 #endif
2391
2392 #ifdef notyet
2393 bool
imxuart_suspend(device_t self PMF_FN_ARGS)2394 imxuart_suspend(device_t self PMF_FN_ARGS)
2395 {
2396 struct imxuart_softc *sc = device_private(self);
2397
2398 UR_WRITE_1(&sc->sc_regs, IMXUART_REG_IER, 0);
2399 (void)CSR_READ_1(&sc->sc_regs, IMXUART_REG_IIR);
2400
2401 return true;
2402 }
2403 #endif
2404
2405 #ifdef notyet
2406 bool
imxuart_resume(device_t self PMF_FN_ARGS)2407 imxuart_resume(device_t self PMF_FN_ARGS)
2408 {
2409 struct imxuart_softc *sc = device_private(self);
2410
2411 mutex_spin_enter(&sc->sc_lock);
2412 imxuart_loadchannelregs(sc);
2413 mutex_spin_exit(&sc->sc_lock);
2414
2415 return true;
2416 }
2417 #endif
2418
2419 static void
imxuart_enable_debugport(struct imxuart_softc * sc)2420 imxuart_enable_debugport(struct imxuart_softc *sc)
2421 {
2422 bus_space_tag_t iot = sc->sc_regs.ur_iot;
2423 bus_space_handle_t ioh = sc->sc_regs.ur_ioh;
2424
2425 if (sc->sc_hwflags & (IMXUART_HW_CONSOLE|IMXUART_HW_KGDB)) {
2426
2427 /* Turn on line break interrupt, set carrier. */
2428
2429 sc->sc_ucr3 |= IMX_UCR3_DSR;
2430 bus_space_write_4(iot, ioh, IMX_UCR3, sc->sc_ucr3);
2431
2432 sc->sc_ucr4 |= IMX_UCR4_BKEN;
2433 bus_space_write_4(iot, ioh, IMX_UCR4, sc->sc_ucr4);
2434
2435 sc->sc_ucr2 |= IMX_UCR2_TXEN|IMX_UCR2_RXEN|
2436 IMX_UCR2_CTS;
2437 bus_space_write_4(iot, ioh, IMX_UCR2, sc->sc_ucr2);
2438
2439 sc->sc_ucr1 |= IMX_UCR1_UARTEN;
2440 bus_space_write_4(iot, ioh, IMX_UCR1, sc->sc_ucr1);
2441 }
2442 }
2443
2444
2445 void
imxuart_set_frequency(u_int freq,u_int div)2446 imxuart_set_frequency(u_int freq, u_int div)
2447 {
2448 imxuart_freq = freq;
2449 imxuart_freqdiv = div;
2450 }
2451