1 /* $NetBSD: imx31_clock.c,v 1.5 2012/10/27 17:17:39 chs Exp $ */
2 /*
3 * Copyright (c) 2009,2010 Genetec corp. All rights reserved.
4 * Written by Hashimoto Kenichi for Genetec corp.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
31 #include <sys/evcnt.h>
32 #include <sys/atomic.h>
33 #include <sys/time.h>
34 #include <sys/timetc.h>
35
36 #include <sys/types.h>
37 #include <sys/device.h>
38
39 #include <machine/intr.h>
40 #include <sys/bus.h>
41
42 #include <arm/cpu.h>
43 #include <arm/armreg.h>
44 #include <arm/cpufunc.h>
45
46 #include <arm/imx/imx31reg.h>
47 #include <arm/imx/imx31var.h>
48 #if 0 /* notyet */
49 #include <arm/imx/imx31_ccmvar.h>
50 #endif
51 #include <arm/imx/imxclockvar.h>
52 #include <arm/imx/imxepitreg.h>
53
54 #include "imxccm.h" /* if CCM driver is configured into the kernel */
55 #include "opt_imx31clk.h"
56
57 static int imxclock_match(device_t, struct cfdata *, void *);
58 static void imxclock_attach(device_t, device_t, void *);
59
60 struct imxclock_softc *epit1_sc = NULL;
61 struct imxclock_softc *epit2_sc = NULL;
62
63 CFATTACH_DECL_NEW(imxclock, sizeof(struct imxclock_softc),
64 imxclock_match, imxclock_attach, NULL, NULL);
65
66 static int
imxclock_match(device_t parent,struct cfdata * match,void * aux)67 imxclock_match(device_t parent, struct cfdata *match, void *aux)
68 {
69 struct aips_attach_args *aipsa = aux;
70
71 if ( (aipsa->aipsa_addr != EPIT1_BASE) &&
72 (aipsa->aipsa_addr != EPIT2_BASE) ) {
73 return 0;
74 }
75
76 return 2;
77 }
78
79 static void
imxclock_attach(device_t parent,device_t self,void * aux)80 imxclock_attach(device_t parent, device_t self, void *aux)
81 {
82 struct imxclock_softc *sc = device_private(self);
83 struct aips_attach_args *aipsa = aux;
84
85 aprint_normal("\n");
86
87 sc->sc_dev = self;
88 sc->sc_iot = aipsa->aipsa_memt;
89 sc->sc_intr = aipsa->aipsa_intr;
90
91 KASSERT((sc->sc_intr == IRQ_EPIT1) || (sc->sc_intr == IRQ_EPIT2));
92
93 switch ( aipsa->aipsa_addr ) {
94 case EPIT1_BASE:
95 epit1_sc = sc;
96 break;
97 case EPIT2_BASE:
98 epit2_sc = sc;
99 break;
100 default:
101 panic("%s: invalid address %p", device_xname(self), (void *)aipsa->aipsa_addr);
102 break;
103 }
104
105 if (bus_space_map(aipsa->aipsa_memt, aipsa->aipsa_addr,
106 aipsa->aipsa_size, 0, &sc->sc_ioh)) {
107 panic("%s: Cannot map registers", device_xname(self));
108 }
109
110 sc->sc_clksrc = EPITCR_CLKSRC_HIGH;
111 }
112
113 int
imxclock_get_timerfreq(struct imxclock_softc * sc)114 imxclock_get_timerfreq(struct imxclock_softc *sc)
115 {
116 #if NIMXCCM > 0
117 struct imx31_clocks clk;
118 imx31_get_clocks(&clk);
119
120 return clk.ipg_clk;
121 #else
122 #ifndef IMX31_IPGCLK_FREQ
123 #error IMX31_IPGCLK_FREQ need to be defined.
124 #endif
125 return IMX31_IPGCLK_FREQ;
126
127 #endif
128 }
129
130
131