1 /* $NetBSD: apecs_bus_io.c,v 1.13 2023/12/04 00:32:10 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(1, "$NetBSD: apecs_bus_io.c,v 1.13 2023/12/04 00:32:10 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/syslog.h> 37 #include <sys/device.h> 38 39 #include <sys/bus.h> 40 41 #include <alpha/pci/apecsreg.h> 42 #include <alpha/pci/apecsvar.h> 43 44 #define CHIP apecs 45 46 #define CHIP_IO_ARENA(v) (((struct apecs_config *)(v))->ac_io_arena) 47 48 /* IO region 1 */ 49 #define CHIP_IO_W1_BUS_START(v) 0x00000000UL 50 #define CHIP_IO_W1_BUS_END(v) 0x0003ffffUL 51 #define CHIP_IO_W1_SYS_START(v) APECS_PCI_SIO 52 #define CHIP_IO_W1_SYS_END(v) (APECS_PCI_SIO + (0x00040000UL << 5) - 1) 53 54 /* IO region 2 */ 55 #define CHIP_IO_W2_BUS_START(v) \ 56 ((((struct apecs_config *)(v))->ac_haxr2 & EPIC_HAXR2_EADDR) + \ 57 0x00040000UL) 58 #define CHIP_IO_W2_BUS_END(v) \ 59 ((((struct apecs_config *)(v))->ac_haxr2 & EPIC_HAXR2_EADDR) + \ 60 0x00ffffffUL) 61 #define CHIP_IO_W2_SYS_START(v) (APECS_PCI_SIO + (0x00040000UL << 5)) 62 #define CHIP_IO_W2_SYS_END(v) (APECS_PCI_SIO + (0x01000000UL << 5) - 1) 63 64 #include <alpha/pci/pci_swiz_bus_io_chipdep.c> 65