1 /* $OpenBSD: aplgpio.c,v 1.6 2022/10/20 20:40:57 kettenis Exp $ */
2 /*
3 * Copyright (c) 2016 Mark Kettenis
4 * Copyright (c) 2019 James Hastings
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #include <sys/param.h>
20 #include <sys/malloc.h>
21 #include <sys/systm.h>
22
23 #include <dev/acpi/acpireg.h>
24 #include <dev/acpi/acpivar.h>
25 #include <dev/acpi/acpidev.h>
26 #include <dev/acpi/amltypes.h>
27 #include <dev/acpi/dsdt.h>
28
29 #define APLGPIO_CONF_TXSTATE 0x00000001
30 #define APLGPIO_CONF_RXSTATE 0x00000002
31 #define APLGPIO_CONF_RXINV 0x00800000
32 #define APLGPIO_CONF_RXEV_EDGE 0x02000000
33 #define APLGPIO_CONF_RXEV_ZERO 0x04000000
34 #define APLGPIO_CONF_RXEV_MASK 0x06000000
35
36 #define APLGPIO_IRQ_STS 0x100
37 #define APLGPIO_IRQ_EN 0x110
38 #define APLGPIO_PAD_CFG0 0x500
39
40 struct aplgpio_intrhand {
41 int (*ih_func)(void *);
42 void *ih_arg;
43 };
44
45 struct aplgpio_softc {
46 struct device sc_dev;
47 struct acpi_softc *sc_acpi;
48 struct aml_node *sc_node;
49
50 bus_space_tag_t sc_memt;
51 bus_space_handle_t sc_memh;
52 void *sc_ih;
53
54 int sc_npins;
55 struct aplgpio_intrhand *sc_pin_ih;
56
57 struct acpi_gpio sc_gpio;
58 };
59
60 int aplgpio_match(struct device *, void *, void *);
61 void aplgpio_attach(struct device *, struct device *, void *);
62
63 const struct cfattach aplgpio_ca = {
64 sizeof(struct aplgpio_softc), aplgpio_match, aplgpio_attach
65 };
66
67 struct cfdriver aplgpio_cd = {
68 NULL, "aplgpio", DV_DULL
69 };
70
71 const char *aplgpio_hids[] = {
72 "INT3452",
73 NULL
74 };
75
76 int aplgpio_read_pin(void *, int);
77 void aplgpio_write_pin(void *, int, int);
78 void aplgpio_intr_establish(void *, int, int, int (*)(void *), void *);
79 void aplgpio_intr_enable(void *, int);
80 void aplgpio_intr_disable(void *, int);
81 int aplgpio_intr(void *);
82
83 int
aplgpio_match(struct device * parent,void * match,void * aux)84 aplgpio_match(struct device *parent, void *match, void *aux)
85 {
86 struct acpi_attach_args *aaa = aux;
87 struct cfdata *cf = match;
88
89 if (aaa->aaa_naddr < 1 || aaa->aaa_nirq < 1)
90 return 0;
91 return acpi_matchhids(aaa, aplgpio_hids, cf->cf_driver->cd_name);
92 }
93
94 void
aplgpio_attach(struct device * parent,struct device * self,void * aux)95 aplgpio_attach(struct device *parent, struct device *self, void *aux)
96 {
97 struct aplgpio_softc *sc = (struct aplgpio_softc *)self;
98 struct acpi_attach_args *aaa = aux;
99 int64_t uid;
100 int i;
101
102 sc->sc_acpi = (struct acpi_softc *)parent;
103 sc->sc_node = aaa->aaa_node;
104 printf(" %s", sc->sc_node->name);
105
106 if (aml_evalinteger(sc->sc_acpi, sc->sc_node, "_UID", 0, NULL, &uid)) {
107 printf(": can't find uid\n");
108 return;
109 }
110
111 printf(" uid %lld", uid);
112
113 switch (uid) {
114 case 1:
115 sc->sc_npins = 78;
116 break;
117 case 2:
118 sc->sc_npins = 77;
119 break;
120 case 3:
121 sc->sc_npins = 47;
122 break;
123 case 4:
124 sc->sc_npins = 43;
125 break;
126 default:
127 printf("\n");
128 return;
129 }
130
131 printf(" addr 0x%llx/0x%llx", aaa->aaa_addr[0], aaa->aaa_size[0]);
132 printf(" irq %d", aaa->aaa_irq[0]);
133
134 sc->sc_memt = aaa->aaa_bst[0];
135 if (bus_space_map(sc->sc_memt, aaa->aaa_addr[0], aaa->aaa_size[0],
136 0, &sc->sc_memh)) {
137 printf(": can't map registers\n");
138 return;
139 }
140
141 sc->sc_pin_ih = mallocarray(sc->sc_npins, sizeof(*sc->sc_pin_ih),
142 M_DEVBUF, M_WAITOK | M_ZERO);
143
144 sc->sc_ih = acpi_intr_establish(aaa->aaa_irq[0], aaa->aaa_irq_flags[0],
145 IPL_BIO, aplgpio_intr, sc, sc->sc_dev.dv_xname);
146 if (sc->sc_ih == NULL) {
147 printf(": can't establish interrupt\n");
148 goto unmap;
149 }
150
151 sc->sc_gpio.cookie = sc;
152 sc->sc_gpio.read_pin = aplgpio_read_pin;
153 sc->sc_gpio.write_pin = aplgpio_write_pin;
154 sc->sc_gpio.intr_establish = aplgpio_intr_establish;
155 sc->sc_gpio.intr_enable = aplgpio_intr_enable;
156 sc->sc_gpio.intr_disable = aplgpio_intr_disable;
157 sc->sc_node->gpio = &sc->sc_gpio;
158
159 /* Mask and clear all interrupts. */
160 for (i = 0; i < sc->sc_npins; i++) {
161 if (i % 32 == 0) {
162 bus_space_write_4(sc->sc_memt, sc->sc_memh,
163 APLGPIO_IRQ_EN + (i / 32) * 4, 0x00000000);
164 bus_space_write_4(sc->sc_memt, sc->sc_memh,
165 APLGPIO_IRQ_STS + (i / 32) * 4, 0xffffffff);
166 }
167 }
168
169 printf(", %d pins\n", sc->sc_npins);
170
171 acpi_register_gpio(sc->sc_acpi, sc->sc_node);
172 return;
173
174 unmap:
175 free(sc->sc_pin_ih, M_DEVBUF, sc->sc_npins * sizeof(*sc->sc_pin_ih));
176 bus_space_unmap(sc->sc_memt, sc->sc_memh, aaa->aaa_size[0]);
177 }
178
179 int
aplgpio_read_pin(void * cookie,int pin)180 aplgpio_read_pin(void *cookie, int pin)
181 {
182 struct aplgpio_softc *sc = cookie;
183 uint32_t reg;
184
185 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
186 APLGPIO_PAD_CFG0 + pin * 8);
187
188 return !!(reg & APLGPIO_CONF_RXSTATE);
189 }
190
191 void
aplgpio_write_pin(void * cookie,int pin,int value)192 aplgpio_write_pin(void *cookie, int pin, int value)
193 {
194 struct aplgpio_softc *sc = cookie;
195 uint32_t reg;
196
197 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
198 APLGPIO_PAD_CFG0 + pin * 8);
199 if (value)
200 reg |= APLGPIO_CONF_TXSTATE;
201 else
202 reg &= ~APLGPIO_CONF_TXSTATE;
203 bus_space_write_4(sc->sc_memt, sc->sc_memh,
204 APLGPIO_PAD_CFG0 + pin * 8, reg);
205 }
206
207 void
aplgpio_intr_establish(void * cookie,int pin,int flags,int (* func)(void *),void * arg)208 aplgpio_intr_establish(void *cookie, int pin, int flags,
209 int (*func)(void *), void *arg)
210 {
211 struct aplgpio_softc *sc = cookie;
212 uint32_t reg;
213
214 KASSERT(pin >= 0 && pin < sc->sc_npins);
215
216 sc->sc_pin_ih[pin].ih_func = func;
217 sc->sc_pin_ih[pin].ih_arg = arg;
218
219 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
220 APLGPIO_PAD_CFG0 + pin * 8);
221 reg &= ~(APLGPIO_CONF_RXEV_MASK | APLGPIO_CONF_RXINV);
222 if ((flags & LR_GPIO_MODE) == 1)
223 reg |= APLGPIO_CONF_RXEV_EDGE;
224 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTLO)
225 reg |= APLGPIO_CONF_RXINV;
226 if ((flags & LR_GPIO_POLARITY) == LR_GPIO_ACTBOTH)
227 reg |= APLGPIO_CONF_RXEV_EDGE | APLGPIO_CONF_RXEV_ZERO;
228 bus_space_write_4(sc->sc_memt, sc->sc_memh,
229 APLGPIO_PAD_CFG0 + pin * 8, reg);
230
231 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
232 APLGPIO_IRQ_EN + (pin / 32) * 4);
233 reg |= (1 << (pin % 32));
234 bus_space_write_4(sc->sc_memt, sc->sc_memh,
235 APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
236 }
237
238 void
aplgpio_intr_enable(void * cookie,int pin)239 aplgpio_intr_enable(void *cookie, int pin)
240 {
241 struct aplgpio_softc *sc = cookie;
242 uint32_t reg;
243
244 KASSERT(pin >= 0 && pin < sc->sc_npins);
245
246 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
247 APLGPIO_IRQ_EN + (pin / 32) * 4);
248 reg |= (1 << (pin % 32));
249 bus_space_write_4(sc->sc_memt, sc->sc_memh,
250 APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
251 }
252
253 void
aplgpio_intr_disable(void * cookie,int pin)254 aplgpio_intr_disable(void *cookie, int pin)
255 {
256 struct aplgpio_softc *sc = cookie;
257 uint32_t reg;
258
259 KASSERT(pin >= 0 && pin < sc->sc_npins);
260
261 reg = bus_space_read_4(sc->sc_memt, sc->sc_memh,
262 APLGPIO_IRQ_EN + (pin / 32) * 4);
263 reg &= ~(1 << (pin % 32));
264 bus_space_write_4(sc->sc_memt, sc->sc_memh,
265 APLGPIO_IRQ_EN + (pin / 32) * 4, reg);
266 }
267
268 int
aplgpio_intr(void * arg)269 aplgpio_intr(void *arg)
270 {
271 struct aplgpio_softc *sc = arg;
272 uint32_t status, enable;
273 int rc = 0;
274 int pin;
275
276 for (pin = 0; pin < sc->sc_npins; pin++) {
277 if (pin % 32 == 0) {
278 status = bus_space_read_4(sc->sc_memt, sc->sc_memh,
279 APLGPIO_IRQ_STS + (pin / 32) * 4);
280 bus_space_write_4(sc->sc_memt, sc->sc_memh,
281 APLGPIO_IRQ_STS + (pin / 32) * 4, status);
282 enable = bus_space_read_4(sc->sc_memt, sc->sc_memh,
283 APLGPIO_IRQ_EN + (pin / 32) * 4);
284 status &= enable;
285 }
286 if (status & (1 << (pin % 32))) {
287 if (sc->sc_pin_ih[pin].ih_func)
288 sc->sc_pin_ih[pin].ih_func(sc->sc_pin_ih[pin].ih_arg);
289 rc = 1;
290 }
291 }
292 return rc;
293 }
294