1 /* $NetBSD: amdgpu_uvd.h,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __AMDGPU_UVD_H__ 27 #define __AMDGPU_UVD_H__ 28 29 #define AMDGPU_DEFAULT_UVD_HANDLES 10 30 #define AMDGPU_MAX_UVD_HANDLES 40 31 #define AMDGPU_UVD_STACK_SIZE (200*1024) 32 #define AMDGPU_UVD_HEAP_SIZE (256*1024) 33 #define AMDGPU_UVD_SESSION_SIZE (50*1024) 34 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 35 36 #define AMDGPU_MAX_UVD_INSTANCES 2 37 38 #define AMDGPU_UVD_FIRMWARE_SIZE(adev) \ 39 (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \ 40 8) - AMDGPU_UVD_FIRMWARE_OFFSET) 41 42 struct amdgpu_uvd_inst { 43 struct amdgpu_bo *vcpu_bo; 44 void *cpu_addr; 45 uint64_t gpu_addr; 46 void *saved_bo; 47 struct amdgpu_ring ring; 48 struct amdgpu_ring ring_enc[AMDGPU_MAX_UVD_ENC_RINGS]; 49 struct amdgpu_irq_src irq; 50 uint32_t srbm_soft_reset; 51 }; 52 53 #define AMDGPU_UVD_HARVEST_UVD0 (1 << 0) 54 #define AMDGPU_UVD_HARVEST_UVD1 (1 << 1) 55 56 struct amdgpu_uvd { 57 const struct firmware *fw; /* UVD firmware */ 58 unsigned fw_version; 59 unsigned max_handles; 60 unsigned num_enc_rings; 61 uint8_t num_uvd_inst; 62 bool address_64_bit; 63 bool use_ctx_buf; 64 struct amdgpu_uvd_inst inst[AMDGPU_MAX_UVD_INSTANCES]; 65 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 66 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 67 struct drm_sched_entity entity; 68 struct delayed_work idle_work; 69 unsigned harvest_config; 70 /* store image width to adjust nb memory state */ 71 unsigned decode_image_width; 72 }; 73 74 int amdgpu_uvd_sw_init(struct amdgpu_device *adev); 75 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev); 76 int amdgpu_uvd_entity_init(struct amdgpu_device *adev); 77 int amdgpu_uvd_suspend(struct amdgpu_device *adev); 78 int amdgpu_uvd_resume(struct amdgpu_device *adev); 79 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 80 struct dma_fence **fence); 81 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 82 bool direct, struct dma_fence **fence); 83 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, 84 struct drm_file *filp); 85 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx); 86 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring); 87 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring); 88 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout); 89 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev); 90 91 #endif 92