1 /* $NetBSD: amdgpu_umc.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __AMDGPU_UMC_H__ 24 #define __AMDGPU_UMC_H__ 25 26 struct amdgpu_umc_funcs { 27 void (*err_cnt_init)(struct amdgpu_device *adev); 28 int (*ras_late_init)(struct amdgpu_device *adev); 29 void (*query_ras_error_count)(struct amdgpu_device *adev, 30 void *ras_error_status); 31 void (*query_ras_error_address)(struct amdgpu_device *adev, 32 void *ras_error_status); 33 void (*init_registers)(struct amdgpu_device *adev); 34 }; 35 36 struct amdgpu_umc { 37 /* max error count in one ras query call */ 38 uint32_t max_ras_err_cnt_per_query; 39 /* number of umc channel instance with memory map register access */ 40 uint32_t channel_inst_num; 41 /* number of umc instance with memory map register access */ 42 uint32_t umc_inst_num; 43 /* UMC regiser per channel offset */ 44 uint32_t channel_offs; 45 /* channel index table of interleaved memory */ 46 const uint32_t *channel_idx_tbl; 47 struct ras_common_if *ras_if; 48 49 const struct amdgpu_umc_funcs *funcs; 50 }; 51 52 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev); 53 void amdgpu_umc_ras_fini(struct amdgpu_device *adev); 54 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 55 void *ras_error_status, 56 struct amdgpu_iv_entry *entry); 57 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 58 struct amdgpu_irq_src *source, 59 struct amdgpu_iv_entry *entry); 60 #endif 61