1 /* $NetBSD: amdgpu_mes.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __AMDGPU_MES_H__ 27 #define __AMDGPU_MES_H__ 28 29 struct amdgpu_mes_funcs; 30 31 struct amdgpu_mes { 32 struct amdgpu_adev *adev; 33 34 const struct firmware *fw; 35 36 /* mes ucode */ 37 struct amdgpu_bo *ucode_fw_obj; 38 uint64_t ucode_fw_gpu_addr; 39 uint32_t *ucode_fw_ptr; 40 uint32_t ucode_fw_version; 41 uint64_t uc_start_addr; 42 43 /* mes ucode data */ 44 struct amdgpu_bo *data_fw_obj; 45 uint64_t data_fw_gpu_addr; 46 uint32_t *data_fw_ptr; 47 uint32_t data_fw_version; 48 uint64_t data_start_addr; 49 50 /* ip specific functions */ 51 struct amdgpu_mes_funcs *funcs; 52 }; 53 54 struct mes_add_queue_input { 55 uint32_t process_id; 56 uint64_t page_table_base_addr; 57 uint64_t process_va_start; 58 uint64_t process_va_end; 59 uint64_t process_quantum; 60 uint64_t process_context_addr; 61 uint64_t gang_quantum; 62 uint64_t gang_context_addr; 63 uint32_t inprocess_gang_priority; 64 uint32_t gang_global_priority_level; 65 uint32_t doorbell_offset; 66 uint64_t mqd_addr; 67 uint64_t wptr_addr; 68 uint32_t queue_type; 69 uint32_t paging; 70 }; 71 72 struct mes_remove_queue_input { 73 uint32_t doorbell_offset; 74 uint64_t gang_context_addr; 75 }; 76 77 struct mes_suspend_gang_input { 78 bool suspend_all_gangs; 79 uint64_t gang_context_addr; 80 uint64_t suspend_fence_addr; 81 uint32_t suspend_fence_value; 82 }; 83 84 struct mes_resume_gang_input { 85 bool resume_all_gangs; 86 uint64_t gang_context_addr; 87 }; 88 89 struct amdgpu_mes_funcs { 90 int (*add_hw_queue)(struct amdgpu_mes *mes, 91 struct mes_add_queue_input *input); 92 93 int (*remove_hw_queue)(struct amdgpu_mes *mes, 94 struct mes_remove_queue_input *input); 95 96 int (*suspend_gang)(struct amdgpu_mes *mes, 97 struct mes_suspend_gang_input *input); 98 99 int (*resume_gang)(struct amdgpu_mes *mes, 100 struct mes_resume_gang_input *input); 101 }; 102 103 #endif /* __AMDGPU_MES_H__ */ 104