1 /* $NetBSD: amdgpu_job.h,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __AMDGPU_JOB_H__ 26 #define __AMDGPU_JOB_H__ 27 28 /* bit set means command submit involves a preamble IB */ 29 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) 30 /* bit set means preamble IB is first presented in belonging context */ 31 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) 32 /* bit set means context switch occured */ 33 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) 34 /* bit set means IB is preempted */ 35 #define AMDGPU_IB_PREEMPTED (1 << 3) 36 37 #define to_amdgpu_job(sched_job) \ 38 container_of((sched_job), struct amdgpu_job, base) 39 40 #define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0) 41 42 struct amdgpu_fence; 43 44 struct amdgpu_job { 45 struct drm_sched_job base; 46 struct amdgpu_vm *vm; 47 struct amdgpu_sync sync; 48 struct amdgpu_sync sched_sync; 49 struct amdgpu_ib *ibs; 50 struct dma_fence *fence; /* the hw fence */ 51 uint32_t preamble_status; 52 uint32_t preemption_status; 53 uint32_t num_ibs; 54 bool vm_needs_flush; 55 uint64_t vm_pd_addr; 56 unsigned vmid; 57 unsigned pasid; 58 uint32_t gds_base, gds_size; 59 uint32_t gws_base, gws_size; 60 uint32_t oa_base, oa_size; 61 uint32_t vram_lost_counter; 62 63 /* user fence handling */ 64 uint64_t uf_addr; 65 uint64_t uf_sequence; 66 67 }; 68 69 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 70 struct amdgpu_job **job, struct amdgpu_vm *vm); 71 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 72 struct amdgpu_job **job); 73 74 void amdgpu_job_free_resources(struct amdgpu_job *job); 75 void amdgpu_job_free(struct amdgpu_job *job); 76 int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 77 void *owner, struct dma_fence **f); 78 int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 79 struct dma_fence **fence); 80 81 void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched); 82 83 #endif 84