1 /* $NetBSD: amdgpu_ih.h,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __AMDGPU_IH_H__ 27 #define __AMDGPU_IH_H__ 28 29 /* Maximum number of IVs processed at once */ 30 #define AMDGPU_IH_MAX_NUM_IVS 32 31 32 struct amdgpu_device; 33 struct amdgpu_iv_entry; 34 35 /* 36 * R6xx+ IH ring 37 */ 38 struct amdgpu_ih_ring { 39 unsigned ring_size; 40 uint32_t ptr_mask; 41 u32 doorbell_index; 42 bool use_doorbell; 43 bool use_bus_addr; 44 45 struct amdgpu_bo *ring_obj; 46 #ifdef __NetBSD__ 47 bus_dma_segment_t ring_seg; 48 bus_dmamap_t ring_map; 49 #endif 50 volatile uint32_t *ring; 51 uint64_t gpu_addr; 52 53 uint64_t wptr_addr; 54 volatile uint32_t *wptr_cpu; 55 56 uint64_t rptr_addr; 57 volatile uint32_t *rptr_cpu; 58 59 bool enabled; 60 unsigned rptr; 61 atomic_t lock; 62 }; 63 64 /* provided by the ih block */ 65 struct amdgpu_ih_funcs { 66 /* ring read/write ptr handling, called from interrupt context */ 67 u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 68 void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 69 struct amdgpu_iv_entry *entry); 70 void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 71 }; 72 73 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) 74 #define amdgpu_ih_decode_iv(adev, iv) \ 75 (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv)) 76 #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih)) 77 78 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 79 unsigned ring_size, bool use_bus_addr); 80 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 81 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 82 83 #endif 84