1 /* $NetBSD: amdgpu_i2c.c,v 1.6 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2007-8 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors: Dave Airlie
26 * Alex Deucher
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_i2c.c,v 1.6 2021/12/18 23:44:58 riastradh Exp $");
31
32 #include <linux/export.h>
33 #include <linux/pci.h>
34
35 #include <drm/drm_edid.h>
36 #include <drm/amdgpu_drm.h>
37 #include "amdgpu.h"
38 #include "amdgpu_i2c.h"
39 #include "amdgpu_atombios.h"
40 #include "atom.h"
41 #include "atombios_dp.h"
42 #include "atombios_i2c.h"
43
44 #include <linux/nbsd-namespace.h>
45
46 /* bit banging i2c */
amdgpu_i2c_pre_xfer(struct i2c_adapter * i2c_adap)47 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap)
48 {
49 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
50 struct amdgpu_device *adev = i2c->dev->dev_private;
51 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
52 uint32_t temp;
53
54 mutex_lock(&i2c->mutex);
55
56 /* switch the pads to ddc mode */
57 if (rec->hw_capable) {
58 temp = RREG32(rec->mask_clk_reg);
59 temp &= ~(1 << 16);
60 WREG32(rec->mask_clk_reg, temp);
61 }
62
63 /* clear the output pin values */
64 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
65 WREG32(rec->a_clk_reg, temp);
66
67 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
68 WREG32(rec->a_data_reg, temp);
69
70 /* set the pins to input */
71 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
72 WREG32(rec->en_clk_reg, temp);
73
74 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
75 WREG32(rec->en_data_reg, temp);
76
77 /* mask the gpio pins for software use */
78 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
79 WREG32(rec->mask_clk_reg, temp);
80 temp = RREG32(rec->mask_clk_reg);
81
82 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
83 WREG32(rec->mask_data_reg, temp);
84 temp = RREG32(rec->mask_data_reg);
85
86 return 0;
87 }
88
amdgpu_i2c_post_xfer(struct i2c_adapter * i2c_adap)89 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap)
90 {
91 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
92 struct amdgpu_device *adev = i2c->dev->dev_private;
93 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
94 uint32_t temp;
95
96 /* unmask the gpio pins for software use */
97 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
98 WREG32(rec->mask_clk_reg, temp);
99 temp = RREG32(rec->mask_clk_reg);
100
101 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
102 WREG32(rec->mask_data_reg, temp);
103 temp = RREG32(rec->mask_data_reg);
104
105 mutex_unlock(&i2c->mutex);
106 }
107
amdgpu_i2c_get_clock(void * i2c_priv)108 static int amdgpu_i2c_get_clock(void *i2c_priv)
109 {
110 struct amdgpu_i2c_chan *i2c = i2c_priv;
111 struct amdgpu_device *adev = i2c->dev->dev_private;
112 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
113 uint32_t val;
114
115 /* read the value off the pin */
116 val = RREG32(rec->y_clk_reg);
117 val &= rec->y_clk_mask;
118
119 return (val != 0);
120 }
121
122
amdgpu_i2c_get_data(void * i2c_priv)123 static int amdgpu_i2c_get_data(void *i2c_priv)
124 {
125 struct amdgpu_i2c_chan *i2c = i2c_priv;
126 struct amdgpu_device *adev = i2c->dev->dev_private;
127 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
128 uint32_t val;
129
130 /* read the value off the pin */
131 val = RREG32(rec->y_data_reg);
132 val &= rec->y_data_mask;
133
134 return (val != 0);
135 }
136
amdgpu_i2c_set_clock(void * i2c_priv,int clock)137 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)
138 {
139 struct amdgpu_i2c_chan *i2c = i2c_priv;
140 struct amdgpu_device *adev = i2c->dev->dev_private;
141 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
142 uint32_t val;
143
144 /* set pin direction */
145 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
146 val |= clock ? 0 : rec->en_clk_mask;
147 WREG32(rec->en_clk_reg, val);
148 }
149
amdgpu_i2c_set_data(void * i2c_priv,int data)150 static void amdgpu_i2c_set_data(void *i2c_priv, int data)
151 {
152 struct amdgpu_i2c_chan *i2c = i2c_priv;
153 struct amdgpu_device *adev = i2c->dev->dev_private;
154 struct amdgpu_i2c_bus_rec *rec = &i2c->rec;
155 uint32_t val;
156
157 /* set pin direction */
158 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
159 val |= data ? 0 : rec->en_data_mask;
160 WREG32(rec->en_data_reg, val);
161 }
162
163 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = {
164 .master_xfer = amdgpu_atombios_i2c_xfer,
165 .functionality = amdgpu_atombios_i2c_func,
166 };
167
amdgpu_i2c_create(struct drm_device * dev,const struct amdgpu_i2c_bus_rec * rec,const char * name)168 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev,
169 const struct amdgpu_i2c_bus_rec *rec,
170 const char *name)
171 {
172 struct amdgpu_i2c_chan *i2c;
173 int ret;
174
175 /* don't add the mm_i2c bus unless hw_i2c is enabled */
176 if (rec->mm_i2c && (amdgpu_hw_i2c == 0))
177 return NULL;
178
179 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL);
180 if (i2c == NULL)
181 return NULL;
182
183 i2c->rec = *rec;
184 i2c->adapter.owner = THIS_MODULE;
185 i2c->adapter.class = I2C_CLASS_DDC;
186 i2c->adapter.dev.parent = dev->dev;
187 i2c->dev = dev;
188 i2c_set_adapdata(&i2c->adapter, i2c);
189 mutex_init(&i2c->mutex);
190 if (rec->hw_capable &&
191 amdgpu_hw_i2c) {
192 /* hw i2c using atom */
193 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
194 "AMDGPU i2c hw bus %s", name);
195 i2c->adapter.algo = &amdgpu_atombios_i2c_algo;
196 ret = i2c_add_adapter(&i2c->adapter);
197 if (ret)
198 goto out_free;
199 } else {
200 /* set the amdgpu bit adapter */
201 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
202 "AMDGPU i2c bit bus %s", name);
203 i2c->adapter.algo_data = &i2c->bit;
204 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer;
205 i2c->bit.post_xfer = amdgpu_i2c_post_xfer;
206 i2c->bit.setsda = amdgpu_i2c_set_data;
207 i2c->bit.setscl = amdgpu_i2c_set_clock;
208 i2c->bit.getsda = amdgpu_i2c_get_data;
209 i2c->bit.getscl = amdgpu_i2c_get_clock;
210 i2c->bit.udelay = 10;
211 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */
212 i2c->bit.data = i2c;
213 ret = i2c_bit_add_bus(&i2c->adapter);
214 if (ret) {
215 DRM_ERROR("Failed to register bit i2c %s\n", name);
216 goto out_free;
217 }
218 }
219
220 return i2c;
221 out_free:
222 mutex_destroy(&i2c->mutex);
223 kfree(i2c);
224 return NULL;
225
226 }
227
amdgpu_i2c_destroy(struct amdgpu_i2c_chan * i2c)228 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c)
229 {
230 if (!i2c)
231 return;
232 WARN_ON(i2c->has_aux);
233 i2c_del_adapter(&i2c->adapter);
234 mutex_destroy(&i2c->mutex);
235 kfree(i2c);
236 }
237
238 /* Add the default buses */
amdgpu_i2c_init(struct amdgpu_device * adev)239 void amdgpu_i2c_init(struct amdgpu_device *adev)
240 {
241 if (amdgpu_hw_i2c)
242 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n");
243
244 amdgpu_atombios_i2c_init(adev);
245 }
246
247 /* remove all the buses */
amdgpu_i2c_fini(struct amdgpu_device * adev)248 void amdgpu_i2c_fini(struct amdgpu_device *adev)
249 {
250 int i;
251
252 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
253 if (adev->i2c_bus[i]) {
254 amdgpu_i2c_destroy(adev->i2c_bus[i]);
255 adev->i2c_bus[i] = NULL;
256 }
257 }
258 }
259
260 /* Add additional buses */
amdgpu_i2c_add(struct amdgpu_device * adev,const struct amdgpu_i2c_bus_rec * rec,const char * name)261 void amdgpu_i2c_add(struct amdgpu_device *adev,
262 const struct amdgpu_i2c_bus_rec *rec,
263 const char *name)
264 {
265 struct drm_device *dev = adev->ddev;
266 int i;
267
268 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
269 if (!adev->i2c_bus[i]) {
270 adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name);
271 return;
272 }
273 }
274 }
275
276 /* looks up bus based on id */
277 struct amdgpu_i2c_chan *
amdgpu_i2c_lookup(struct amdgpu_device * adev,const struct amdgpu_i2c_bus_rec * i2c_bus)278 amdgpu_i2c_lookup(struct amdgpu_device *adev,
279 const struct amdgpu_i2c_bus_rec *i2c_bus)
280 {
281 int i;
282
283 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) {
284 if (adev->i2c_bus[i] &&
285 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
286 return adev->i2c_bus[i];
287 }
288 }
289 return NULL;
290 }
291
amdgpu_i2c_get_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 * val)292 static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus,
293 u8 slave_addr,
294 u8 addr,
295 u8 *val)
296 {
297 u8 out_buf[2];
298 u8 in_buf[2];
299 struct i2c_msg msgs[] = {
300 {
301 .addr = slave_addr,
302 .flags = 0,
303 .len = 1,
304 .buf = out_buf,
305 },
306 {
307 .addr = slave_addr,
308 .flags = I2C_M_RD,
309 .len = 1,
310 .buf = in_buf,
311 }
312 };
313
314 out_buf[0] = addr;
315 out_buf[1] = 0;
316
317 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) {
318 *val = in_buf[0];
319 DRM_DEBUG("val = 0x%02x\n", *val);
320 } else {
321 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
322 addr, *val);
323 }
324 }
325
amdgpu_i2c_put_byte(struct amdgpu_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 val)326 static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
327 u8 slave_addr,
328 u8 addr,
329 u8 val)
330 {
331 uint8_t out_buf[2];
332 struct i2c_msg msg = {
333 .addr = slave_addr,
334 .flags = 0,
335 .len = 2,
336 .buf = out_buf,
337 };
338
339 out_buf[0] = addr;
340 out_buf[1] = val;
341
342 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1)
343 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
344 addr, val);
345 }
346
347 /* ddc router switching */
348 void
amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector * amdgpu_connector)349 amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
350 {
351 u8 val;
352
353 if (!amdgpu_connector->router.ddc_valid)
354 return;
355
356 if (!amdgpu_connector->router_bus)
357 return;
358
359 amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
360 amdgpu_connector->router.i2c_addr,
361 0x3, &val);
362 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
363 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
364 amdgpu_connector->router.i2c_addr,
365 0x3, val);
366 amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
367 amdgpu_connector->router.i2c_addr,
368 0x1, &val);
369 val &= ~amdgpu_connector->router.ddc_mux_control_pin;
370 val |= amdgpu_connector->router.ddc_mux_state;
371 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
372 amdgpu_connector->router.i2c_addr,
373 0x1, val);
374 }
375
376 /* clock/data router switching */
377 void
amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector * amdgpu_connector)378 amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector)
379 {
380 u8 val;
381
382 if (!amdgpu_connector->router.cd_valid)
383 return;
384
385 if (!amdgpu_connector->router_bus)
386 return;
387
388 amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
389 amdgpu_connector->router.i2c_addr,
390 0x3, &val);
391 val &= ~amdgpu_connector->router.cd_mux_control_pin;
392 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
393 amdgpu_connector->router.i2c_addr,
394 0x3, val);
395 amdgpu_i2c_get_byte(amdgpu_connector->router_bus,
396 amdgpu_connector->router.i2c_addr,
397 0x1, &val);
398 val &= ~amdgpu_connector->router.cd_mux_control_pin;
399 val |= amdgpu_connector->router.cd_mux_state;
400 amdgpu_i2c_put_byte(amdgpu_connector->router_bus,
401 amdgpu_connector->router.i2c_addr,
402 0x1, val);
403 }
404