1 /* $NetBSD: amdgpu_dc_debug.c,v 1.3 2021/12/19 10:59:01 riastradh Exp $ */
2
3 /*
4 * Copyright 2017 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 /*
26 * dc_debug.c
27 *
28 * Created on: Nov 3, 2016
29 * Author: yonsun
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dc_debug.c,v 1.3 2021/12/19 10:59:01 riastradh Exp $");
34
35 #include "dm_services.h"
36
37 #include "dc.h"
38
39 #include "core_status.h"
40 #include "core_types.h"
41
42 #include "resource.h"
43
44 #define DC_LOGGER_INIT(logger)
45
46
47 #define SURFACE_TRACE(...) do {\
48 if (dc->debug.surface_trace) \
49 DC_LOG_IF_TRACE(__VA_ARGS__); \
50 } while (0)
51
52 #define TIMING_TRACE(...) do {\
53 if (dc->debug.timing_trace) \
54 DC_LOG_SYNC(__VA_ARGS__); \
55 } while (0)
56
57 #define CLOCK_TRACE(...) do {\
58 if (dc->debug.clock_trace) \
59 DC_LOG_BANDWIDTH_CALCS(__VA_ARGS__); \
60 } while (0)
61
pre_surface_trace(struct dc * dc,const struct dc_plane_state * const * plane_states,int surface_count)62 void pre_surface_trace(
63 struct dc *dc,
64 const struct dc_plane_state *const *plane_states,
65 int surface_count)
66 {
67 int i;
68 DC_LOGGER_INIT(dc->ctx->logger);
69
70 for (i = 0; i < surface_count; i++) {
71 const struct dc_plane_state *plane_state = plane_states[i];
72
73 SURFACE_TRACE("Planes %d:\n", i);
74
75 SURFACE_TRACE(
76 "plane_state->visible = %d;\n"
77 "plane_state->flip_immediate = %d;\n"
78 "plane_state->address.type = %d;\n"
79 "plane_state->address.grph.addr.quad_part = 0x%"PRIX64";\n"
80 "plane_state->address.grph.meta_addr.quad_part = 0x%"PRIX64";\n"
81 "plane_state->scaling_quality.h_taps = %d;\n"
82 "plane_state->scaling_quality.v_taps = %d;\n"
83 "plane_state->scaling_quality.h_taps_c = %d;\n"
84 "plane_state->scaling_quality.v_taps_c = %d;\n",
85 plane_state->visible,
86 plane_state->flip_immediate,
87 plane_state->address.type,
88 plane_state->address.grph.addr.quad_part,
89 plane_state->address.grph.meta_addr.quad_part,
90 plane_state->scaling_quality.h_taps,
91 plane_state->scaling_quality.v_taps,
92 plane_state->scaling_quality.h_taps_c,
93 plane_state->scaling_quality.v_taps_c);
94
95 SURFACE_TRACE(
96 "plane_state->src_rect.x = %d;\n"
97 "plane_state->src_rect.y = %d;\n"
98 "plane_state->src_rect.width = %d;\n"
99 "plane_state->src_rect.height = %d;\n"
100 "plane_state->dst_rect.x = %d;\n"
101 "plane_state->dst_rect.y = %d;\n"
102 "plane_state->dst_rect.width = %d;\n"
103 "plane_state->dst_rect.height = %d;\n"
104 "plane_state->clip_rect.x = %d;\n"
105 "plane_state->clip_rect.y = %d;\n"
106 "plane_state->clip_rect.width = %d;\n"
107 "plane_state->clip_rect.height = %d;\n",
108 plane_state->src_rect.x,
109 plane_state->src_rect.y,
110 plane_state->src_rect.width,
111 plane_state->src_rect.height,
112 plane_state->dst_rect.x,
113 plane_state->dst_rect.y,
114 plane_state->dst_rect.width,
115 plane_state->dst_rect.height,
116 plane_state->clip_rect.x,
117 plane_state->clip_rect.y,
118 plane_state->clip_rect.width,
119 plane_state->clip_rect.height);
120
121 SURFACE_TRACE(
122 "plane_state->plane_size.surface_size.x = %d;\n"
123 "plane_state->plane_size.surface_size.y = %d;\n"
124 "plane_state->plane_size.surface_size.width = %d;\n"
125 "plane_state->plane_size.surface_size.height = %d;\n"
126 "plane_state->plane_size.surface_pitch = %d;\n",
127 plane_state->plane_size.surface_size.x,
128 plane_state->plane_size.surface_size.y,
129 plane_state->plane_size.surface_size.width,
130 plane_state->plane_size.surface_size.height,
131 plane_state->plane_size.surface_pitch);
132
133
134 SURFACE_TRACE(
135 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
136 "plane_state->tiling_info.gfx8.bank_width = %d;\n"
137 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
138 "plane_state->tiling_info.gfx8.bank_height = %d;\n"
139 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
140 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
141 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
142 "plane_state->tiling_info.gfx8.tile_split = %d;\n"
143 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
144 "plane_state->tiling_info.gfx8.tile_mode = %d;\n"
145 "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
146 plane_state->tiling_info.gfx8.num_banks,
147 plane_state->tiling_info.gfx8.bank_width,
148 plane_state->tiling_info.gfx8.bank_width_c,
149 plane_state->tiling_info.gfx8.bank_height,
150 plane_state->tiling_info.gfx8.bank_height_c,
151 plane_state->tiling_info.gfx8.tile_aspect,
152 plane_state->tiling_info.gfx8.tile_aspect_c,
153 plane_state->tiling_info.gfx8.tile_split,
154 plane_state->tiling_info.gfx8.tile_split_c,
155 plane_state->tiling_info.gfx8.tile_mode,
156 plane_state->tiling_info.gfx8.tile_mode_c);
157
158 SURFACE_TRACE(
159 "plane_state->tiling_info.gfx8.pipe_config = %d;\n"
160 "plane_state->tiling_info.gfx8.array_mode = %d;\n"
161 "plane_state->color_space = %d;\n"
162 "plane_state->dcc.enable = %d;\n"
163 "plane_state->format = %d;\n"
164 "plane_state->rotation = %d;\n"
165 "plane_state->stereo_format = %d;\n",
166 plane_state->tiling_info.gfx8.pipe_config,
167 plane_state->tiling_info.gfx8.array_mode,
168 plane_state->color_space,
169 plane_state->dcc.enable,
170 plane_state->format,
171 plane_state->rotation,
172 plane_state->stereo_format);
173
174 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
175 plane_state->tiling_info.gfx9.swizzle);
176
177 SURFACE_TRACE("\n");
178 }
179 SURFACE_TRACE("\n");
180 }
181
update_surface_trace(struct dc * dc,const struct dc_surface_update * updates,int surface_count)182 void update_surface_trace(
183 struct dc *dc,
184 const struct dc_surface_update *updates,
185 int surface_count)
186 {
187 int i;
188 DC_LOGGER_INIT(dc->ctx->logger);
189
190 for (i = 0; i < surface_count; i++) {
191 const struct dc_surface_update *update = &updates[i];
192
193 SURFACE_TRACE("Update %d\n", i);
194 if (update->flip_addr) {
195 SURFACE_TRACE("flip_addr->address.type = %d;\n"
196 "flip_addr->address.grph.addr.quad_part = 0x%"PRIX64";\n"
197 "flip_addr->address.grph.meta_addr.quad_part = 0x%"PRIX64";\n"
198 "flip_addr->flip_immediate = %d;\n",
199 update->flip_addr->address.type,
200 update->flip_addr->address.grph.addr.quad_part,
201 update->flip_addr->address.grph.meta_addr.quad_part,
202 update->flip_addr->flip_immediate);
203 }
204
205 if (update->plane_info) {
206 SURFACE_TRACE(
207 "plane_info->color_space = %d;\n"
208 "plane_info->format = %d;\n"
209 "plane_info->plane_size.surface_pitch = %d;\n"
210 "plane_info->plane_size.surface_size.height = %d;\n"
211 "plane_info->plane_size.surface_size.width = %d;\n"
212 "plane_info->plane_size.surface_size.x = %d;\n"
213 "plane_info->plane_size.surface_size.y = %d;\n"
214 "plane_info->rotation = %d;\n"
215 "plane_info->stereo_format = %d;\n",
216 update->plane_info->color_space,
217 update->plane_info->format,
218 update->plane_info->plane_size.surface_pitch,
219 update->plane_info->plane_size.surface_size.height,
220 update->plane_info->plane_size.surface_size.width,
221 update->plane_info->plane_size.surface_size.x,
222 update->plane_info->plane_size.surface_size.y,
223 update->plane_info->rotation,
224 update->plane_info->stereo_format);
225
226 SURFACE_TRACE(
227 "plane_info->tiling_info.gfx8.num_banks = %d;\n"
228 "plane_info->tiling_info.gfx8.bank_width = %d;\n"
229 "plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
230 "plane_info->tiling_info.gfx8.bank_height = %d;\n"
231 "plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
232 "plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
233 "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
234 "plane_info->tiling_info.gfx8.tile_split = %d;\n"
235 "plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
236 "plane_info->tiling_info.gfx8.tile_mode = %d;\n"
237 "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
238 update->plane_info->tiling_info.gfx8.num_banks,
239 update->plane_info->tiling_info.gfx8.bank_width,
240 update->plane_info->tiling_info.gfx8.bank_width_c,
241 update->plane_info->tiling_info.gfx8.bank_height,
242 update->plane_info->tiling_info.gfx8.bank_height_c,
243 update->plane_info->tiling_info.gfx8.tile_aspect,
244 update->plane_info->tiling_info.gfx8.tile_aspect_c,
245 update->plane_info->tiling_info.gfx8.tile_split,
246 update->plane_info->tiling_info.gfx8.tile_split_c,
247 update->plane_info->tiling_info.gfx8.tile_mode,
248 update->plane_info->tiling_info.gfx8.tile_mode_c);
249
250 SURFACE_TRACE(
251 "plane_info->tiling_info.gfx8.pipe_config = %d;\n"
252 "plane_info->tiling_info.gfx8.array_mode = %d;\n"
253 "plane_info->visible = %d;\n"
254 "plane_info->per_pixel_alpha = %d;\n",
255 update->plane_info->tiling_info.gfx8.pipe_config,
256 update->plane_info->tiling_info.gfx8.array_mode,
257 update->plane_info->visible,
258 update->plane_info->per_pixel_alpha);
259
260 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
261 update->plane_info->tiling_info.gfx9.swizzle);
262 }
263
264 if (update->scaling_info) {
265 SURFACE_TRACE(
266 "scaling_info->src_rect.x = %d;\n"
267 "scaling_info->src_rect.y = %d;\n"
268 "scaling_info->src_rect.width = %d;\n"
269 "scaling_info->src_rect.height = %d;\n"
270 "scaling_info->dst_rect.x = %d;\n"
271 "scaling_info->dst_rect.y = %d;\n"
272 "scaling_info->dst_rect.width = %d;\n"
273 "scaling_info->dst_rect.height = %d;\n"
274 "scaling_info->clip_rect.x = %d;\n"
275 "scaling_info->clip_rect.y = %d;\n"
276 "scaling_info->clip_rect.width = %d;\n"
277 "scaling_info->clip_rect.height = %d;\n"
278 "scaling_info->scaling_quality.h_taps = %d;\n"
279 "scaling_info->scaling_quality.v_taps = %d;\n"
280 "scaling_info->scaling_quality.h_taps_c = %d;\n"
281 "scaling_info->scaling_quality.v_taps_c = %d;\n",
282 update->scaling_info->src_rect.x,
283 update->scaling_info->src_rect.y,
284 update->scaling_info->src_rect.width,
285 update->scaling_info->src_rect.height,
286 update->scaling_info->dst_rect.x,
287 update->scaling_info->dst_rect.y,
288 update->scaling_info->dst_rect.width,
289 update->scaling_info->dst_rect.height,
290 update->scaling_info->clip_rect.x,
291 update->scaling_info->clip_rect.y,
292 update->scaling_info->clip_rect.width,
293 update->scaling_info->clip_rect.height,
294 update->scaling_info->scaling_quality.h_taps,
295 update->scaling_info->scaling_quality.v_taps,
296 update->scaling_info->scaling_quality.h_taps_c,
297 update->scaling_info->scaling_quality.v_taps_c);
298 }
299 SURFACE_TRACE("\n");
300 }
301 SURFACE_TRACE("\n");
302 }
303
post_surface_trace(struct dc * dc)304 void post_surface_trace(struct dc *dc)
305 {
306 DC_LOGGER_INIT(dc->ctx->logger);
307
308 SURFACE_TRACE("post surface process.\n");
309
310 }
311
context_timing_trace(struct dc * dc,struct resource_context * res_ctx)312 void context_timing_trace(
313 struct dc *dc,
314 struct resource_context *res_ctx)
315 {
316 int i;
317 int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0};
318 struct crtc_position position;
319 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
320 DC_LOGGER_INIT(dc->ctx->logger);
321
322
323 for (i = 0; i < dc->res_pool->pipe_count; i++) {
324 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
325 /* get_position() returns CRTC vertical/horizontal counter
326 * hence not applicable for underlay pipe
327 */
328 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
329 continue;
330
331 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
332 h_pos[i] = position.horizontal_count;
333 v_pos[i] = position.vertical_count;
334 }
335 for (i = 0; i < dc->res_pool->pipe_count; i++) {
336 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
337
338 if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx)
339 continue;
340
341 TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
342 pipe_ctx->stream_res.tg->inst,
343 pipe_ctx->stream->timing.h_total,
344 pipe_ctx->stream->timing.v_total,
345 h_pos[i], v_pos[i]);
346 }
347 }
348
context_clock_trace(struct dc * dc,struct dc_state * context)349 void context_clock_trace(
350 struct dc *dc,
351 struct dc_state *context)
352 {
353 #if defined(CONFIG_DRM_AMD_DC_DCN)
354 DC_LOGGER_INIT(dc->ctx->logger);
355 CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
356 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
357 context->bw_ctx.bw.dcn.clk.dispclk_khz,
358 context->bw_ctx.bw.dcn.clk.dppclk_khz,
359 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
360 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
361 context->bw_ctx.bw.dcn.clk.fclk_khz,
362 context->bw_ctx.bw.dcn.clk.socclk_khz);
363 CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
364 "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
365 context->bw_ctx.bw.dcn.clk.dispclk_khz,
366 context->bw_ctx.bw.dcn.clk.dppclk_khz,
367 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
368 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
369 context->bw_ctx.bw.dcn.clk.fclk_khz,
370 context->bw_ctx.bw.dcn.clk.socclk_khz);
371 #endif
372 }
373