1 /* $NetBSD: agp_i810.c,v 1.126 2024/01/29 01:05:55 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2000 Doug Rabson
5 * Copyright (c) 2000 Ruslan Ermilov
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.126 2024/01/29 01:05:55 riastradh Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/atomic.h>
38 #include <sys/malloc.h>
39 #include <sys/kernel.h>
40 #include <sys/proc.h>
41 #include <sys/device.h>
42 #include <sys/conf.h>
43 #include <sys/xcall.h>
44
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcidevs.h>
48 #include <dev/pci/agpvar.h>
49 #include <dev/pci/agpreg.h>
50 #include <dev/pci/agp_i810var.h>
51
52 #include <sys/agpio.h>
53
54 #include <sys/bus.h>
55
56 #include "agp_intel.h"
57
58 #ifdef AGP_DEBUG
59 #define DPRINTF(sc, fmt, ...) \
60 device_printf((sc)->as_dev, "%s: " fmt, __func__, ##__VA_ARGS__)
61 #else
62 #define DPRINTF(sc, fmt, ...) do {} while (0)
63 #endif
64
65 struct agp_softc *agp_i810_sc = NULL;
66
67 #define READ1(off) bus_space_read_1(isc->bst, isc->bsh, off)
68 #define READ4(off) bus_space_read_4(isc->bst, isc->bsh, off)
69 #define WRITE4(off,v) bus_space_write_4(isc->bst, isc->bsh, off, v)
70
71 #define CHIP_I810 0 /* i810/i815 */
72 #define CHIP_I830 1 /* 830M/845G */
73 #define CHIP_I855 2 /* 852GM/855GM/865G */
74 #define CHIP_I915 3 /* 915G/915GM/945G/945GM/945GME */
75 #define CHIP_I965 4 /* 965Q/965PM */
76 #define CHIP_G33 5 /* G33/Q33/Q35 */
77 #define CHIP_G4X 6 /* G45/Q45 */
78 #define CHIP_PINEVIEW 7 /* Pineview */
79
80 /* XXX hack, see below */
81 static bus_addr_t agp_i810_vga_regbase;
82 static bus_size_t agp_i810_vga_regsize;
83 static bus_space_tag_t agp_i810_vga_bst;
84 static bus_space_handle_t agp_i810_vga_bsh;
85
86 static u_int32_t agp_i810_get_aperture(struct agp_softc *);
87 static int agp_i810_set_aperture(struct agp_softc *, u_int32_t);
88 static int agp_i810_bind_page(struct agp_softc *, off_t, bus_addr_t);
89 static int agp_i810_unbind_page(struct agp_softc *, off_t);
90 static void agp_i810_flush_tlb(struct agp_softc *);
91 static int agp_i810_enable(struct agp_softc *, u_int32_t mode);
92 static struct agp_memory *agp_i810_alloc_memory(struct agp_softc *, int,
93 vsize_t);
94 static int agp_i810_free_memory(struct agp_softc *, struct agp_memory *);
95 static int agp_i810_bind_memory(struct agp_softc *, struct agp_memory *,
96 off_t);
97 static int agp_i810_bind_memory_dcache(struct agp_softc *, struct agp_memory *,
98 off_t);
99 static int agp_i810_bind_memory_hwcursor(struct agp_softc *,
100 struct agp_memory *, off_t);
101 static int agp_i810_unbind_memory(struct agp_softc *, struct agp_memory *);
102
103 static bool agp_i810_resume(device_t, const pmf_qual_t *);
104 static int agp_i810_init(struct agp_softc *);
105
106 static int agp_i810_setup_chipset_flush_page(struct agp_softc *);
107 static void agp_i810_teardown_chipset_flush_page(struct agp_softc *);
108 static int agp_i810_init(struct agp_softc *);
109
110 static struct agp_methods agp_i810_methods = {
111 agp_i810_get_aperture,
112 agp_i810_set_aperture,
113 agp_i810_bind_page,
114 agp_i810_unbind_page,
115 agp_i810_flush_tlb,
116 agp_i810_enable,
117 agp_i810_alloc_memory,
118 agp_i810_free_memory,
119 agp_i810_bind_memory,
120 agp_i810_unbind_memory,
121 };
122
123 int
agp_i810_write_gtt_entry(struct agp_i810_softc * isc,off_t off,bus_addr_t addr,int flags)124 agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off,
125 bus_addr_t addr, int flags)
126 {
127 u_int32_t pte;
128
129 /*
130 * Bits 11:4 (physical start address extension) should be zero.
131 * Flag bits 3:0 should be zero too.
132 *
133 * XXX This should be a kassert -- no reason for this routine
134 * to allow failure.
135 */
136 if ((addr & 0xfff) != 0)
137 return EINVAL;
138 KASSERT(flags == (flags & 0x7));
139
140 pte = (u_int32_t)addr;
141 /*
142 * We need to massage the pte if bus_addr_t is wider than 32 bits.
143 * The compiler isn't smart enough, hence the casts to uintmax_t.
144 */
145 if (sizeof(bus_addr_t) > sizeof(u_int32_t)) {
146 /* 965+ can do 36-bit addressing, add in the extra bits. */
147 if (isc->chiptype == CHIP_I965 ||
148 isc->chiptype == CHIP_G33 ||
149 isc->chiptype == CHIP_PINEVIEW ||
150 isc->chiptype == CHIP_G4X) {
151 if (((uintmax_t)addr >> 36) != 0)
152 return EINVAL;
153 pte |= (addr >> 28) & 0xf0;
154 } else {
155 if (((uintmax_t)addr >> 32) != 0)
156 return EINVAL;
157 }
158 }
159
160 bus_space_write_4(isc->gtt_bst, isc->gtt_bsh,
161 4*(off >> AGP_PAGE_SHIFT), pte | flags);
162
163 return 0;
164 }
165
166 void
agp_i810_post_gtt_entry(struct agp_i810_softc * isc,off_t off)167 agp_i810_post_gtt_entry(struct agp_i810_softc *isc, off_t off)
168 {
169
170 /*
171 * See <https://bugs.freedesktop.org/show_bug.cgi?id=88191>.
172 * Out of paranoia, let's do the write barrier and posting
173 * read, because I don't have enough time or hardware to
174 * conduct conclusive tests.
175 */
176 bus_space_barrier(isc->gtt_bst, isc->gtt_bsh, 0, isc->gtt_size,
177 BUS_SPACE_BARRIER_WRITE);
178 (void)bus_space_read_4(isc->gtt_bst, isc->gtt_bsh,
179 4*(off >> AGP_PAGE_SHIFT));
180 }
181
182 static void
agp_flush_cache_ipi(void * cookie __unused)183 agp_flush_cache_ipi(void *cookie __unused)
184 {
185
186 agp_flush_cache();
187 }
188
189 void
agp_i810_chipset_flush(struct agp_i810_softc * isc)190 agp_i810_chipset_flush(struct agp_i810_softc *isc)
191 {
192 unsigned int timo = 20000; /* * 50 us = 1 s */
193
194 switch (isc->chiptype) {
195 case CHIP_I810:
196 break;
197 case CHIP_I830:
198 case CHIP_I855:
199 /*
200 * Flush all CPU caches. If we're cold, we can't run
201 * xcalls, but there should be only one CPU up, so
202 * flushing only the local CPU's cache should suffice.
203 *
204 * XXX Come to think of it, do these chipsets appear in
205 * any multi-CPU systems?
206 */
207 if (cold) {
208 agp_flush_cache();
209 } else {
210 /*
211 * Caller may hold a spin lock, so use ipi(9)
212 * rather than xcall(9) here.
213 */
214 ipi_msg_t msg = { .func = agp_flush_cache_ipi };
215 kpreempt_disable();
216 ipi_broadcast(&msg, /*skip_self*/false);
217 ipi_wait(&msg);
218 kpreempt_enable();
219 }
220 WRITE4(AGP_I830_HIC, READ4(AGP_I830_HIC) | __BIT(31));
221 while (ISSET(READ4(AGP_I830_HIC), __BIT(31))) {
222 if (timo-- == 0)
223 break;
224 DELAY(50);
225 }
226 break;
227 case CHIP_I915:
228 case CHIP_I965:
229 case CHIP_G33:
230 case CHIP_PINEVIEW:
231 case CHIP_G4X:
232 bus_space_write_4(isc->flush_bst, isc->flush_bsh, 0, 1);
233 break;
234 }
235 }
236
237 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */
238 static int
agp_i810_vgamatch(const struct pci_attach_args * pa)239 agp_i810_vgamatch(const struct pci_attach_args *pa)
240 {
241
242 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
243 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
244 return (0);
245
246 switch (PCI_PRODUCT(pa->pa_id)) {
247 case PCI_PRODUCT_INTEL_82810_GC:
248 case PCI_PRODUCT_INTEL_82810_DC100_GC:
249 case PCI_PRODUCT_INTEL_82810E_GC:
250 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH:
251 case PCI_PRODUCT_INTEL_82830MP_IV:
252 case PCI_PRODUCT_INTEL_82845G_IGD:
253 case PCI_PRODUCT_INTEL_82855GM_IGD:
254 case PCI_PRODUCT_INTEL_82865_IGD:
255 case PCI_PRODUCT_INTEL_82915G_IGD:
256 case PCI_PRODUCT_INTEL_82915GM_IGD:
257 case PCI_PRODUCT_INTEL_82945P_IGD:
258 case PCI_PRODUCT_INTEL_82945GM_IGD:
259 case PCI_PRODUCT_INTEL_82945GM_IGD_1:
260 case PCI_PRODUCT_INTEL_82945GME_IGD:
261 case PCI_PRODUCT_INTEL_E7221_IGD:
262 case PCI_PRODUCT_INTEL_82965Q_IGD:
263 case PCI_PRODUCT_INTEL_82965Q_IGD_1:
264 case PCI_PRODUCT_INTEL_82965PM_IGD:
265 case PCI_PRODUCT_INTEL_82965PM_IGD_1:
266 case PCI_PRODUCT_INTEL_82G33_IGD:
267 case PCI_PRODUCT_INTEL_82G33_IGD_1:
268 case PCI_PRODUCT_INTEL_82965G_IGD:
269 case PCI_PRODUCT_INTEL_82965G_IGD_1:
270 case PCI_PRODUCT_INTEL_82965GME_IGD:
271 case PCI_PRODUCT_INTEL_82Q35_IGD:
272 case PCI_PRODUCT_INTEL_82Q35_IGD_1:
273 case PCI_PRODUCT_INTEL_82Q33_IGD:
274 case PCI_PRODUCT_INTEL_82Q33_IGD_1:
275 case PCI_PRODUCT_INTEL_82G35_IGD:
276 case PCI_PRODUCT_INTEL_82G35_IGD_1:
277 case PCI_PRODUCT_INTEL_82946GZ_IGD:
278 case PCI_PRODUCT_INTEL_82GM45_IGD:
279 case PCI_PRODUCT_INTEL_82GM45_IGD_1:
280 case PCI_PRODUCT_INTEL_82IGD_E_IGD:
281 case PCI_PRODUCT_INTEL_82Q45_IGD:
282 case PCI_PRODUCT_INTEL_82G45_IGD:
283 case PCI_PRODUCT_INTEL_82G41_IGD:
284 case PCI_PRODUCT_INTEL_82B43_IGD:
285 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD:
286 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD:
287 case PCI_PRODUCT_INTEL_PINEVIEW_IGD:
288 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD:
289 return (1);
290 }
291
292 return (0);
293 }
294
295 static int
agp_i965_map_aperture(struct pci_attach_args * pa,struct agp_softc * sc,int reg)296 agp_i965_map_aperture(struct pci_attach_args *pa, struct agp_softc *sc, int reg)
297 {
298 /*
299 * Find the aperture. Don't map it (yet), this would
300 * eat KVA.
301 */
302 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, reg,
303 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_64BIT, &sc->as_apaddr, &sc->as_apsize,
304 &sc->as_apflags) != 0)
305 return ENXIO;
306
307 sc->as_apt = pa->pa_memt;
308
309 return 0;
310 }
311
312 int
agp_i810_attach(device_t parent,device_t self,void * aux)313 agp_i810_attach(device_t parent, device_t self, void *aux)
314 {
315 struct agp_softc *sc = device_private(self);
316 struct agp_i810_softc *isc;
317 int apbase, mmadr_bar, gtt_bar;
318 int mmadr_type, mmadr_flags;
319 bus_addr_t mmadr;
320 bus_size_t mmadr_size, gtt_off;
321 int error;
322
323 isc = malloc(sizeof *isc, M_AGP, M_WAITOK|M_ZERO);
324 sc->as_chipc = isc;
325 sc->as_methods = &agp_i810_methods;
326
327 if (pci_find_device(&isc->vga_pa, agp_i810_vgamatch) == 0) {
328 #if NAGP_INTEL > 0
329 const struct pci_attach_args *pa = aux;
330
331 switch (PCI_PRODUCT(pa->pa_id)) {
332 case PCI_PRODUCT_INTEL_82840_HB:
333 case PCI_PRODUCT_INTEL_82865_HB:
334 case PCI_PRODUCT_INTEL_82845G_DRAM:
335 case PCI_PRODUCT_INTEL_82815_FULL_HUB:
336 case PCI_PRODUCT_INTEL_82855GM_MCH:
337 free(isc, M_AGP);
338 return agp_intel_attach(parent, self, aux);
339 }
340 #endif
341 aprint_error(": can't find internal VGA"
342 " config space\n");
343 error = ENOENT;
344 goto fail1;
345 }
346
347 /* XXXfvdl */
348 sc->as_dmat = isc->vga_pa.pa_dmat;
349
350 switch (PCI_PRODUCT(isc->vga_pa.pa_id)) {
351 case PCI_PRODUCT_INTEL_82810_GC:
352 case PCI_PRODUCT_INTEL_82810_DC100_GC:
353 case PCI_PRODUCT_INTEL_82810E_GC:
354 case PCI_PRODUCT_INTEL_82815_FULL_GRAPH:
355 isc->chiptype = CHIP_I810;
356 aprint_normal(": i810-family chipset\n");
357 break;
358 case PCI_PRODUCT_INTEL_82830MP_IV:
359 case PCI_PRODUCT_INTEL_82845G_IGD:
360 isc->chiptype = CHIP_I830;
361 aprint_normal(": i830-family chipset\n");
362 break;
363 case PCI_PRODUCT_INTEL_82855GM_IGD:
364 case PCI_PRODUCT_INTEL_82865_IGD:
365 isc->chiptype = CHIP_I855;
366 aprint_normal(": i855-family chipset\n");
367 break;
368 case PCI_PRODUCT_INTEL_82915G_IGD:
369 case PCI_PRODUCT_INTEL_82915GM_IGD:
370 case PCI_PRODUCT_INTEL_82945P_IGD:
371 case PCI_PRODUCT_INTEL_82945GM_IGD:
372 case PCI_PRODUCT_INTEL_82945GM_IGD_1:
373 case PCI_PRODUCT_INTEL_82945GME_IGD:
374 case PCI_PRODUCT_INTEL_E7221_IGD:
375 isc->chiptype = CHIP_I915;
376 aprint_normal(": i915-family chipset\n");
377 break;
378 case PCI_PRODUCT_INTEL_82965Q_IGD:
379 case PCI_PRODUCT_INTEL_82965Q_IGD_1:
380 case PCI_PRODUCT_INTEL_82965PM_IGD:
381 case PCI_PRODUCT_INTEL_82965PM_IGD_1:
382 case PCI_PRODUCT_INTEL_82965G_IGD:
383 case PCI_PRODUCT_INTEL_82965G_IGD_1:
384 case PCI_PRODUCT_INTEL_82965GME_IGD:
385 case PCI_PRODUCT_INTEL_82946GZ_IGD:
386 case PCI_PRODUCT_INTEL_82G35_IGD:
387 case PCI_PRODUCT_INTEL_82G35_IGD_1:
388 isc->chiptype = CHIP_I965;
389 aprint_normal(": i965-family chipset\n");
390 break;
391 case PCI_PRODUCT_INTEL_82Q35_IGD:
392 case PCI_PRODUCT_INTEL_82Q35_IGD_1:
393 case PCI_PRODUCT_INTEL_82G33_IGD:
394 case PCI_PRODUCT_INTEL_82G33_IGD_1:
395 case PCI_PRODUCT_INTEL_82Q33_IGD:
396 case PCI_PRODUCT_INTEL_82Q33_IGD_1:
397 isc->chiptype = CHIP_G33;
398 aprint_normal(": G33-family chipset\n");
399 break;
400 case PCI_PRODUCT_INTEL_PINEVIEW_IGD:
401 case PCI_PRODUCT_INTEL_PINEVIEW_M_IGD:
402 isc->chiptype = CHIP_PINEVIEW;
403 aprint_normal(": Pineview chipset\n");
404 break;
405 case PCI_PRODUCT_INTEL_82GM45_IGD:
406 case PCI_PRODUCT_INTEL_82GM45_IGD_1:
407 case PCI_PRODUCT_INTEL_82IGD_E_IGD:
408 case PCI_PRODUCT_INTEL_82Q45_IGD:
409 case PCI_PRODUCT_INTEL_82G45_IGD:
410 case PCI_PRODUCT_INTEL_82G41_IGD:
411 case PCI_PRODUCT_INTEL_82B43_IGD:
412 case PCI_PRODUCT_INTEL_IRONLAKE_D_IGD:
413 case PCI_PRODUCT_INTEL_IRONLAKE_M_IGD:
414 isc->chiptype = CHIP_G4X;
415 aprint_normal(": G4X-family chipset\n");
416 break;
417 }
418 aprint_naive("\n");
419
420 /* Discriminate on the chipset to choose the relevant BARs. */
421 switch (isc->chiptype) {
422 case CHIP_I915:
423 case CHIP_G33:
424 case CHIP_PINEVIEW:
425 apbase = AGP_I915_GMADR;
426 mmadr_bar = AGP_I915_MMADR;
427 gtt_bar = AGP_I915_GTTADR;
428 gtt_off = ~(bus_size_t)0; /* XXXGCC */
429 break;
430 case CHIP_I965:
431 apbase = AGP_I965_GMADR;
432 mmadr_bar = AGP_I965_MMADR;
433 gtt_bar = 0;
434 gtt_off = AGP_I965_GTT;
435 break;
436 case CHIP_G4X:
437 apbase = AGP_I965_GMADR;
438 mmadr_bar = AGP_I965_MMADR;
439 gtt_bar = 0;
440 gtt_off = AGP_G4X_GTT;
441 break;
442 default:
443 apbase = AGP_I810_GMADR;
444 mmadr_bar = AGP_I810_MMADR;
445 gtt_bar = 0;
446 gtt_off = AGP_I810_GTT;
447 break;
448 }
449
450 /*
451 * Ensure the MMIO BAR is, in fact, a memory BAR.
452 *
453 * XXX This is required because we use pa_memt below. It is
454 * not a priori clear to me there is any other reason to
455 * require this.
456 */
457 mmadr_type = pci_mapreg_type(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag,
458 mmadr_bar);
459 if (PCI_MAPREG_TYPE(mmadr_type) != PCI_MAPREG_TYPE_MEM) {
460 aprint_error_dev(self, "non-memory device MMIO registers\n");
461 error = ENXIO;
462 goto fail1;
463 }
464
465 /*
466 * Determine the size of the MMIO registers.
467 *
468 * XXX The size of the MMIO registers we use is statically
469 * determined, as a function of the chipset, by the driver's
470 * implementation.
471 *
472 * On some chipsets, the GTT is part of the MMIO register BAR.
473 * We would like to map the GTT separately, so that we can map
474 * it prefetchable, which we can't do with the MMIO registers.
475 * Consequently, we would especially like to map a fixed size
476 * of MMIO registers, not just whatever size the BAR says.
477 *
478 * However, old drm assumes that the combined GTT/MMIO register
479 * space is a single bus space mapping, so mapping them
480 * separately breaks that. Once we rip out old drm, we can
481 * replace the pci_mapreg_info call by the chipset switch.
482 */
483 #if notyet
484 switch (isc->chiptype) {
485 case CHIP_I810:
486 case CHIP_I830:
487 case CHIP_I855:
488 case CHIP_I915:
489 case CHIP_I965:
490 case CHIP_G33:
491 case CHIP_PINEVIEW:
492 case CHIP_G4X:
493 isc->size = 512*1024;
494 break;
495 case CHIP_SANDYBRIDGE:
496 case CHIP_IVYBRIDGE:
497 case CHIP_HASWELL:
498 isc->size = 2*1024*1024;
499 break;
500 }
501 #else
502 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag,
503 mmadr_bar, mmadr_type, NULL, &isc->size, NULL))
504 isc->size = 512*1024;
505 #endif /* notyet */
506
507 /* Map (or, rather, find the address and size of) the aperture. */
508 if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X)
509 error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase);
510 else
511 error = agp_map_aperture(&isc->vga_pa, sc, apbase);
512 if (error) {
513 aprint_error_dev(self, "can't map aperture: %d\n", error);
514 goto fail1;
515 }
516
517 /* Map the memory-mapped I/O registers, or the non-GTT part. */
518 if (pci_mapreg_info(isc->vga_pa.pa_pc, isc->vga_pa.pa_tag, mmadr_bar,
519 mmadr_type, &mmadr, &mmadr_size, &mmadr_flags)) {
520 aprint_error_dev(self, "can't find MMIO registers\n");
521 error = ENXIO;
522 goto fail1;
523 }
524 if (mmadr_size < isc->size) {
525 aprint_error_dev(self, "MMIO registers too small"
526 ": %"PRIuMAX" < %"PRIuMAX"\n",
527 (uintmax_t)mmadr_size, (uintmax_t)isc->size);
528 error = ENXIO;
529 goto fail1;
530 }
531 isc->bst = isc->vga_pa.pa_memt;
532 error = bus_space_map(isc->bst, mmadr, isc->size, mmadr_flags,
533 &isc->bsh);
534 if (error) {
535 aprint_error_dev(self, "can't map MMIO registers: %d\n",
536 error);
537 error = ENXIO;
538 goto fail1;
539 }
540
541 /* Set up a chipset flush page if necessary. */
542 switch (isc->chiptype) {
543 case CHIP_I915:
544 case CHIP_I965:
545 case CHIP_G33:
546 case CHIP_PINEVIEW:
547 case CHIP_G4X:
548 error = agp_i810_setup_chipset_flush_page(sc);
549 if (error) {
550 aprint_error_dev(self,
551 "can't set up chipset flush page: %d\n", error);
552 goto fail2;
553 }
554 break;
555 }
556
557 /*
558 * XXX horrible hack to allow drm code to use our mapping
559 * of VGA chip registers
560 */
561 agp_i810_vga_regbase = mmadr;
562 agp_i810_vga_regsize = isc->size;
563 agp_i810_vga_bst = isc->bst;
564 agp_i810_vga_bsh = isc->bsh;
565
566 /* Initialize the chipset. */
567 error = agp_i810_init(sc);
568 if (error)
569 goto fail3;
570
571 /* Map the GTT, from either part of the MMIO region or its own BAR. */
572 if (gtt_bar == 0) {
573 isc->gtt_bst = isc->bst;
574 if ((mmadr_size - gtt_off) < isc->gtt_size) {
575 aprint_error_dev(self, "GTTMMADR too small for GTT"
576 ": (%"PRIxMAX" - %"PRIxMAX") < %"PRIxMAX"\n",
577 (uintmax_t)mmadr_size,
578 (uintmax_t)gtt_off,
579 (uintmax_t)isc->gtt_size);
580 error = ENXIO;
581 goto fail4;
582 }
583 /*
584 * Map the GTT separately if we can, so that we can map
585 * it prefetchable, but in early models, there are MMIO
586 * registers before and after the GTT, so we can only
587 * take a subregion.
588 */
589 if (isc->size < gtt_off)
590 error = bus_space_map(isc->gtt_bst, (mmadr + gtt_off),
591 isc->gtt_size, mmadr_flags, &isc->gtt_bsh);
592 else
593 error = bus_space_subregion(isc->bst, isc->bsh,
594 gtt_off, isc->gtt_size, &isc->gtt_bsh);
595 if (error) {
596 aprint_error_dev(self, "can't map GTT: %d\n", error);
597 error = ENXIO;
598 goto fail4;
599 }
600 } else {
601 bus_size_t gtt_bar_size;
602 /*
603 * All chipsets with a separate BAR for the GTT, namely
604 * the i915 and G33 families, have 32-bit GTT BARs.
605 *
606 * XXX [citation needed]
607 */
608 if (pci_mapreg_map(&isc->vga_pa, gtt_bar, PCI_MAPREG_TYPE_MEM,
609 0,
610 &isc->gtt_bst, &isc->gtt_bsh, NULL, >t_bar_size)) {
611 aprint_error_dev(self, "can't map GTT\n");
612 error = ENXIO;
613 goto fail4;
614 }
615 if (gtt_bar_size != isc->gtt_size) {
616 aprint_error_dev(self,
617 "BAR size %"PRIxMAX
618 " mismatches detected GTT size %"PRIxMAX
619 "; trusting BAR\n",
620 (uintmax_t)gtt_bar_size,
621 (uintmax_t)isc->gtt_size);
622 isc->gtt_size = gtt_bar_size;
623 }
624 }
625
626 /* Power management. (XXX Nothing to save on suspend? Fishy...) */
627 if (!pmf_device_register(self, NULL, agp_i810_resume))
628 aprint_error_dev(self, "can't establish power handler\n");
629
630 /* Match the generic AGP code's autoconf output format. */
631 aprint_normal("%s", device_xname(self));
632
633 /* Success! */
634 return 0;
635
636 fail5: __unused
637 pmf_device_deregister(self);
638 if ((gtt_bar != 0) || (isc->size < gtt_off))
639 bus_space_unmap(isc->gtt_bst, isc->gtt_bsh, isc->gtt_size);
640 isc->gtt_size = 0;
641 fail4:
642 #if notyet
643 agp_i810_fini(sc);
644 #endif
645 fail3: switch (isc->chiptype) {
646 case CHIP_I915:
647 case CHIP_I965:
648 case CHIP_G33:
649 case CHIP_PINEVIEW:
650 case CHIP_G4X:
651 agp_i810_teardown_chipset_flush_page(sc);
652 break;
653 }
654 fail2: bus_space_unmap(isc->bst, isc->bsh, isc->size);
655 isc->size = 0;
656 fail1: free(isc, M_AGP);
657 sc->as_chipc = NULL;
658 agp_generic_detach(sc);
659 KASSERT(error);
660 return error;
661 }
662
663 /*
664 * Skip pages reserved by the BIOS. Notably, skip 0xa0000-0xfffff,
665 * which includes the video BIOS at 0xc0000-0xdffff which the display
666 * drivers need for video mode detection.
667 *
668 * XXX Is there an MI name for this, or a conventional x86 name? Or
669 * should we really use bus_dma instead?
670 */
671 #define PCIBIOS_MIN_MEM 0x100000
672
673 static int
agp_i810_setup_chipset_flush_page(struct agp_softc * sc)674 agp_i810_setup_chipset_flush_page(struct agp_softc *sc)
675 {
676 struct agp_i810_softc *const isc = sc->as_chipc;
677 const pci_chipset_tag_t pc = sc->as_pc;
678 const pcitag_t tag = sc->as_tag;
679 pcireg_t lo, hi;
680 bus_addr_t addr, minaddr, maxaddr;
681 int error;
682
683 /* We always use memory-mapped I/O. */
684 isc->flush_bst = isc->vga_pa.pa_memt;
685
686 /* No page allocated yet. */
687 isc->flush_addr = 0;
688
689 /* Read the PCI config register: 4-byte on gen3, 8-byte on gen>=4. */
690 if (isc->chiptype == CHIP_I915) {
691 addr = pci_conf_read(pc, tag, AGP_I915_IFPADDR);
692 minaddr = PCIBIOS_MIN_MEM;
693 maxaddr = UINT32_MAX;
694 } else {
695 hi = pci_conf_read(pc, tag, AGP_I965_IFPADDR+4);
696 lo = pci_conf_read(pc, tag, AGP_I965_IFPADDR);
697 /*
698 * Convert to uint64_t, rather than bus_addr_t which
699 * may be 32-bit, to avoid undefined behaviour with a
700 * too-wide shift. Since the BIOS doesn't know whether
701 * the OS will run 64-bit or with PAE, it ought to
702 * configure at most a 32-bit physical address, so
703 * let's print a warning in case that happens.
704 */
705 addr = ((uint64_t)hi << 32) | lo;
706 if (hi) {
707 aprint_error_dev(sc->as_dev,
708 "BIOS configured >32-bit flush page address"
709 ": %"PRIx64"\n", ((uint64_t)hi << 32) | lo);
710 #if __i386__ && !PAE
711 return EIO;
712 #endif
713 }
714 minaddr = PCIBIOS_MIN_MEM;
715 maxaddr = MIN(UINT64_MAX, ~(bus_addr_t)0);
716 }
717
718 /* Allocate or map a pre-allocated a page for it. */
719 if (ISSET(addr, 1)) {
720 /* BIOS allocated it for us. Use that. */
721 error = bus_space_map(isc->flush_bst, addr & ~1, PAGE_SIZE, 0,
722 &isc->flush_bsh);
723 if (error)
724 return error;
725 } else {
726 /* None allocated. Allocate one. */
727 error = bus_space_alloc(isc->flush_bst, minaddr, maxaddr,
728 PAGE_SIZE, PAGE_SIZE, 0, 0,
729 &isc->flush_addr, &isc->flush_bsh);
730 if (error)
731 return error;
732 KASSERT(isc->flush_addr != 0);
733 /* Write it into the PCI config register. */
734 addr = isc->flush_addr | 1;
735 if (isc->chiptype == CHIP_I915) {
736 pci_conf_write(pc, tag, AGP_I915_IFPADDR, addr);
737 } else {
738 hi = __SHIFTOUT(addr, __BITS(63, 32));
739 lo = __SHIFTOUT(addr, __BITS(31, 0));
740 pci_conf_write(pc, tag, AGP_I965_IFPADDR+4, hi);
741 pci_conf_write(pc, tag, AGP_I965_IFPADDR, lo);
742 }
743 }
744
745 /* Success! */
746 return 0;
747 }
748
749 static void
agp_i810_teardown_chipset_flush_page(struct agp_softc * sc)750 agp_i810_teardown_chipset_flush_page(struct agp_softc *sc)
751 {
752 struct agp_i810_softc *const isc = sc->as_chipc;
753
754 if (isc->flush_addr) {
755 /* If we allocated a page, clear it. */
756 if (isc->chiptype == CHIP_I915) {
757 pci_conf_write(sc->as_pc, sc->as_tag, AGP_I915_IFPADDR,
758 0);
759 } else {
760 pci_conf_write(sc->as_pc, sc->as_tag,
761 AGP_I965_IFPADDR, 0);
762 pci_conf_write(sc->as_pc, sc->as_tag,
763 AGP_I965_IFPADDR + 4, 0);
764 }
765 isc->flush_addr = 0;
766 bus_space_free(isc->flush_bst, isc->flush_bsh, PAGE_SIZE);
767 } else {
768 /* Otherwise, just unmap the pre-allocated page. */
769 bus_space_unmap(isc->flush_bst, isc->flush_bsh, PAGE_SIZE);
770 }
771 }
772
773 /*
774 * XXX horrible hack to allow drm code to use our mapping
775 * of VGA chip registers
776 */
777 int
agp_i810_borrow(bus_addr_t base,bus_size_t size,bus_space_handle_t * hdlp)778 agp_i810_borrow(bus_addr_t base, bus_size_t size, bus_space_handle_t *hdlp)
779 {
780
781 if (agp_i810_vga_regbase == 0)
782 return 0;
783 if (base < agp_i810_vga_regbase)
784 return 0;
785 if (agp_i810_vga_regsize < size)
786 return 0;
787 if ((base - agp_i810_vga_regbase) > (agp_i810_vga_regsize - size))
788 return 0;
789 if (bus_space_subregion(agp_i810_vga_bst, agp_i810_vga_bsh,
790 (base - agp_i810_vga_regbase), (agp_i810_vga_regsize - size),
791 hdlp))
792 return 0;
793 return 1;
794 }
795
796 static int
agp_i810_init(struct agp_softc * sc)797 agp_i810_init(struct agp_softc *sc)
798 {
799 struct agp_i810_softc *isc;
800 int error;
801
802 isc = sc->as_chipc;
803
804 if (isc->chiptype == CHIP_I810) {
805 struct agp_gatt *gatt;
806 void *virtual;
807 int dummyseg;
808
809 /* Some i810s have on-chip memory called dcache */
810 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED)
811 isc->dcache_size = 4 * 1024 * 1024;
812 else
813 isc->dcache_size = 0;
814
815 /* According to the specs the gatt on the i810 must be 64k */
816 isc->gtt_size = 64 * 1024;
817 gatt = malloc(sizeof(*gatt), M_AGP, M_WAITOK);
818 gatt->ag_entries = isc->gtt_size / sizeof(uint32_t);
819 error = agp_alloc_dmamem(sc->as_dmat, isc->gtt_size,
820 0, &gatt->ag_dmamap, &virtual, &gatt->ag_physical,
821 &gatt->ag_dmaseg, 1, &dummyseg);
822 if (error) {
823 aprint_error_dev(sc->as_dev,
824 "can't allocate memory for GTT: %d\n", error);
825 free(gatt, M_AGP);
826 goto fail0;
827 }
828
829 gatt->ag_virtual = (uint32_t *)virtual;
830 gatt->ag_size = gatt->ag_entries * sizeof(uint32_t);
831 memset(gatt->ag_virtual, 0, gatt->ag_size);
832 agp_flush_cache();
833
834 /* Install the GATT. */
835 isc->pgtblctl = gatt->ag_physical | 1;
836 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
837 isc->gatt = gatt;
838 } else if (isc->chiptype == CHIP_I830) {
839 /* The i830 automatically initializes the 128k gatt on boot. */
840 /* XXX [citation needed] */
841 pcireg_t reg;
842 u_int16_t gcc1;
843
844 isc->gtt_size = 128 * 1024;
845
846 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
847 gcc1 = (u_int16_t)(reg >> 16);
848 switch (gcc1 & AGP_I830_GCC1_GMS) {
849 case AGP_I830_GCC1_GMS_STOLEN_512:
850 isc->stolen = (512 - 132) * 1024 / 4096;
851 break;
852 case AGP_I830_GCC1_GMS_STOLEN_1024:
853 isc->stolen = (1024 - 132) * 1024 / 4096;
854 break;
855 case AGP_I830_GCC1_GMS_STOLEN_8192:
856 isc->stolen = (8192 - 132) * 1024 / 4096;
857 break;
858 default:
859 isc->stolen = 0;
860 aprint_error_dev(sc->as_dev,
861 "unknown memory configuration, disabling\n");
862 error = ENXIO;
863 goto fail0;
864 }
865
866 if (isc->stolen > 0) {
867 aprint_normal_dev(sc->as_dev,
868 "detected %dk stolen memory\n",
869 isc->stolen * 4);
870 }
871
872 /* GATT address is already in there, make sure it's enabled */
873 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL);
874 isc->pgtblctl |= 1;
875 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
876 } else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 ||
877 isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 ||
878 isc->chiptype == CHIP_PINEVIEW ||
879 isc->chiptype == CHIP_G4X) {
880 pcireg_t reg;
881 u_int32_t gtt_size, stolen; /* XXX kilobytes */
882 u_int16_t gcc1;
883
884 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1);
885 gcc1 = (u_int16_t)(reg >> 16);
886
887 isc->pgtblctl = READ4(AGP_I810_PGTBL_CTL);
888
889 /* Stolen memory is set up at the beginning of the aperture by
890 * the BIOS, consisting of the GATT followed by 4kb for the
891 * BIOS display.
892 */
893 switch (isc->chiptype) {
894 case CHIP_I855:
895 gtt_size = 128;
896 break;
897 case CHIP_I915:
898 gtt_size = 256;
899 break;
900 case CHIP_I965:
901 switch (isc->pgtblctl & AGP_I810_PGTBL_SIZE_MASK) {
902 case AGP_I810_PGTBL_SIZE_128KB:
903 case AGP_I810_PGTBL_SIZE_512KB:
904 gtt_size = 512;
905 break;
906 case AGP_I965_PGTBL_SIZE_1MB:
907 gtt_size = 1024;
908 break;
909 case AGP_I965_PGTBL_SIZE_2MB:
910 gtt_size = 2048;
911 break;
912 case AGP_I965_PGTBL_SIZE_1_5MB:
913 gtt_size = 1024 + 512;
914 break;
915 default:
916 aprint_error_dev(sc->as_dev,
917 "bad PGTBL size\n");
918 error = ENXIO;
919 goto fail0;
920 }
921 break;
922 case CHIP_G33:
923 switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) {
924 case AGP_G33_PGTBL_SIZE_1M:
925 gtt_size = 1024;
926 break;
927 case AGP_G33_PGTBL_SIZE_2M:
928 gtt_size = 2048;
929 break;
930 default:
931 aprint_error_dev(sc->as_dev,
932 "bad PGTBL size\n");
933 error = ENXIO;
934 goto fail0;
935 }
936 break;
937 case CHIP_PINEVIEW:
938 switch (gcc1 & AGP_PINEVIEW_PGTBL_SIZE_MASK) {
939 case AGP_PINEVIEW_PGTBL_SIZE_1M:
940 gtt_size = 1024;
941 break;
942 default:
943 aprint_error_dev(sc->as_dev,
944 "bad PGTBL size\n");
945 error = ENXIO;
946 goto fail0;
947 }
948 break;
949 case CHIP_G4X:
950 switch (isc->pgtblctl & AGP_G4X_PGTBL_SIZE_MASK) {
951 case AGP_G4X_PGTBL_SIZE_512K:
952 gtt_size = 512;
953 break;
954 case AGP_G4X_PGTBL_SIZE_256K:
955 gtt_size = 256;
956 break;
957 case AGP_G4X_PGTBL_SIZE_128K:
958 gtt_size = 128;
959 break;
960 case AGP_G4X_PGTBL_SIZE_1M:
961 gtt_size = 1*1024;
962 break;
963 case AGP_G4X_PGTBL_SIZE_2M:
964 gtt_size = 2*1024;
965 break;
966 case AGP_G4X_PGTBL_SIZE_1_5M:
967 gtt_size = 1*1024 + 512;
968 break;
969 default:
970 aprint_error_dev(sc->as_dev,
971 "bad PGTBL size\n");
972 error = ENXIO;
973 goto fail0;
974 }
975 break;
976 default:
977 panic("impossible chiptype %d", isc->chiptype);
978 }
979
980 /*
981 * XXX If I'm reading the datasheets right, this stolen
982 * memory detection logic is totally wrong.
983 */
984 switch (gcc1 & AGP_I855_GCC1_GMS) {
985 case AGP_I855_GCC1_GMS_STOLEN_1M:
986 stolen = 1024;
987 break;
988 case AGP_I855_GCC1_GMS_STOLEN_4M:
989 stolen = 4 * 1024;
990 break;
991 case AGP_I855_GCC1_GMS_STOLEN_8M:
992 stolen = 8 * 1024;
993 break;
994 case AGP_I855_GCC1_GMS_STOLEN_16M:
995 stolen = 16 * 1024;
996 break;
997 case AGP_I855_GCC1_GMS_STOLEN_32M:
998 stolen = 32 * 1024;
999 break;
1000 case AGP_I915_GCC1_GMS_STOLEN_48M:
1001 stolen = 48 * 1024;
1002 break;
1003 case AGP_I915_GCC1_GMS_STOLEN_64M:
1004 stolen = 64 * 1024;
1005 break;
1006 case AGP_G33_GCC1_GMS_STOLEN_128M:
1007 stolen = 128 * 1024;
1008 break;
1009 case AGP_G33_GCC1_GMS_STOLEN_256M:
1010 stolen = 256 * 1024;
1011 break;
1012 case AGP_G4X_GCC1_GMS_STOLEN_96M:
1013 stolen = 96 * 1024;
1014 break;
1015 case AGP_G4X_GCC1_GMS_STOLEN_160M:
1016 stolen = 160 * 1024;
1017 break;
1018 case AGP_G4X_GCC1_GMS_STOLEN_224M:
1019 stolen = 224 * 1024;
1020 break;
1021 case AGP_G4X_GCC1_GMS_STOLEN_352M:
1022 stolen = 352 * 1024;
1023 break;
1024 default:
1025 aprint_error_dev(sc->as_dev,
1026 "unknown memory configuration, disabling\n");
1027 error = ENXIO;
1028 goto fail0;
1029 }
1030
1031 switch (gcc1 & AGP_I855_GCC1_GMS) {
1032 case AGP_I915_GCC1_GMS_STOLEN_48M:
1033 case AGP_I915_GCC1_GMS_STOLEN_64M:
1034 if (isc->chiptype != CHIP_I915 &&
1035 isc->chiptype != CHIP_I965 &&
1036 isc->chiptype != CHIP_G33 &&
1037 isc->chiptype != CHIP_PINEVIEW &&
1038 isc->chiptype != CHIP_G4X)
1039 stolen = 0;
1040 break;
1041 case AGP_G33_GCC1_GMS_STOLEN_128M:
1042 case AGP_G33_GCC1_GMS_STOLEN_256M:
1043 if (isc->chiptype != CHIP_I965 &&
1044 isc->chiptype != CHIP_G33 &&
1045 isc->chiptype != CHIP_PINEVIEW &&
1046 isc->chiptype != CHIP_G4X)
1047 stolen = 0;
1048 break;
1049 case AGP_G4X_GCC1_GMS_STOLEN_96M:
1050 case AGP_G4X_GCC1_GMS_STOLEN_160M:
1051 case AGP_G4X_GCC1_GMS_STOLEN_224M:
1052 case AGP_G4X_GCC1_GMS_STOLEN_352M:
1053 if (isc->chiptype != CHIP_I965 &&
1054 isc->chiptype != CHIP_G4X)
1055 stolen = 0;
1056 break;
1057 }
1058
1059 isc->gtt_size = gtt_size * 1024;
1060
1061 /* BIOS space */
1062 /* XXX [citation needed] */
1063 gtt_size += 4;
1064
1065 /* XXX [citation needed] for this subtraction */
1066 isc->stolen = (stolen - gtt_size) * 1024 / 4096;
1067
1068 if (isc->stolen > 0) {
1069 aprint_normal_dev(sc->as_dev,
1070 "detected %dk stolen memory\n",
1071 isc->stolen * 4);
1072 }
1073
1074 /* GATT address is already in there, make sure it's enabled */
1075 isc->pgtblctl |= 1;
1076 WRITE4(AGP_I810_PGTBL_CTL, isc->pgtblctl);
1077 }
1078
1079 /*
1080 * Make sure the chipset can see everything.
1081 */
1082 agp_flush_cache();
1083
1084 /*
1085 * Publish what we found for kludgey drivers (I'm looking at
1086 * you, drm).
1087 */
1088 if (agp_i810_sc == NULL)
1089 agp_i810_sc = sc;
1090 else
1091 aprint_error_dev(sc->as_dev, "agp already attached\n");
1092
1093 /* Success! */
1094 return 0;
1095
1096 fail0: KASSERT(error);
1097 return error;
1098 }
1099
1100 #if 0
1101 static int
1102 agp_i810_detach(struct agp_softc *sc)
1103 {
1104 int error;
1105 struct agp_i810_softc *isc = sc->as_chipc;
1106
1107 error = agp_generic_detach(sc);
1108 if (error)
1109 return error;
1110
1111 switch (isc->chiptype) {
1112 case CHIP_I915:
1113 case CHIP_I965:
1114 case CHIP_G33:
1115 case CHIP_PINEVIEW:
1116 case CHIP_G4X:
1117 agp_i810_teardown_chipset_flush_page(sc);
1118 break;
1119 }
1120
1121 /* Clear the GATT base. */
1122 if (sc->chiptype == CHIP_I810) {
1123 WRITE4(AGP_I810_PGTBL_CTL, 0);
1124 } else {
1125 unsigned int pgtblctl;
1126 pgtblctl = READ4(AGP_I810_PGTBL_CTL);
1127 pgtblctl &= ~1;
1128 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
1129 }
1130
1131 if (sc->chiptype == CHIP_I810) {
1132 agp_free_dmamem(sc->as_dmat, gatt->ag_size, gatt->ag_dmamap,
1133 (void *)gatt->ag_virtual, &gatt->ag_dmaseg, 1);
1134 free(isc->gatt, M_AGP);
1135 }
1136
1137 return 0;
1138 }
1139 #endif
1140
1141 static u_int32_t
agp_i810_get_aperture(struct agp_softc * sc)1142 agp_i810_get_aperture(struct agp_softc *sc)
1143 {
1144 struct agp_i810_softc *isc = sc->as_chipc;
1145 pcireg_t reg;
1146 u_int32_t size;
1147 u_int16_t miscc, gcc1;
1148
1149 size = 0;
1150
1151 switch (isc->chiptype) {
1152 case CHIP_I810:
1153 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM);
1154 miscc = (u_int16_t)(reg >> 16);
1155 if ((miscc & AGP_I810_MISCC_WINSIZE) ==
1156 AGP_I810_MISCC_WINSIZE_32)
1157 size = 32 * 1024 * 1024;
1158 else
1159 size = 64 * 1024 * 1024;
1160 break;
1161 case CHIP_I830:
1162 reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
1163 gcc1 = (u_int16_t)(reg >> 16);
1164 if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
1165 size = 64 * 1024 * 1024;
1166 else
1167 size = 128 * 1024 * 1024;
1168 break;
1169 case CHIP_I855:
1170 size = 128 * 1024 * 1024;
1171 break;
1172 case CHIP_I915:
1173 case CHIP_G33:
1174 case CHIP_PINEVIEW:
1175 case CHIP_G4X:
1176 size = sc->as_apsize;
1177 break;
1178 case CHIP_I965:
1179 size = 512 * 1024 * 1024;
1180 break;
1181 default:
1182 aprint_error(": Unknown chipset\n");
1183 }
1184
1185 return size;
1186 }
1187
1188 static int
agp_i810_set_aperture(struct agp_softc * sc __unused,uint32_t aperture __unused)1189 agp_i810_set_aperture(struct agp_softc *sc __unused,
1190 uint32_t aperture __unused)
1191 {
1192
1193 return ENOSYS;
1194 }
1195
1196 static int
agp_i810_bind_page(struct agp_softc * sc,off_t offset,bus_addr_t physical)1197 agp_i810_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
1198 {
1199 struct agp_i810_softc *isc = sc->as_chipc;
1200
1201 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT)) {
1202 DPRINTF(sc, "failed"
1203 ": offset 0x%"PRIxMAX", shift %u, entries %"PRIuMAX"\n",
1204 (uintmax_t)offset,
1205 (unsigned)AGP_PAGE_SHIFT,
1206 (uintmax_t)isc->gtt_size/4);
1207 return EINVAL;
1208 }
1209
1210 if (isc->chiptype != CHIP_I810) {
1211 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) {
1212 DPRINTF(sc, "trying to bind into stolen memory\n");
1213 return EINVAL;
1214 }
1215 }
1216
1217 return agp_i810_write_gtt_entry(isc, offset, physical,
1218 AGP_I810_GTT_VALID);
1219 }
1220
1221 static int
agp_i810_unbind_page(struct agp_softc * sc,off_t offset)1222 agp_i810_unbind_page(struct agp_softc *sc, off_t offset)
1223 {
1224 struct agp_i810_softc *isc = sc->as_chipc;
1225
1226 if (offset < 0 || offset >= ((isc->gtt_size/4) << AGP_PAGE_SHIFT))
1227 return EINVAL;
1228
1229 if (isc->chiptype != CHIP_I810 ) {
1230 if ((offset >> AGP_PAGE_SHIFT) < isc->stolen) {
1231 DPRINTF(sc, "trying to unbind from stolen memory\n");
1232 return EINVAL;
1233 }
1234 }
1235
1236 return agp_i810_write_gtt_entry(isc, offset, 0, 0);
1237 }
1238
1239 /*
1240 * Writing via memory mapped registers already flushes all TLBs.
1241 */
1242 static void
agp_i810_flush_tlb(struct agp_softc * sc)1243 agp_i810_flush_tlb(struct agp_softc *sc)
1244 {
1245 }
1246
1247 static int
agp_i810_enable(struct agp_softc * sc,u_int32_t mode)1248 agp_i810_enable(struct agp_softc *sc, u_int32_t mode)
1249 {
1250
1251 return 0;
1252 }
1253
1254 #define AGP_I810_MEMTYPE_MAIN 0
1255 #define AGP_I810_MEMTYPE_DCACHE 1
1256 #define AGP_I810_MEMTYPE_HWCURSOR 2
1257
1258 static struct agp_memory *
agp_i810_alloc_memory(struct agp_softc * sc,int type,vsize_t size)1259 agp_i810_alloc_memory(struct agp_softc *sc, int type, vsize_t size)
1260 {
1261 struct agp_i810_softc *isc = sc->as_chipc;
1262 struct agp_memory *mem;
1263 int error;
1264
1265 DPRINTF(sc, "AGP: alloc(%d, 0x%"PRIxMAX")\n", type, (uintmax_t)size);
1266
1267 if (size <= 0)
1268 return NULL;
1269 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
1270 return NULL;
1271 KASSERT(sc->as_allocated <= sc->as_maxmem);
1272 if (size > (sc->as_maxmem - sc->as_allocated))
1273 return NULL;
1274 if (size > ((isc->gtt_size/4) << AGP_PAGE_SHIFT))
1275 return NULL;
1276
1277 switch (type) {
1278 case AGP_I810_MEMTYPE_MAIN:
1279 break;
1280 case AGP_I810_MEMTYPE_DCACHE:
1281 if (isc->chiptype != CHIP_I810)
1282 return NULL;
1283 if (size != isc->dcache_size)
1284 return NULL;
1285 break;
1286 case AGP_I810_MEMTYPE_HWCURSOR:
1287 if ((size != AGP_PAGE_SIZE) &&
1288 (size != AGP_PAGE_SIZE*4))
1289 return NULL;
1290 break;
1291 default:
1292 return NULL;
1293 }
1294
1295 mem = malloc(sizeof(*mem), M_AGP, M_WAITOK|M_ZERO);
1296 if (mem == NULL)
1297 goto fail0;
1298 mem->am_id = sc->as_nextid++;
1299 mem->am_size = size;
1300 mem->am_type = type;
1301
1302 switch (type) {
1303 case AGP_I810_MEMTYPE_MAIN:
1304 error = bus_dmamap_create(sc->as_dmat, size,
1305 (size >> AGP_PAGE_SHIFT) + 1, size, 0, BUS_DMA_WAITOK,
1306 &mem->am_dmamap);
1307 if (error)
1308 goto fail1;
1309 break;
1310 case AGP_I810_MEMTYPE_DCACHE:
1311 break;
1312 case AGP_I810_MEMTYPE_HWCURSOR:
1313 mem->am_dmaseg = malloc(sizeof(*mem->am_dmaseg), M_AGP,
1314 M_WAITOK);
1315 error = agp_alloc_dmamem(sc->as_dmat, size, 0, &mem->am_dmamap,
1316 &mem->am_virtual, &mem->am_physical, mem->am_dmaseg, 1,
1317 &mem->am_nseg);
1318 if (error) {
1319 free(mem->am_dmaseg, M_AGP);
1320 goto fail1;
1321 }
1322 (void)memset(mem->am_virtual, 0, size);
1323 break;
1324 default:
1325 panic("invalid agp memory type: %d", type);
1326 }
1327
1328 TAILQ_INSERT_TAIL(&sc->as_memory, mem, am_link);
1329 sc->as_allocated += size;
1330
1331 return mem;
1332
1333 fail1: free(mem, M_AGP);
1334 fail0: return NULL;
1335 }
1336
1337 static int
agp_i810_free_memory(struct agp_softc * sc,struct agp_memory * mem)1338 agp_i810_free_memory(struct agp_softc *sc, struct agp_memory *mem)
1339 {
1340
1341 if (mem->am_is_bound)
1342 return EBUSY;
1343
1344 switch (mem->am_type) {
1345 case AGP_I810_MEMTYPE_MAIN:
1346 bus_dmamap_destroy(sc->as_dmat, mem->am_dmamap);
1347 break;
1348 case AGP_I810_MEMTYPE_DCACHE:
1349 break;
1350 case AGP_I810_MEMTYPE_HWCURSOR:
1351 agp_free_dmamem(sc->as_dmat, mem->am_size, mem->am_dmamap,
1352 mem->am_virtual, mem->am_dmaseg, mem->am_nseg);
1353 free(mem->am_dmaseg, M_AGP);
1354 break;
1355 default:
1356 panic("invalid agp i810 memory type: %d", mem->am_type);
1357 }
1358
1359 sc->as_allocated -= mem->am_size;
1360 TAILQ_REMOVE(&sc->as_memory, mem, am_link);
1361 free(mem, M_AGP);
1362
1363 return 0;
1364 }
1365
1366 static int
agp_i810_bind_memory(struct agp_softc * sc,struct agp_memory * mem,off_t offset)1367 agp_i810_bind_memory(struct agp_softc *sc, struct agp_memory *mem,
1368 off_t offset)
1369 {
1370 struct agp_i810_softc *isc = sc->as_chipc;
1371 uint32_t pgtblctl;
1372 int error;
1373
1374 if (mem->am_is_bound)
1375 return EINVAL;
1376
1377 /*
1378 * XXX evil hack: the PGTBL_CTL appearently gets overwritten by the
1379 * X server for mysterious reasons which leads to crashes if we write
1380 * to the GTT through the MMIO window.
1381 * Until the issue is solved, simply restore it.
1382 */
1383 pgtblctl = bus_space_read_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL);
1384 if (pgtblctl != isc->pgtblctl) {
1385 printf("agp_i810_bind_memory: PGTBL_CTL is 0x%"PRIx32
1386 " - fixing\n", pgtblctl);
1387 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL,
1388 isc->pgtblctl);
1389 }
1390
1391 switch (mem->am_type) {
1392 case AGP_I810_MEMTYPE_MAIN:
1393 return agp_generic_bind_memory_bounded(sc, mem, offset,
1394 0, (isc->gtt_size/4) << AGP_PAGE_SHIFT);
1395 case AGP_I810_MEMTYPE_DCACHE:
1396 error = agp_i810_bind_memory_dcache(sc, mem, offset);
1397 break;
1398 case AGP_I810_MEMTYPE_HWCURSOR:
1399 error = agp_i810_bind_memory_hwcursor(sc, mem, offset);
1400 break;
1401 default:
1402 panic("invalid agp i810 memory type: %d", mem->am_type);
1403 }
1404 if (error)
1405 return error;
1406
1407 /* Success! */
1408 mem->am_is_bound = 1;
1409 return 0;
1410 }
1411
1412 static int
agp_i810_bind_memory_dcache(struct agp_softc * sc,struct agp_memory * mem,off_t offset)1413 agp_i810_bind_memory_dcache(struct agp_softc *sc, struct agp_memory *mem,
1414 off_t offset)
1415 {
1416 struct agp_i810_softc *const isc __diagused = sc->as_chipc;
1417 uint32_t i, j;
1418 int error;
1419
1420 KASSERT(isc->chiptype == CHIP_I810);
1421
1422 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0);
1423 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1424 error = agp_i810_write_gtt_entry(isc, offset + i,
1425 i, AGP_I810_GTT_VALID | AGP_I810_GTT_I810_DCACHE);
1426 if (error)
1427 goto fail0;
1428 }
1429
1430 /* Success! */
1431 mem->am_offset = offset;
1432 return 0;
1433
1434 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE)
1435 (void)agp_i810_unbind_page(sc, offset + j);
1436 return error;
1437 }
1438
1439 static int
agp_i810_bind_memory_hwcursor(struct agp_softc * sc,struct agp_memory * mem,off_t offset)1440 agp_i810_bind_memory_hwcursor(struct agp_softc *sc, struct agp_memory *mem,
1441 off_t offset)
1442 {
1443 const bus_addr_t pa = mem->am_physical;
1444 uint32_t i, j;
1445 int error;
1446
1447 KASSERT((mem->am_size & (AGP_PAGE_SIZE - 1)) == 0);
1448 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1449 error = agp_i810_bind_page(sc, offset + i, pa + i);
1450 if (error)
1451 goto fail0;
1452 }
1453
1454 /* Success! */
1455 mem->am_offset = offset;
1456 return 0;
1457
1458 fail0: for (j = 0; j < i; j += AGP_PAGE_SIZE)
1459 (void)agp_i810_unbind_page(sc, offset + j);
1460 return error;
1461 }
1462
1463 static int
agp_i810_unbind_memory(struct agp_softc * sc,struct agp_memory * mem)1464 agp_i810_unbind_memory(struct agp_softc *sc, struct agp_memory *mem)
1465 {
1466 struct agp_i810_softc *isc __diagused = sc->as_chipc;
1467 u_int32_t i;
1468
1469 if (!mem->am_is_bound)
1470 return EINVAL;
1471
1472 switch (mem->am_type) {
1473 case AGP_I810_MEMTYPE_MAIN:
1474 return agp_generic_unbind_memory(sc, mem);
1475 case AGP_I810_MEMTYPE_DCACHE:
1476 KASSERT(isc->chiptype == CHIP_I810);
1477 /* FALLTHROUGH */
1478 case AGP_I810_MEMTYPE_HWCURSOR:
1479 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
1480 (void)agp_i810_unbind_page(sc, mem->am_offset + i);
1481 mem->am_offset = 0;
1482 break;
1483 default:
1484 panic("invalid agp i810 memory type: %d", mem->am_type);
1485 }
1486
1487 mem->am_is_bound = 0;
1488 return 0;
1489 }
1490
1491 void
agp_i810_reset(struct agp_i810_softc * isc)1492 agp_i810_reset(struct agp_i810_softc *isc)
1493 {
1494
1495 /* Restore the page table control register. */
1496 bus_space_write_4(isc->bst, isc->bsh, AGP_I810_PGTBL_CTL,
1497 isc->pgtblctl);
1498
1499 agp_flush_cache();
1500 }
1501
1502 static bool
agp_i810_resume(device_t dv,const pmf_qual_t * qual)1503 agp_i810_resume(device_t dv, const pmf_qual_t *qual)
1504 {
1505 struct agp_softc *sc = device_private(dv);
1506 struct agp_i810_softc *isc = sc->as_chipc;
1507
1508 agp_i810_reset(isc);
1509
1510 return true;
1511 }
1512