1//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Haswell to support instruction 10// scheduling and other instruction cost heuristics. 11// 12// Note that we define some instructions here that are not supported by haswell, 13// but we still have to define them because KNL uses the HSW model. 14// They are currently tagged with a comment `Unsupported = 1`. 15// FIXME: Use Unsupported = 1 once KNL has its own model. 16// 17//===----------------------------------------------------------------------===// 18 19def HaswellModel : SchedMachineModel { 20 // All x86 instructions are modeled as a single micro-op, and HW can decode 4 21 // instructions per cycle. 22 let IssueWidth = 4; 23 let MicroOpBufferSize = 192; // Based on the reorder buffer. 24 let LoadLatency = 5; 25 let MispredictPenalty = 16; 26 27 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 28 let LoopMicroOpBufferSize = 50; 29 30 // This flag is set to allow the scheduler to assign a default model to 31 // unrecognized opcodes. 32 let CompleteModel = 0; 33} 34 35let SchedModel = HaswellModel in { 36 37// Haswell can issue micro-ops to 8 different ports in one cycle. 38 39// Ports 0, 1, 5, and 6 handle all computation. 40// Port 4 gets the data half of stores. Store data can be available later than 41// the store address, but since we don't model the latency of stores, we can 42// ignore that. 43// Ports 2 and 3 are identical. They handle loads and the address half of 44// stores. Port 7 can handle address calculations. 45def HWPort0 : ProcResource<1>; 46def HWPort1 : ProcResource<1>; 47def HWPort2 : ProcResource<1>; 48def HWPort3 : ProcResource<1>; 49def HWPort4 : ProcResource<1>; 50def HWPort5 : ProcResource<1>; 51def HWPort6 : ProcResource<1>; 52def HWPort7 : ProcResource<1>; 53 54// Many micro-ops are capable of issuing on multiple ports. 55def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>; 56def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; 57def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; 58def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>; 59def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; 60def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; 61def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; 62def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>; 63def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>; 64def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; 65def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; 66def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; 67 68// 60 Entry Unified Scheduler 69def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, 70 HWPort5, HWPort6, HWPort7]> { 71 let BufferSize=60; 72} 73 74// Integer division issued on port 0. 75def HWDivider : ProcResource<1>; 76// FP division and sqrt on port 0. 77def HWFPDivider : ProcResource<1>; 78 79// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 80// cycles after the memory operand. 81def : ReadAdvance<ReadAfterLd, 5>; 82 83// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 84// until 5/6/7 cycles after the memory operand. 85def : ReadAdvance<ReadAfterVecLd, 5>; 86def : ReadAdvance<ReadAfterVecXLd, 6>; 87def : ReadAdvance<ReadAfterVecYLd, 7>; 88 89def : ReadAdvance<ReadInt2Fpu, 0>; 90 91// Many SchedWrites are defined in pairs with and without a folded load. 92// Instructions with folded loads are usually micro-fused, so they only appear 93// as two micro-ops when queued in the reservation station. 94// This multiclass defines the resource usage for variants with and without 95// folded loads. 96multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW, 97 list<ProcResourceKind> ExePorts, 98 int Lat, list<int> Res = [1], int UOps = 1, 99 int LoadLat = 5> { 100 // Register variant is using a single cycle on ExePort. 101 def : WriteRes<SchedRW, ExePorts> { 102 let Latency = Lat; 103 let ResourceCycles = Res; 104 let NumMicroOps = UOps; 105 } 106 107 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 108 // the latency (default = 5). 109 def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> { 110 let Latency = !add(Lat, LoadLat); 111 let ResourceCycles = !listconcat([1], Res); 112 let NumMicroOps = !add(UOps, 1); 113 } 114} 115 116// A folded store needs a cycle on port 4 for the store data, and an extra port 117// 2/3/7 cycle to recompute the address. 118def : WriteRes<WriteRMW, [HWPort237,HWPort4]>; 119 120// Store_addr on 237. 121// Store_data on 4. 122defm : X86WriteRes<WriteStore, [HWPort237, HWPort4], 1, [1,1], 1>; 123defm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>; 124defm : X86WriteRes<WriteLoad, [HWPort23], 5, [1], 1>; 125defm : X86WriteRes<WriteMove, [HWPort0156], 1, [1], 1>; 126def : WriteRes<WriteZero, []>; 127 128// Arithmetic. 129defm : HWWriteResPair<WriteALU, [HWPort0156], 1>; 130defm : HWWriteResPair<WriteADC, [HWPort06, HWPort0156], 2, [1,1], 2>; 131 132// Integer multiplication. 133defm : HWWriteResPair<WriteIMul8, [HWPort1], 3>; 134defm : HWWriteResPair<WriteIMul16, [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>; 135defm : X86WriteRes<WriteIMul16Imm, [HWPort1,HWPort0156], 4, [1,1], 2>; 136defm : X86WriteRes<WriteIMul16ImmLd, [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>; 137defm : HWWriteResPair<WriteIMul16Reg, [HWPort1], 3>; 138defm : HWWriteResPair<WriteIMul32, [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>; 139defm : HWWriteResPair<WriteIMul32Imm, [HWPort1], 3>; 140defm : HWWriteResPair<WriteIMul32Reg, [HWPort1], 3>; 141defm : HWWriteResPair<WriteIMul64, [HWPort1,HWPort6], 4, [1,1], 2>; 142defm : HWWriteResPair<WriteIMul64Imm, [HWPort1], 3>; 143defm : HWWriteResPair<WriteIMul64Reg, [HWPort1], 3>; 144def : WriteRes<WriteIMulH, []> { let Latency = 3; } 145 146defm : X86WriteRes<WriteBSWAP32, [HWPort15], 1, [1], 1>; 147defm : X86WriteRes<WriteBSWAP64, [HWPort06, HWPort15], 2, [1,1], 2>; 148defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>; 149defm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>; 150defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>; 151 152// Integer shifts and rotates. 153defm : HWWriteResPair<WriteShift, [HWPort06], 1>; 154defm : HWWriteResPair<WriteShiftCL, [HWPort06, HWPort0156], 3, [2,1], 3>; 155defm : HWWriteResPair<WriteRotate, [HWPort06], 1, [1], 1>; 156defm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156], 3, [2,1], 3>; 157 158// SHLD/SHRD. 159defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>; 160defm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>; 161defm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>; 162defm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>; 163 164defm : HWWriteResPair<WriteJump, [HWPort06], 1>; 165defm : HWWriteResPair<WriteCRC32, [HWPort1], 3>; 166 167defm : HWWriteResPair<WriteCMOV, [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move. 168defm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move. 169def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc. 170def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> { 171 let Latency = 2; 172 let NumMicroOps = 3; 173} 174 175defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>; 176defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>; 177defm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>; 178defm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>; 179defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>; 180defm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 3>; 181//defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>; 182 183// This is for simple LEAs with one or two input operands. 184// The complex ones can only execute on port 1, and they require two cycles on 185// the port to read all inputs. We don't model that. 186def : WriteRes<WriteLEA, [HWPort15]>; 187 188// Bit counts. 189defm : HWWriteResPair<WriteBSF, [HWPort1], 3>; 190defm : HWWriteResPair<WriteBSR, [HWPort1], 3>; 191defm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>; 192defm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>; 193defm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>; 194 195// BMI1 BEXTR/BLS, BMI2 BZHI 196defm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>; 197defm : HWWriteResPair<WriteBLS, [HWPort15], 1>; 198defm : HWWriteResPair<WriteBZHI, [HWPort15], 1>; 199 200// TODO: Why isn't the HWDivider used? 201defm : X86WriteRes<WriteDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 22, [], 9>; 202defm : X86WriteRes<WriteDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 203defm : X86WriteRes<WriteDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 204defm : X86WriteRes<WriteDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 205defm : X86WriteRes<WriteDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 206defm : X86WriteRes<WriteDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 207defm : X86WriteRes<WriteDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 208defm : X86WriteRes<WriteDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 209 210defm : X86WriteRes<WriteIDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 23, [], 9>; 211defm : X86WriteRes<WriteIDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 212defm : X86WriteRes<WriteIDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 213defm : X86WriteRes<WriteIDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 214defm : X86WriteRes<WriteIDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 215defm : X86WriteRes<WriteIDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 216defm : X86WriteRes<WriteIDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 217defm : X86WriteRes<WriteIDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 218 219// Scalar and vector floating point. 220defm : X86WriteRes<WriteFLD0, [HWPort01], 1, [1], 1>; 221defm : X86WriteRes<WriteFLD1, [HWPort01], 1, [2], 2>; 222defm : X86WriteRes<WriteFLDC, [HWPort01], 1, [2], 2>; 223defm : X86WriteRes<WriteFLoad, [HWPort23], 5, [1], 1>; 224defm : X86WriteRes<WriteFLoadX, [HWPort23], 6, [1], 1>; 225defm : X86WriteRes<WriteFLoadY, [HWPort23], 7, [1], 1>; 226defm : X86WriteRes<WriteFMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>; 227defm : X86WriteRes<WriteFMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>; 228defm : X86WriteRes<WriteFStore, [HWPort237,HWPort4], 1, [1,1], 2>; 229defm : X86WriteRes<WriteFStoreX, [HWPort237,HWPort4], 1, [1,1], 2>; 230defm : X86WriteRes<WriteFStoreY, [HWPort237,HWPort4], 1, [1,1], 2>; 231defm : X86WriteRes<WriteFStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>; 232defm : X86WriteRes<WriteFStoreNTX, [HWPort237,HWPort4], 1, [1,1], 2>; 233defm : X86WriteRes<WriteFStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>; 234 235defm : X86WriteRes<WriteFMaskedStore32, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 236defm : X86WriteRes<WriteFMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 237defm : X86WriteRes<WriteFMaskedStore64, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 238defm : X86WriteRes<WriteFMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 239 240defm : X86WriteRes<WriteFMove, [HWPort5], 1, [1], 1>; 241defm : X86WriteRes<WriteFMoveX, [HWPort5], 1, [1], 1>; 242defm : X86WriteRes<WriteFMoveY, [HWPort5], 1, [1], 1>; 243defm : X86WriteRes<WriteEMMS, [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>; 244 245defm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 5>; 246defm : HWWriteResPair<WriteFAddX, [HWPort1], 3, [1], 1, 6>; 247defm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>; 248defm : HWWriteResPair<WriteFAddZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 249defm : HWWriteResPair<WriteFAdd64, [HWPort1], 3, [1], 1, 5>; 250defm : HWWriteResPair<WriteFAdd64X, [HWPort1], 3, [1], 1, 6>; 251defm : HWWriteResPair<WriteFAdd64Y, [HWPort1], 3, [1], 1, 7>; 252defm : HWWriteResPair<WriteFAdd64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 253 254defm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 5>; 255defm : HWWriteResPair<WriteFCmpX, [HWPort1], 3, [1], 1, 6>; 256defm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>; 257defm : HWWriteResPair<WriteFCmpZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 258defm : HWWriteResPair<WriteFCmp64, [HWPort1], 3, [1], 1, 5>; 259defm : HWWriteResPair<WriteFCmp64X, [HWPort1], 3, [1], 1, 6>; 260defm : HWWriteResPair<WriteFCmp64Y, [HWPort1], 3, [1], 1, 7>; 261defm : HWWriteResPair<WriteFCmp64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 262 263defm : HWWriteResPair<WriteFCom, [HWPort1], 3>; 264defm : HWWriteResPair<WriteFComX, [HWPort1], 3>; 265 266defm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 5>; 267defm : HWWriteResPair<WriteFMulX, [HWPort01], 5, [1], 1, 6>; 268defm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>; 269defm : HWWriteResPair<WriteFMulZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 270defm : HWWriteResPair<WriteFMul64, [HWPort01], 5, [1], 1, 5>; 271defm : HWWriteResPair<WriteFMul64X, [HWPort01], 5, [1], 1, 6>; 272defm : HWWriteResPair<WriteFMul64Y, [HWPort01], 5, [1], 1, 7>; 273defm : HWWriteResPair<WriteFMul64Z, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 274 275defm : HWWriteResPair<WriteFDiv, [HWPort0,HWFPDivider], 13, [1,7], 1, 5>; 276defm : HWWriteResPair<WriteFDivX, [HWPort0,HWFPDivider], 13, [1,7], 1, 6>; 277defm : HWWriteResPair<WriteFDivY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; 278defm : HWWriteResPair<WriteFDivZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1 279defm : HWWriteResPair<WriteFDiv64, [HWPort0,HWFPDivider], 20, [1,14], 1, 5>; 280defm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>; 281defm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; 282defm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1 283 284defm : HWWriteResPair<WriteFRcp, [HWPort0], 5, [1], 1, 5>; 285defm : HWWriteResPair<WriteFRcpX, [HWPort0], 5, [1], 1, 6>; 286defm : HWWriteResPair<WriteFRcpY, [HWPort0,HWPort015], 11, [2,1], 3, 7>; 287defm : HWWriteResPair<WriteFRcpZ, [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1 288 289defm : HWWriteResPair<WriteFRsqrt, [HWPort0], 5, [1], 1, 5>; 290defm : HWWriteResPair<WriteFRsqrtX,[HWPort0], 5, [1], 1, 6>; 291defm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>; 292defm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1 293 294defm : HWWriteResPair<WriteFSqrt, [HWPort0,HWFPDivider], 11, [1,7], 1, 5>; 295defm : HWWriteResPair<WriteFSqrtX, [HWPort0,HWFPDivider], 11, [1,7], 1, 6>; 296defm : HWWriteResPair<WriteFSqrtY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; 297defm : HWWriteResPair<WriteFSqrtZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1 298defm : HWWriteResPair<WriteFSqrt64, [HWPort0,HWFPDivider], 16, [1,14], 1, 5>; 299defm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>; 300defm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; 301defm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1 302defm : HWWriteResPair<WriteFSqrt80, [HWPort0,HWFPDivider], 23, [1,17]>; 303 304defm : HWWriteResPair<WriteFMA, [HWPort01], 5, [1], 1, 5>; 305defm : HWWriteResPair<WriteFMAX, [HWPort01], 5, [1], 1, 6>; 306defm : HWWriteResPair<WriteFMAY, [HWPort01], 5, [1], 1, 7>; 307defm : HWWriteResPair<WriteFMAZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 308defm : HWWriteResPair<WriteDPPD, [HWPort0,HWPort1,HWPort5], 9, [1,1,1], 3, 6>; 309defm : HWWriteResPair<WriteDPPS, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 6>; 310defm : HWWriteResPair<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; 311defm : HWWriteResPair<WriteDPPSZ, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; // Unsupported = 1 312defm : HWWriteResPair<WriteFSign, [HWPort0], 1>; 313defm : X86WriteRes<WriteFRnd, [HWPort23], 6, [1], 1>; 314defm : X86WriteRes<WriteFRndY, [HWPort23], 6, [1], 1>; 315defm : X86WriteRes<WriteFRndZ, [HWPort23], 6, [1], 1>; // Unsupported = 1 316defm : X86WriteRes<WriteFRndLd, [HWPort1,HWPort23], 12, [2,1], 3>; 317defm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>; 318defm : X86WriteRes<WriteFRndZLd, [HWPort1,HWPort23], 13, [2,1], 3>; // Unsupported = 1 319defm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>; 320defm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>; 321defm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 322defm : HWWriteResPair<WriteFTest, [HWPort0], 1, [1], 1, 6>; 323defm : HWWriteResPair<WriteFTestY, [HWPort0], 1, [1], 1, 7>; 324defm : HWWriteResPair<WriteFTestZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1 325defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1, [1], 1, 6>; 326defm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>; 327defm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 328defm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1, [1], 1, 6>; 329defm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>; 330defm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 331defm : HWWriteResPair<WriteFBlend, [HWPort015], 1, [1], 1, 6>; 332defm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>; 333defm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1 334defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>; 335defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>; 336defm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2], 2, 6>; 337defm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>; 338defm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1 339 340// Conversion between integer and float. 341defm : HWWriteResPair<WriteCvtSD2I, [HWPort1], 3>; 342defm : HWWriteResPair<WriteCvtPD2I, [HWPort1], 3>; 343defm : HWWriteResPair<WriteCvtPD2IY, [HWPort1], 3>; 344defm : HWWriteResPair<WriteCvtPD2IZ, [HWPort1], 3>; // Unsupported = 1 345defm : HWWriteResPair<WriteCvtSS2I, [HWPort1], 3>; 346defm : HWWriteResPair<WriteCvtPS2I, [HWPort1], 3>; 347defm : HWWriteResPair<WriteCvtPS2IY, [HWPort1], 3>; 348defm : HWWriteResPair<WriteCvtPS2IZ, [HWPort1], 3>; // Unsupported = 1 349 350defm : HWWriteResPair<WriteCvtI2SD, [HWPort1], 4>; 351defm : HWWriteResPair<WriteCvtI2PD, [HWPort1], 4>; 352defm : HWWriteResPair<WriteCvtI2PDY, [HWPort1], 4>; 353defm : HWWriteResPair<WriteCvtI2PDZ, [HWPort1], 4>; // Unsupported = 1 354defm : HWWriteResPair<WriteCvtI2SS, [HWPort1], 4>; 355defm : HWWriteResPair<WriteCvtI2PS, [HWPort1], 4>; 356defm : HWWriteResPair<WriteCvtI2PSY, [HWPort1], 4>; 357defm : HWWriteResPair<WriteCvtI2PSZ, [HWPort1], 4>; // Unsupported = 1 358 359defm : HWWriteResPair<WriteCvtSS2SD, [HWPort1], 3>; 360defm : HWWriteResPair<WriteCvtPS2PD, [HWPort1], 3>; 361defm : HWWriteResPair<WriteCvtPS2PDY, [HWPort1], 3>; 362defm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort1], 3>; // Unsupported = 1 363defm : HWWriteResPair<WriteCvtSD2SS, [HWPort1], 3>; 364defm : HWWriteResPair<WriteCvtPD2PS, [HWPort1], 3>; 365defm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1], 3>; 366defm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1], 3>; // Unsupported = 1 367 368defm : X86WriteRes<WriteCvtPH2PS, [HWPort0,HWPort5], 2, [1,1], 2>; 369defm : X86WriteRes<WriteCvtPH2PSY, [HWPort0,HWPort5], 2, [1,1], 2>; 370defm : X86WriteRes<WriteCvtPH2PSZ, [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1 371defm : X86WriteRes<WriteCvtPH2PSLd, [HWPort0,HWPort23], 6, [1,1], 2>; 372defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>; 373defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1 374 375defm : X86WriteRes<WriteCvtPS2PH, [HWPort1,HWPort5], 4, [1,1], 2>; 376defm : X86WriteRes<WriteCvtPS2PHY, [HWPort1,HWPort5], 6, [1,1], 2>; 377defm : X86WriteRes<WriteCvtPS2PHZ, [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1 378defm : X86WriteRes<WriteCvtPS2PHSt, [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>; 379defm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; 380defm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1 381 382// Vector integer operations. 383defm : X86WriteRes<WriteVecLoad, [HWPort23], 5, [1], 1>; 384defm : X86WriteRes<WriteVecLoadX, [HWPort23], 6, [1], 1>; 385defm : X86WriteRes<WriteVecLoadY, [HWPort23], 7, [1], 1>; 386defm : X86WriteRes<WriteVecLoadNT, [HWPort23], 6, [1], 1>; 387defm : X86WriteRes<WriteVecLoadNTY, [HWPort23], 7, [1], 1>; 388defm : X86WriteRes<WriteVecMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>; 389defm : X86WriteRes<WriteVecMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>; 390defm : X86WriteRes<WriteVecStore, [HWPort237,HWPort4], 1, [1,1], 2>; 391defm : X86WriteRes<WriteVecStoreX, [HWPort237,HWPort4], 1, [1,1], 2>; 392defm : X86WriteRes<WriteVecStoreY, [HWPort237,HWPort4], 1, [1,1], 2>; 393defm : X86WriteRes<WriteVecStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>; 394defm : X86WriteRes<WriteVecStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>; 395defm : X86WriteRes<WriteVecMaskedStore32, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 396defm : X86WriteRes<WriteVecMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 397defm : X86WriteRes<WriteVecMaskedStore64, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 398defm : X86WriteRes<WriteVecMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 399defm : X86WriteRes<WriteVecMove, [HWPort015], 1, [1], 1>; 400defm : X86WriteRes<WriteVecMoveX, [HWPort015], 1, [1], 1>; 401defm : X86WriteRes<WriteVecMoveY, [HWPort015], 1, [1], 1>; 402defm : X86WriteRes<WriteVecMoveToGpr, [HWPort0], 1, [1], 1>; 403defm : X86WriteRes<WriteVecMoveFromGpr, [HWPort5], 1, [1], 1>; 404 405defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>; 406defm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>; 407defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>; 408defm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1 409defm : HWWriteResPair<WriteVecTest, [HWPort0,HWPort5], 2, [1,1], 2, 6>; 410defm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>; 411defm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1 412defm : HWWriteResPair<WriteVecALU, [HWPort15], 1, [1], 1, 5>; 413defm : HWWriteResPair<WriteVecALUX, [HWPort15], 1, [1], 1, 6>; 414defm : HWWriteResPair<WriteVecALUY, [HWPort15], 1, [1], 1, 7>; 415defm : HWWriteResPair<WriteVecALUZ, [HWPort15], 1, [1], 1, 7>; // Unsupported = 1 416defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 5>; 417defm : HWWriteResPair<WriteVecIMulX, [HWPort0], 5, [1], 1, 6>; 418defm : HWWriteResPair<WriteVecIMulY, [HWPort0], 5, [1], 1, 7>; 419defm : HWWriteResPair<WriteVecIMulZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1 420defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>; 421defm : HWWriteResPair<WritePMULLDY, [HWPort0], 10, [2], 2, 7>; 422defm : HWWriteResPair<WritePMULLDZ, [HWPort0], 10, [2], 2, 7>; // Unsupported = 1 423defm : HWWriteResPair<WriteShuffle, [HWPort5], 1, [1], 1, 5>; 424defm : HWWriteResPair<WriteShuffleX, [HWPort5], 1, [1], 1, 6>; 425defm : HWWriteResPair<WriteShuffleY, [HWPort5], 1, [1], 1, 7>; 426defm : HWWriteResPair<WriteShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 427defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>; 428defm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>; 429defm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>; 430defm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1 431defm : HWWriteResPair<WriteBlend, [HWPort5], 1, [1], 1, 6>; 432defm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>; 433defm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 434defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>; 435defm : HWWriteResPair<WriteVPMOV256, [HWPort5], 3, [1], 1, 7>; 436defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>; 437defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>; 438defm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>; 439defm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1 440defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 7, [1, 2], 3, 6>; 441defm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; 442defm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1 443defm : HWWriteResPair<WritePSADBW, [HWPort0], 5, [1], 1, 5>; 444defm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>; 445defm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>; 446defm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1 447defm : HWWriteResPair<WritePHMINPOS, [HWPort0], 5, [1], 1, 6>; 448 449// Vector integer shifts. 450defm : HWWriteResPair<WriteVecShift, [HWPort0], 1, [1], 1, 5>; 451defm : HWWriteResPair<WriteVecShiftX, [HWPort0,HWPort5], 2, [1,1], 2, 6>; 452defm : X86WriteRes<WriteVecShiftY, [HWPort0,HWPort5], 4, [1,1], 2>; 453defm : X86WriteRes<WriteVecShiftZ, [HWPort0,HWPort5], 4, [1,1], 2>; // Unsupported = 1 454defm : X86WriteRes<WriteVecShiftYLd, [HWPort0,HWPort23], 8, [1,1], 2>; 455defm : X86WriteRes<WriteVecShiftZLd, [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1 456 457defm : HWWriteResPair<WriteVecShiftImm, [HWPort0], 1, [1], 1, 5>; 458defm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>; 459defm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>; 460defm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1 461defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 3, [2,1], 3, 6>; 462defm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>; 463defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1 464 465// Vector insert/extract operations. 466def : WriteRes<WriteVecInsert, [HWPort5]> { 467 let Latency = 2; 468 let NumMicroOps = 2; 469 let ResourceCycles = [2]; 470} 471def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> { 472 let Latency = 6; 473 let NumMicroOps = 2; 474} 475def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 476 477def : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> { 478 let Latency = 2; 479 let NumMicroOps = 2; 480} 481def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> { 482 let Latency = 2; 483 let NumMicroOps = 3; 484} 485 486// String instructions. 487 488// Packed Compare Implicit Length Strings, Return Mask 489def : WriteRes<WritePCmpIStrM, [HWPort0]> { 490 let Latency = 11; 491 let NumMicroOps = 3; 492 let ResourceCycles = [3]; 493} 494def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> { 495 let Latency = 17; 496 let NumMicroOps = 4; 497 let ResourceCycles = [3,1]; 498} 499 500// Packed Compare Explicit Length Strings, Return Mask 501def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> { 502 let Latency = 19; 503 let NumMicroOps = 9; 504 let ResourceCycles = [4,3,1,1]; 505} 506def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> { 507 let Latency = 25; 508 let NumMicroOps = 10; 509 let ResourceCycles = [4,3,1,1,1]; 510} 511 512// Packed Compare Implicit Length Strings, Return Index 513def : WriteRes<WritePCmpIStrI, [HWPort0]> { 514 let Latency = 11; 515 let NumMicroOps = 3; 516 let ResourceCycles = [3]; 517} 518def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> { 519 let Latency = 17; 520 let NumMicroOps = 4; 521 let ResourceCycles = [3,1]; 522} 523 524// Packed Compare Explicit Length Strings, Return Index 525def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> { 526 let Latency = 18; 527 let NumMicroOps = 8; 528 let ResourceCycles = [4,3,1]; 529} 530def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> { 531 let Latency = 24; 532 let NumMicroOps = 9; 533 let ResourceCycles = [4,3,1,1]; 534} 535 536// MOVMSK Instructions. 537def : WriteRes<WriteFMOVMSK, [HWPort0]> { let Latency = 3; } 538def : WriteRes<WriteVecMOVMSK, [HWPort0]> { let Latency = 3; } 539def : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; } 540def : WriteRes<WriteMMXMOVMSK, [HWPort0]> { let Latency = 1; } 541 542// AES Instructions. 543def : WriteRes<WriteAESDecEnc, [HWPort5]> { 544 let Latency = 7; 545 let NumMicroOps = 1; 546 let ResourceCycles = [1]; 547} 548def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> { 549 let Latency = 13; 550 let NumMicroOps = 2; 551 let ResourceCycles = [1,1]; 552} 553 554def : WriteRes<WriteAESIMC, [HWPort5]> { 555 let Latency = 14; 556 let NumMicroOps = 2; 557 let ResourceCycles = [2]; 558} 559def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> { 560 let Latency = 20; 561 let NumMicroOps = 3; 562 let ResourceCycles = [2,1]; 563} 564 565def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> { 566 let Latency = 29; 567 let NumMicroOps = 11; 568 let ResourceCycles = [2,7,2]; 569} 570def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> { 571 let Latency = 34; 572 let NumMicroOps = 11; 573 let ResourceCycles = [2,7,1,1]; 574} 575 576// Carry-less multiplication instructions. 577def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> { 578 let Latency = 11; 579 let NumMicroOps = 3; 580 let ResourceCycles = [2,1]; 581} 582def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> { 583 let Latency = 17; 584 let NumMicroOps = 4; 585 let ResourceCycles = [2,1,1]; 586} 587 588// Load/store MXCSR. 589def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 590def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 591 592def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; } 593def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; } 594def : WriteRes<WriteFence, [HWPort23, HWPort4]>; 595def : WriteRes<WriteNop, []>; 596 597//================ Exceptions ================// 598 599//-- Specific Scheduling Models --// 600 601// Starting with P0. 602def HWWriteP0 : SchedWriteRes<[HWPort0]>; 603 604def HWWriteP01 : SchedWriteRes<[HWPort01]>; 605 606def HWWrite2P01 : SchedWriteRes<[HWPort01]> { 607 let NumMicroOps = 2; 608} 609def HWWrite3P01 : SchedWriteRes<[HWPort01]> { 610 let NumMicroOps = 3; 611} 612 613def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { 614 let NumMicroOps = 2; 615} 616 617def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { 618 let NumMicroOps = 3; 619 let ResourceCycles = [2, 1]; 620} 621 622// Starting with P1. 623def HWWriteP1 : SchedWriteRes<[HWPort1]>; 624 625 626def HWWrite2P1 : SchedWriteRes<[HWPort1]> { 627 let NumMicroOps = 2; 628 let ResourceCycles = [2]; 629} 630 631// Notation: 632// - r: register. 633// - mm: 64 bit mmx register. 634// - x = 128 bit xmm register. 635// - (x)mm = mmx or xmm register. 636// - y = 256 bit ymm register. 637// - v = any vector register. 638// - m = memory. 639 640//=== Integer Instructions ===// 641//-- Move instructions --// 642 643// XLAT. 644def HWWriteXLAT : SchedWriteRes<[]> { 645 let Latency = 7; 646 let NumMicroOps = 3; 647} 648def : InstRW<[HWWriteXLAT], (instrs XLAT)>; 649 650// PUSHA. 651def HWWritePushA : SchedWriteRes<[]> { 652 let NumMicroOps = 19; 653} 654def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>; 655 656// POPA. 657def HWWritePopA : SchedWriteRes<[]> { 658 let NumMicroOps = 18; 659} 660def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>; 661 662//-- Arithmetic instructions --// 663 664// BTR BTS BTC. 665// m,r. 666def HWWriteBTRSCmr : SchedWriteRes<[]> { 667 let NumMicroOps = 11; 668} 669def : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>; 670 671//-- Control transfer instructions --// 672 673// CALL. 674// i. 675def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { 676 let NumMicroOps = 4; 677 let ResourceCycles = [1, 2, 1]; 678} 679def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; 680 681// BOUND. 682// r,m. 683def HWWriteBOUND : SchedWriteRes<[]> { 684 let NumMicroOps = 15; 685} 686def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>; 687 688// INTO. 689def HWWriteINTO : SchedWriteRes<[]> { 690 let NumMicroOps = 4; 691} 692def : InstRW<[HWWriteINTO], (instrs INTO)>; 693 694//-- String instructions --// 695 696// LODSB/W. 697def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>; 698 699// LODSD/Q. 700def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>; 701 702// MOVS. 703def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { 704 let Latency = 4; 705 let NumMicroOps = 5; 706 let ResourceCycles = [2, 1, 2]; 707} 708def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 709 710// CMPS. 711def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { 712 let Latency = 4; 713 let NumMicroOps = 5; 714 let ResourceCycles = [2, 3]; 715} 716def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>; 717 718//-- Other --// 719 720// RDPMC.f 721def HWWriteRDPMC : SchedWriteRes<[]> { 722 let NumMicroOps = 34; 723} 724def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>; 725 726// RDRAND. 727def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { 728 let NumMicroOps = 17; 729 let ResourceCycles = [1, 16]; 730} 731def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 732 733//=== Floating Point x87 Instructions ===// 734//-- Move instructions --// 735 736// FLD. 737// m80. 738def : InstRW<[HWWriteP01], (instrs LD_Frr)>; 739 740// FBLD. 741// m80. 742def HWWriteFBLD : SchedWriteRes<[]> { 743 let Latency = 47; 744 let NumMicroOps = 43; 745} 746def : InstRW<[HWWriteFBLD], (instrs FBLDm)>; 747 748// FST(P). 749// r. 750def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>; 751 752// FFREE. 753def : InstRW<[HWWriteP01], (instregex "FFREE")>; 754 755// FNSAVE. 756def HWWriteFNSAVE : SchedWriteRes<[]> { 757 let NumMicroOps = 147; 758} 759def : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>; 760 761// FRSTOR. 762def HWWriteFRSTOR : SchedWriteRes<[]> { 763 let NumMicroOps = 90; 764} 765def : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>; 766 767//-- Arithmetic instructions --// 768 769// FCOMPP FUCOMPP. 770// r. 771def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>; 772 773// FCOMI(P) FUCOMI(P). 774// m. 775def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 776 777// FTST. 778def : InstRW<[HWWriteP1], (instregex "TST_F")>; 779 780// FXAM. 781def : InstRW<[HWWrite2P1], (instrs FXAM)>; 782 783// FPREM. 784def HWWriteFPREM : SchedWriteRes<[]> { 785 let Latency = 19; 786 let NumMicroOps = 28; 787} 788def : InstRW<[HWWriteFPREM], (instrs FPREM)>; 789 790// FPREM1. 791def HWWriteFPREM1 : SchedWriteRes<[]> { 792 let Latency = 27; 793 let NumMicroOps = 41; 794} 795def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>; 796 797// FRNDINT. 798def HWWriteFRNDINT : SchedWriteRes<[]> { 799 let Latency = 11; 800 let NumMicroOps = 17; 801} 802def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>; 803 804//-- Math instructions --// 805 806// FSCALE. 807def HWWriteFSCALE : SchedWriteRes<[]> { 808 let Latency = 75; // 49-125 809 let NumMicroOps = 50; // 25-75 810} 811def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>; 812 813// FXTRACT. 814def HWWriteFXTRACT : SchedWriteRes<[]> { 815 let Latency = 15; 816 let NumMicroOps = 17; 817} 818def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>; 819 820//////////////////////////////////////////////////////////////////////////////// 821// Horizontal add/sub instructions. 822//////////////////////////////////////////////////////////////////////////////// 823 824defm : HWWriteResPair<WriteFHAdd, [HWPort1, HWPort5], 5, [1,2], 3, 6>; 825defm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>; 826defm : HWWriteResPair<WritePHAdd, [HWPort5, HWPort15], 3, [2,1], 3, 5>; 827defm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>; 828defm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>; 829 830//=== Floating Point XMM and YMM Instructions ===// 831 832// Remaining instrs. 833 834def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> { 835 let Latency = 6; 836 let NumMicroOps = 1; 837 let ResourceCycles = [1]; 838} 839def: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>; 840def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm", 841 "(V?)MOVSLDUPrm", 842 "VPBROADCAST(D|Q)rm")>; 843 844def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> { 845 let Latency = 7; 846 let NumMicroOps = 1; 847 let ResourceCycles = [1]; 848} 849def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128, 850 VBROADCASTI128, 851 VBROADCASTSDYrm, 852 VBROADCASTSSYrm, 853 VMOVDDUPYrm, 854 VMOVSHDUPYrm, 855 VMOVSLDUPYrm)>; 856def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m", 857 "VPBROADCAST(D|Q)Yrm")>; 858 859def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> { 860 let Latency = 5; 861 let NumMicroOps = 1; 862 let ResourceCycles = [1]; 863} 864def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm(8|16|32)", 865 "MOVZX(16|32|64)rm(8|16)", 866 "(V?)MOVDDUPrm")>; 867 868def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> { 869 let Latency = 1; 870 let NumMicroOps = 2; 871 let ResourceCycles = [1,1]; 872} 873def: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>; 874def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>; 875 876def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { 877 let Latency = 1; 878 let NumMicroOps = 1; 879 let ResourceCycles = [1]; 880} 881def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr", 882 "VPSRLVQ(Y?)rr")>; 883 884def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> { 885 let Latency = 1; 886 let NumMicroOps = 1; 887 let ResourceCycles = [1]; 888} 889def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r", 890 "UCOM_F(P?)r")>; 891 892def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> { 893 let Latency = 1; 894 let NumMicroOps = 1; 895 let ResourceCycles = [1]; 896} 897def: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>; 898 899def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> { 900 let Latency = 1; 901 let NumMicroOps = 1; 902 let ResourceCycles = [1]; 903} 904def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>; 905 906def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> { 907 let Latency = 1; 908 let NumMicroOps = 1; 909 let ResourceCycles = [1]; 910} 911def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>; 912 913def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> { 914 let Latency = 1; 915 let NumMicroOps = 1; 916 let ResourceCycles = [1]; 917} 918def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>; 919 920def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { 921 let Latency = 1; 922 let NumMicroOps = 1; 923 let ResourceCycles = [1]; 924} 925def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>; 926 927def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { 928 let Latency = 1; 929 let NumMicroOps = 1; 930 let ResourceCycles = [1]; 931} 932def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>; 933 934def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> { 935 let Latency = 1; 936 let NumMicroOps = 1; 937 let ResourceCycles = [1]; 938} 939def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE, 940 CMC, STC, 941 SGDT64m, 942 SIDT64m, 943 SMSW16m, 944 STRm, 945 SYSCALL)>; 946 947def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> { 948 let Latency = 6; 949 let NumMicroOps = 2; 950 let ResourceCycles = [1,1]; 951} 952def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>; 953 954def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> { 955 let Latency = 7; 956 let NumMicroOps = 2; 957 let ResourceCycles = [1,1]; 958} 959def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>; 960def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm")>; 961 962def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> { 963 let Latency = 8; 964 let NumMicroOps = 2; 965 let ResourceCycles = [1,1]; 966} 967def: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>; 968 969def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> { 970 let Latency = 8; 971 let NumMicroOps = 2; 972 let ResourceCycles = [1,1]; 973} 974def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSirm)>; 975def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>; 976 977def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> { 978 let Latency = 6; 979 let NumMicroOps = 2; 980 let ResourceCycles = [1,1]; 981} 982def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm", 983 "(V?)PMOV(SX|ZX)BQrm", 984 "(V?)PMOV(SX|ZX)BWrm", 985 "(V?)PMOV(SX|ZX)DQrm", 986 "(V?)PMOV(SX|ZX)WDrm", 987 "(V?)PMOV(SX|ZX)WQrm")>; 988 989def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> { 990 let Latency = 8; 991 let NumMicroOps = 2; 992 let ResourceCycles = [1,1]; 993} 994def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm, 995 VPMOVSXBQYrm, 996 VPMOVSXWQYrm)>; 997 998def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> { 999 let Latency = 6; 1000 let NumMicroOps = 2; 1001 let ResourceCycles = [1,1]; 1002} 1003def: InstRW<[HWWriteResGroup14], (instrs FARJMP64m)>; 1004def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>; 1005 1006def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> { 1007 let Latency = 6; 1008 let NumMicroOps = 2; 1009 let ResourceCycles = [1,1]; 1010} 1011def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm", 1012 "MOVBE(16|32|64)rm")>; 1013 1014def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> { 1015 let Latency = 7; 1016 let NumMicroOps = 2; 1017 let ResourceCycles = [1,1]; 1018} 1019def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm, 1020 VINSERTI128rm, 1021 VPBLENDDrmi)>; 1022 1023def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> { 1024 let Latency = 8; 1025 let NumMicroOps = 2; 1026 let ResourceCycles = [1,1]; 1027} 1028def: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>; 1029 1030def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> { 1031 let Latency = 6; 1032 let NumMicroOps = 2; 1033 let ResourceCycles = [1,1]; 1034} 1035def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>; 1036def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>; 1037 1038def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> { 1039 let Latency = 2; 1040 let NumMicroOps = 2; 1041 let ResourceCycles = [1,1]; 1042} 1043def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>; 1044 1045def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> { 1046 let Latency = 2; 1047 let NumMicroOps = 3; 1048 let ResourceCycles = [1,1,1]; 1049} 1050def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>; 1051 1052def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { 1053 let Latency = 2; 1054 let NumMicroOps = 3; 1055 let ResourceCycles = [1,1,1]; 1056} 1057def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>; 1058 1059def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { 1060 let Latency = 2; 1061 let NumMicroOps = 3; 1062 let ResourceCycles = [1,1,1]; 1063} 1064def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>; 1065 1066def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { 1067 let Latency = 2; 1068 let NumMicroOps = 3; 1069 let ResourceCycles = [1,1,1]; 1070} 1071def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 1072 STOSB, STOSL, STOSQ, STOSW)>; 1073def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>; 1074 1075def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { 1076 let Latency = 7; 1077 let NumMicroOps = 4; 1078 let ResourceCycles = [1,1,1,1]; 1079} 1080def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)", 1081 "SHL(8|16|32|64)m(1|i)", 1082 "SHR(8|16|32|64)m(1|i)")>; 1083 1084def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1085 let Latency = 7; 1086 let NumMicroOps = 4; 1087 let ResourceCycles = [1,1,1,1]; 1088} 1089def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm", 1090 "PUSH(16|32|64)rmm")>; 1091 1092def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> { 1093 let Latency = 2; 1094 let NumMicroOps = 2; 1095 let ResourceCycles = [2]; 1096} 1097def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>; 1098 1099def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> { 1100 let Latency = 2; 1101 let NumMicroOps = 2; 1102 let ResourceCycles = [2]; 1103} 1104def: InstRW<[HWWriteResGroup30], (instrs LFENCE, 1105 MFENCE, 1106 WAIT, 1107 XGETBV)>; 1108 1109def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> { 1110 let Latency = 2; 1111 let NumMicroOps = 2; 1112 let ResourceCycles = [1,1]; 1113} 1114def: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr", 1115 "(V?)CVTSS2SDrr")>; 1116 1117def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> { 1118 let Latency = 2; 1119 let NumMicroOps = 2; 1120 let ResourceCycles = [1,1]; 1121} 1122def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>; 1123 1124def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> { 1125 let Latency = 2; 1126 let NumMicroOps = 2; 1127 let ResourceCycles = [1,1]; 1128} 1129def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>; 1130 1131def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> { 1132 let Latency = 2; 1133 let NumMicroOps = 2; 1134 let ResourceCycles = [1,1]; 1135} 1136def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>; 1137 1138def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> { 1139 let Latency = 7; 1140 let NumMicroOps = 3; 1141 let ResourceCycles = [2,1]; 1142} 1143def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWirm, 1144 MMX_PACKSSWBirm, 1145 MMX_PACKUSWBirm)>; 1146 1147def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> { 1148 let Latency = 7; 1149 let NumMicroOps = 3; 1150 let ResourceCycles = [1,2]; 1151} 1152def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64, 1153 SCASB, SCASL, SCASQ, SCASW)>; 1154 1155def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> { 1156 let Latency = 7; 1157 let NumMicroOps = 3; 1158 let ResourceCycles = [1,1,1]; 1159} 1160def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>; 1161 1162def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { 1163 let Latency = 7; 1164 let NumMicroOps = 3; 1165 let ResourceCycles = [1,1,1]; 1166} 1167def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>; 1168 1169def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> { 1170 let Latency = 3; 1171 let NumMicroOps = 4; 1172 let ResourceCycles = [1,1,1,1]; 1173} 1174def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>; 1175 1176def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { 1177 let Latency = 3; 1178 let NumMicroOps = 4; 1179 let ResourceCycles = [1,1,1,1]; 1180} 1181def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>; 1182 1183def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { 1184 let Latency = 8; 1185 let NumMicroOps = 5; 1186 let ResourceCycles = [1,1,1,2]; 1187} 1188def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)", 1189 "ROR(8|16|32|64)m(1|i)")>; 1190 1191def HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> { 1192 let Latency = 2; 1193 let NumMicroOps = 2; 1194 let ResourceCycles = [2]; 1195} 1196def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1197 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1198 1199def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1200 let Latency = 8; 1201 let NumMicroOps = 5; 1202 let ResourceCycles = [1,1,1,2]; 1203} 1204def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>; 1205 1206def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1207 let Latency = 8; 1208 let NumMicroOps = 5; 1209 let ResourceCycles = [1,1,1,1,1]; 1210} 1211def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>; 1212def: InstRW<[HWWriteResGroup48], (instrs FARCALL64m)>; 1213 1214def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> { 1215 let Latency = 3; 1216 let NumMicroOps = 1; 1217 let ResourceCycles = [1]; 1218} 1219def: InstRW<[HWWriteResGroup50], (instrs MMX_CVTPI2PSirr)>; 1220def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr", 1221 "(V?)CVTDQ2PS(Y?)rr")>; 1222 1223def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> { 1224 let Latency = 3; 1225 let NumMicroOps = 1; 1226 let ResourceCycles = [1]; 1227} 1228def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>; 1229 1230def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> { 1231 let Latency = 9; 1232 let NumMicroOps = 2; 1233 let ResourceCycles = [1,1]; 1234} 1235def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm", 1236 "(V?)CVTTPS2DQrm")>; 1237 1238def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> { 1239 let Latency = 10; 1240 let NumMicroOps = 2; 1241 let ResourceCycles = [1,1]; 1242} 1243def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1244 "ILD_F(16|32|64)m")>; 1245def: InstRW<[HWWriteResGroup52_1], (instrs VCVTDQ2PSYrm, 1246 VCVTPS2DQYrm, 1247 VCVTTPS2DQYrm)>; 1248 1249def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> { 1250 let Latency = 9; 1251 let NumMicroOps = 2; 1252 let ResourceCycles = [1,1]; 1253} 1254def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm, 1255 VPMOVSXDQYrm, 1256 VPMOVSXWDYrm, 1257 VPMOVZXWDYrm)>; 1258 1259def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> { 1260 let Latency = 3; 1261 let NumMicroOps = 3; 1262 let ResourceCycles = [2,1]; 1263} 1264def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWirr, 1265 MMX_PACKSSWBirr, 1266 MMX_PACKUSWBirr)>; 1267 1268def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> { 1269 let Latency = 3; 1270 let NumMicroOps = 3; 1271 let ResourceCycles = [1,2]; 1272} 1273def: InstRW<[HWWriteResGroup58], (instregex "CLD")>; 1274 1275def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> { 1276 let Latency = 3; 1277 let NumMicroOps = 3; 1278 let ResourceCycles = [1,2]; 1279} 1280def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)", 1281 "RCR(8|16|32|64)r(1|i)")>; 1282 1283def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> { 1284 let Latency = 4; 1285 let NumMicroOps = 3; 1286 let ResourceCycles = [1,1,1]; 1287} 1288def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>; 1289 1290def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> { 1291 let Latency = 4; 1292 let NumMicroOps = 3; 1293 let ResourceCycles = [1,1,1]; 1294} 1295def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m", 1296 "IST_F(16|32)m")>; 1297 1298def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { 1299 let Latency = 9; 1300 let NumMicroOps = 5; 1301 let ResourceCycles = [1,1,1,2]; 1302} 1303def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)", 1304 "RCR(8|16|32|64)m(1|i)")>; 1305 1306def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1307 let Latency = 9; 1308 let NumMicroOps = 6; 1309 let ResourceCycles = [1,1,1,3]; 1310} 1311def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>; 1312 1313def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1314 let Latency = 9; 1315 let NumMicroOps = 6; 1316 let ResourceCycles = [1,1,1,2,1]; 1317} 1318def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL", 1319 "ROR(8|16|32|64)mCL", 1320 "SAR(8|16|32|64)mCL", 1321 "SHL(8|16|32|64)mCL", 1322 "SHR(8|16|32|64)mCL")>; 1323def: SchedAlias<WriteADCRMW, HWWriteResGroup69>; 1324 1325def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> { 1326 let Latency = 4; 1327 let NumMicroOps = 2; 1328 let ResourceCycles = [1,1]; 1329} 1330def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr", 1331 "(V?)CVT(T?)SS2SI(64)?rr")>; 1332 1333def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> { 1334 let Latency = 4; 1335 let NumMicroOps = 2; 1336 let ResourceCycles = [1,1]; 1337} 1338def: InstRW<[HWWriteResGroup71], (instrs VCVTPS2PDYrr)>; 1339 1340def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> { 1341 let Latency = 4; 1342 let NumMicroOps = 2; 1343 let ResourceCycles = [1,1]; 1344} 1345def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>; 1346 1347def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> { 1348 let Latency = 4; 1349 let NumMicroOps = 2; 1350 let ResourceCycles = [1,1]; 1351} 1352def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDirr, 1353 MMX_CVTPD2PIirr, 1354 MMX_CVTPS2PIirr, 1355 MMX_CVTTPD2PIirr, 1356 MMX_CVTTPS2PIirr)>; 1357def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTDQ2PDrr", 1358 "(V?)CVTPD2PSrr", 1359 "(V?)CVTSD2SSrr", 1360 "(V?)CVTSI(64)?2SDrr", 1361 "(V?)CVTSI2SSrr", 1362 "(V?)CVT(T?)PD2DQrr")>; 1363 1364def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> { 1365 let Latency = 11; 1366 let NumMicroOps = 3; 1367 let ResourceCycles = [2,1]; 1368} 1369def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>; 1370 1371def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1372 let Latency = 9; 1373 let NumMicroOps = 3; 1374 let ResourceCycles = [1,1,1]; 1375} 1376def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm", 1377 "(V?)CVTSS2SI(64)?rm", 1378 "(V?)CVTTSD2SI(64)?rm", 1379 "VCVTTSS2SI64rm", 1380 "(V?)CVTTSS2SIrm")>; 1381 1382def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { 1383 let Latency = 10; 1384 let NumMicroOps = 3; 1385 let ResourceCycles = [1,1,1]; 1386} 1387def: InstRW<[HWWriteResGroup77], (instrs VCVTPS2PDYrm)>; 1388 1389def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1390 let Latency = 10; 1391 let NumMicroOps = 3; 1392 let ResourceCycles = [1,1,1]; 1393} 1394def: InstRW<[HWWriteResGroup78], (instrs CVTPD2PSrm, 1395 CVTPD2DQrm, 1396 CVTTPD2DQrm, 1397 MMX_CVTPD2PIirm, 1398 MMX_CVTTPD2PIirm, 1399 CVTDQ2PDrm, 1400 VCVTDQ2PDrm)>; 1401 1402def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1403 let Latency = 9; 1404 let NumMicroOps = 3; 1405 let ResourceCycles = [1,1,1]; 1406} 1407def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDirm, 1408 CVTSD2SSrm, CVTSD2SSrm_Int, 1409 VCVTSD2SSrm, VCVTSD2SSrm_Int)>; 1410 1411def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> { 1412 let Latency = 9; 1413 let NumMicroOps = 3; 1414 let ResourceCycles = [1,1,1]; 1415} 1416def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>; 1417 1418def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> { 1419 let Latency = 4; 1420 let NumMicroOps = 4; 1421 let ResourceCycles = [4]; 1422} 1423def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>; 1424 1425def HWWriteResGroup82 : SchedWriteRes<[]> { 1426 let Latency = 0; 1427 let NumMicroOps = 4; 1428 let ResourceCycles = []; 1429} 1430def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>; 1431 1432def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> { 1433 let Latency = 4; 1434 let NumMicroOps = 4; 1435 let ResourceCycles = [1,1,2]; 1436} 1437def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>; 1438 1439def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> { 1440 let Latency = 9; 1441 let NumMicroOps = 5; 1442 let ResourceCycles = [1,2,1,1]; 1443} 1444def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm", 1445 "LSL(16|32|64)rm")>; 1446 1447def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { 1448 let Latency = 5; 1449 let NumMicroOps = 6; 1450 let ResourceCycles = [1,1,4]; 1451} 1452def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>; 1453 1454def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> { 1455 let Latency = 5; 1456 let NumMicroOps = 1; 1457 let ResourceCycles = [1]; 1458} 1459def: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 1460 1461def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> { 1462 let Latency = 11; 1463 let NumMicroOps = 2; 1464 let ResourceCycles = [1,1]; 1465} 1466def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>; 1467 1468def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> { 1469 let Latency = 12; 1470 let NumMicroOps = 2; 1471 let ResourceCycles = [1,1]; 1472} 1473def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>; 1474def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>; 1475 1476def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> { 1477 let Latency = 5; 1478 let NumMicroOps = 3; 1479 let ResourceCycles = [1,2]; 1480} 1481def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>; 1482 1483def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> { 1484 let Latency = 5; 1485 let NumMicroOps = 3; 1486 let ResourceCycles = [1,1,1]; 1487} 1488def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>; 1489 1490def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> { 1491 let Latency = 10; 1492 let NumMicroOps = 4; 1493 let ResourceCycles = [1,1,1,1]; 1494} 1495def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>; 1496 1497def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> { 1498 let Latency = 5; 1499 let NumMicroOps = 5; 1500 let ResourceCycles = [1,4]; 1501} 1502def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>; 1503 1504def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> { 1505 let Latency = 5; 1506 let NumMicroOps = 5; 1507 let ResourceCycles = [1,4]; 1508} 1509def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>; 1510 1511def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> { 1512 let Latency = 6; 1513 let NumMicroOps = 2; 1514 let ResourceCycles = [1,1]; 1515} 1516def: InstRW<[HWWriteResGroup102], (instrs VCVTDQ2PDYrr, 1517 VCVTPD2PSYrr, 1518 VCVTPD2DQYrr, 1519 VCVTTPD2DQYrr)>; 1520 1521def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> { 1522 let Latency = 13; 1523 let NumMicroOps = 3; 1524 let ResourceCycles = [2,1]; 1525} 1526def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1527 1528def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1529 let Latency = 12; 1530 let NumMicroOps = 3; 1531 let ResourceCycles = [1,1,1]; 1532} 1533def: InstRW<[HWWriteResGroup104], (instrs VCVTDQ2PDYrm)>; 1534 1535def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> { 1536 let Latency = 6; 1537 let NumMicroOps = 4; 1538 let ResourceCycles = [1,1,1,1]; 1539} 1540def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>; 1541 1542def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> { 1543 let Latency = 6; 1544 let NumMicroOps = 6; 1545 let ResourceCycles = [1,5]; 1546} 1547def: InstRW<[HWWriteResGroup108], (instrs STD)>; 1548 1549def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> { 1550 let Latency = 7; 1551 let NumMicroOps = 7; 1552 let ResourceCycles = [2,2,1,2]; 1553} 1554def: InstRW<[HWWriteResGroup114], (instrs LOOP)>; 1555 1556def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1557 let Latency = 15; 1558 let NumMicroOps = 3; 1559 let ResourceCycles = [1,1,1]; 1560} 1561def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>; 1562 1563def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1564 let Latency = 16; 1565 let NumMicroOps = 10; 1566 let ResourceCycles = [1,1,1,4,1,2]; 1567} 1568def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>; 1569 1570def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { 1571 let Latency = 11; 1572 let NumMicroOps = 7; 1573 let ResourceCycles = [2,2,3]; 1574} 1575def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL", 1576 "RCR(16|32|64)rCL")>; 1577 1578def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { 1579 let Latency = 11; 1580 let NumMicroOps = 9; 1581 let ResourceCycles = [1,4,1,3]; 1582} 1583def: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>; 1584 1585def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> { 1586 let Latency = 11; 1587 let NumMicroOps = 11; 1588 let ResourceCycles = [2,9]; 1589} 1590def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>; 1591 1592def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1593 let Latency = 17; 1594 let NumMicroOps = 14; 1595 let ResourceCycles = [1,1,1,4,2,5]; 1596} 1597def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>; 1598 1599def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1600 let Latency = 19; 1601 let NumMicroOps = 11; 1602 let ResourceCycles = [2,1,1,3,1,3]; 1603} 1604def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>; 1605 1606def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { 1607 let Latency = 14; 1608 let NumMicroOps = 10; 1609 let ResourceCycles = [2,3,1,4]; 1610} 1611def: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>; 1612 1613def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> { 1614 let Latency = 19; 1615 let NumMicroOps = 15; 1616 let ResourceCycles = [1,14]; 1617} 1618def: InstRW<[HWWriteResGroup143], (instrs POPF16)>; 1619 1620def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1621 let Latency = 21; 1622 let NumMicroOps = 8; 1623 let ResourceCycles = [1,1,1,1,1,1,2]; 1624} 1625def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>; 1626 1627def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> { 1628 let Latency = 8; 1629 let NumMicroOps = 20; 1630 let ResourceCycles = [1,1]; 1631} 1632def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>; 1633 1634def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1635 let Latency = 22; 1636 let NumMicroOps = 19; 1637 let ResourceCycles = [2,1,4,1,1,4,6]; 1638} 1639def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>; 1640 1641def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { 1642 let Latency = 17; 1643 let NumMicroOps = 15; 1644 let ResourceCycles = [2,1,2,4,2,4]; 1645} 1646def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>; 1647 1648def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> { 1649 let Latency = 18; 1650 let NumMicroOps = 8; 1651 let ResourceCycles = [1,1,1,5]; 1652} 1653def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>; 1654 1655def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { 1656 let Latency = 23; 1657 let NumMicroOps = 19; 1658 let ResourceCycles = [3,1,15]; 1659} 1660def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>; 1661 1662def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> { 1663 let Latency = 20; 1664 let NumMicroOps = 1; 1665 let ResourceCycles = [1]; 1666} 1667def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1668 1669def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> { 1670 let Latency = 27; 1671 let NumMicroOps = 2; 1672 let ResourceCycles = [1,1]; 1673} 1674def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>; 1675 1676def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> { 1677 let Latency = 20; 1678 let NumMicroOps = 10; 1679 let ResourceCycles = [1,2,7]; 1680} 1681def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>; 1682 1683def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1684 let Latency = 30; 1685 let NumMicroOps = 3; 1686 let ResourceCycles = [1,1,1]; 1687} 1688def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>; 1689 1690def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> { 1691 let Latency = 24; 1692 let NumMicroOps = 1; 1693 let ResourceCycles = [1]; 1694} 1695def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1696 1697def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> { 1698 let Latency = 31; 1699 let NumMicroOps = 2; 1700 let ResourceCycles = [1,1]; 1701} 1702def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>; 1703 1704def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1705 let Latency = 30; 1706 let NumMicroOps = 27; 1707 let ResourceCycles = [1,5,1,1,19]; 1708} 1709def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>; 1710 1711def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1712 let Latency = 31; 1713 let NumMicroOps = 28; 1714 let ResourceCycles = [1,6,1,1,19]; 1715} 1716def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>; 1717def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 1718 1719def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1720 let Latency = 34; 1721 let NumMicroOps = 3; 1722 let ResourceCycles = [1,1,1]; 1723} 1724def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>; 1725 1726def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> { 1727 let Latency = 35; 1728 let NumMicroOps = 23; 1729 let ResourceCycles = [1,5,3,4,10]; 1730} 1731def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri", 1732 "IN(8|16|32)rr")>; 1733 1734def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1735 let Latency = 36; 1736 let NumMicroOps = 23; 1737 let ResourceCycles = [1,5,2,1,4,10]; 1738} 1739def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir", 1740 "OUT(8|16|32)rr")>; 1741 1742def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> { 1743 let Latency = 41; 1744 let NumMicroOps = 18; 1745 let ResourceCycles = [1,1,2,3,1,1,1,8]; 1746} 1747def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>; 1748 1749def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> { 1750 let Latency = 42; 1751 let NumMicroOps = 22; 1752 let ResourceCycles = [2,20]; 1753} 1754def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>; 1755 1756def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> { 1757 let Latency = 61; 1758 let NumMicroOps = 64; 1759 let ResourceCycles = [2,2,8,1,10,2,39]; 1760} 1761def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>; 1762 1763def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { 1764 let Latency = 64; 1765 let NumMicroOps = 88; 1766 let ResourceCycles = [4,4,31,1,2,1,45]; 1767} 1768def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>; 1769 1770def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { 1771 let Latency = 64; 1772 let NumMicroOps = 90; 1773 let ResourceCycles = [4,2,33,1,2,1,47]; 1774} 1775def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>; 1776 1777def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> { 1778 let Latency = 75; 1779 let NumMicroOps = 15; 1780 let ResourceCycles = [6,3,6]; 1781} 1782def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>; 1783 1784def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> { 1785 let Latency = 115; 1786 let NumMicroOps = 100; 1787 let ResourceCycles = [9,9,11,8,1,11,21,30]; 1788} 1789def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>; 1790 1791def HWWriteResGroup184 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 1792 let Latency = 14; 1793 let NumMicroOps = 12; 1794 let ResourceCycles = [2,2,2,1,3,2]; 1795} 1796def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, VPGATHERDQrm)>; 1797 1798def HWWriteResGroup185 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 1799 let Latency = 17; 1800 let NumMicroOps = 20; 1801 let ResourceCycles = [3,3,4,1,5,4]; 1802} 1803def: InstRW<[HWWriteResGroup185], (instrs VGATHERDPDYrm, VPGATHERDQYrm)>; 1804 1805def HWWriteResGroup186 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 1806 let Latency = 16; 1807 let NumMicroOps = 20; 1808 let ResourceCycles = [3,3,4,1,5,4]; 1809} 1810def: InstRW<[HWWriteResGroup186], (instrs VGATHERDPSrm, VPGATHERDDrm)>; 1811 1812def HWWriteResGroup187 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 1813 let Latency = 22; 1814 let NumMicroOps = 34; 1815 let ResourceCycles = [5,3,8,1,9,8]; 1816} 1817def: InstRW<[HWWriteResGroup187], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1818 1819def HWWriteResGroup188 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 1820 let Latency = 15; 1821 let NumMicroOps = 14; 1822 let ResourceCycles = [3,3,2,1,3,2]; 1823} 1824def: InstRW<[HWWriteResGroup188], (instrs VGATHERQPDrm, VPGATHERQQrm)>; 1825 1826def HWWriteResGroup189 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 1827 let Latency = 17; 1828 let NumMicroOps = 22; 1829 let ResourceCycles = [5,3,4,1,5,4]; 1830} 1831def: InstRW<[HWWriteResGroup189], (instrs VGATHERQPDYrm, VPGATHERQQYrm, 1832 VGATHERQPSYrm, VPGATHERQDYrm)>; 1833 1834def HWWriteResGroup190 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 1835 let Latency = 16; 1836 let NumMicroOps = 15; 1837 let ResourceCycles = [3,3,2,1,4,2]; 1838} 1839def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPSrm, VPGATHERQDrm)>; 1840 1841def: InstRW<[WriteZero], (instrs CLC)>; 1842 1843 1844// Instruction variants handled by the renamer. These might not need execution 1845// ports in certain conditions. 1846// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1847// section "Haswell and Broadwell Pipeline" > "Register allocation and 1848// renaming". 1849// These can be investigated with llvm-exegesis, e.g. 1850// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1851// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1852 1853def HWWriteZeroLatency : SchedWriteRes<[]> { 1854 let Latency = 0; 1855} 1856 1857def HWWriteZeroIdiom : SchedWriteVariant<[ 1858 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1859 SchedVar<NoSchedPred, [WriteALU]> 1860]>; 1861def : InstRW<[HWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1862 XOR32rr, XOR64rr)>; 1863 1864def HWWriteFZeroIdiom : SchedWriteVariant<[ 1865 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1866 SchedVar<NoSchedPred, [WriteFLogic]> 1867]>; 1868def : InstRW<[HWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1869 VXORPDrr)>; 1870 1871def HWWriteFZeroIdiomY : SchedWriteVariant<[ 1872 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1873 SchedVar<NoSchedPred, [WriteFLogicY]> 1874]>; 1875def : InstRW<[HWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1876 1877def HWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1878 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1879 SchedVar<NoSchedPred, [WriteVecLogicX]> 1880]>; 1881def : InstRW<[HWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1882 1883def HWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1884 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1885 SchedVar<NoSchedPred, [WriteVecLogicY]> 1886]>; 1887def : InstRW<[HWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1888 1889def HWWriteVZeroIdiomALUX : SchedWriteVariant<[ 1890 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1891 SchedVar<NoSchedPred, [WriteVecALUX]> 1892]>; 1893def : InstRW<[HWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1894 PSUBDrr, VPSUBDrr, 1895 PSUBQrr, VPSUBQrr, 1896 PSUBWrr, VPSUBWrr, 1897 PCMPGTBrr, VPCMPGTBrr, 1898 PCMPGTDrr, VPCMPGTDrr, 1899 PCMPGTWrr, VPCMPGTWrr)>; 1900 1901def HWWriteVZeroIdiomALUY : SchedWriteVariant<[ 1902 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1903 SchedVar<NoSchedPred, [WriteVecALUY]> 1904]>; 1905def : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 1906 VPSUBDYrr, 1907 VPSUBQYrr, 1908 VPSUBWYrr, 1909 VPCMPGTBYrr, 1910 VPCMPGTDYrr, 1911 VPCMPGTWYrr)>; 1912 1913def HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> { 1914 let Latency = 5; 1915 let NumMicroOps = 1; 1916 let ResourceCycles = [1]; 1917} 1918 1919def HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1920 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1921 SchedVar<NoSchedPred, [HWWritePCMPGTQ]> 1922]>; 1923def : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1924 VPCMPGTQYrr)>; 1925 1926 1927// The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require 1928// a single uop. It does not apply to the GR8 encoding. And only applies to the 1929// 8-bit immediate since using larger immediate for 0 would be silly. 1930// Unfortunately, this optimization does not apply to the AX/EAX/RAX short 1931// encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since 1932// we schedule before that point. 1933// TODO: Should we disable using the short encodings on these CPUs? 1934def HWFastADC0 : MCSchedPredicate< 1935 CheckAll<[ 1936 CheckImmOperand<2, 0>, // Second MCOperand is Imm and has value 0. 1937 CheckNot<CheckRegOperand<1, AX>>, // First MCOperand is not register AX 1938 CheckNot<CheckRegOperand<1, EAX>>, // First MCOperand is not register EAX 1939 CheckNot<CheckRegOperand<1, RAX>> // First MCOperand is not register RAX 1940 ]> 1941>; 1942 1943def HWWriteADC0 : SchedWriteRes<[HWPort06]> { 1944 let Latency = 1; 1945 let NumMicroOps = 1; 1946 let ResourceCycles = [1]; 1947} 1948 1949def HWWriteADC : SchedWriteVariant<[ 1950 SchedVar<HWFastADC0, [HWWriteADC0]>, 1951 SchedVar<NoSchedPred, [WriteADC]> 1952]>; 1953 1954def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8, 1955 SBB16ri8, SBB32ri8, SBB64ri8)>; 1956 1957// CMOVs that use both Z and C flag require an extra uop. 1958def HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> { 1959 let Latency = 3; 1960 let ResourceCycles = [1,2]; 1961 let NumMicroOps = 3; 1962} 1963 1964def HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> { 1965 let Latency = 8; 1966 let ResourceCycles = [1,1,2]; 1967 let NumMicroOps = 4; 1968} 1969 1970def HWCMOVA_CMOVBErr : SchedWriteVariant<[ 1971 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>, 1972 SchedVar<NoSchedPred, [WriteCMOV]> 1973]>; 1974 1975def HWCMOVA_CMOVBErm : SchedWriteVariant<[ 1976 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>, 1977 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1978]>; 1979 1980def : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1981def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1982 1983// SETCCs that use both Z and C flag require an extra uop. 1984def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> { 1985 let Latency = 2; 1986 let ResourceCycles = [1,1]; 1987 let NumMicroOps = 2; 1988} 1989 1990def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { 1991 let Latency = 3; 1992 let ResourceCycles = [1,1,1,1]; 1993 let NumMicroOps = 4; 1994} 1995 1996def HWSETA_SETBErr : SchedWriteVariant<[ 1997 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>, 1998 SchedVar<NoSchedPred, [WriteSETCC]> 1999]>; 2000 2001def HWSETA_SETBErm : SchedWriteVariant<[ 2002 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>, 2003 SchedVar<NoSchedPred, [WriteSETCCStore]> 2004]>; 2005 2006def : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>; 2007def : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>; 2008 2009} // SchedModel 2010