1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as Intel-style
11 // assembly.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "X86IntelInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86MCTargetDesc.h"
18 #include "X86InstComments.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include <cctype>
25 using namespace llvm;
26
27 #define DEBUG_TYPE "asm-printer"
28
29 #include "X86GenAsmWriter1.inc"
30
printRegName(raw_ostream & OS,unsigned RegNo) const31 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
32 OS << getRegisterName(RegNo);
33 }
34
printInst(const MCInst * MI,raw_ostream & OS,StringRef Annot)35 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
36 StringRef Annot) {
37 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
38 uint64_t TSFlags = Desc.TSFlags;
39
40 if (TSFlags & X86II::LOCK)
41 OS << "\tlock\n";
42
43 printInstruction(MI, OS);
44
45 // Next always print the annotation.
46 printAnnotation(OS, Annot);
47
48 // If verbose assembly is enabled, we can print some informative comments.
49 if (CommentStream)
50 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
51 }
52
printSSEAVXCC(int64_t Imm,raw_ostream & O)53 static void printSSEAVXCC(int64_t Imm, raw_ostream &O) {
54 switch (Imm) {
55 default: llvm_unreachable("Invalid avxcc argument!");
56 case 0: O << "eq"; break;
57 case 1: O << "lt"; break;
58 case 2: O << "le"; break;
59 case 3: O << "unord"; break;
60 case 4: O << "neq"; break;
61 case 5: O << "nlt"; break;
62 case 6: O << "nle"; break;
63 case 7: O << "ord"; break;
64 case 8: O << "eq_uq"; break;
65 case 9: O << "nge"; break;
66 case 0xa: O << "ngt"; break;
67 case 0xb: O << "false"; break;
68 case 0xc: O << "neq_oq"; break;
69 case 0xd: O << "ge"; break;
70 case 0xe: O << "gt"; break;
71 case 0xf: O << "true"; break;
72 case 0x10: O << "eq_os"; break;
73 case 0x11: O << "lt_oq"; break;
74 case 0x12: O << "le_oq"; break;
75 case 0x13: O << "unord_s"; break;
76 case 0x14: O << "neq_us"; break;
77 case 0x15: O << "nlt_uq"; break;
78 case 0x16: O << "nle_uq"; break;
79 case 0x17: O << "ord_s"; break;
80 case 0x18: O << "eq_us"; break;
81 case 0x19: O << "nge_uq"; break;
82 case 0x1a: O << "ngt_uq"; break;
83 case 0x1b: O << "false_os"; break;
84 case 0x1c: O << "neq_os"; break;
85 case 0x1d: O << "ge_oq"; break;
86 case 0x1e: O << "gt_oq"; break;
87 case 0x1f: O << "true_us"; break;
88 }
89 }
90
printSSECC(const MCInst * MI,unsigned Op,raw_ostream & O)91 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
92 raw_ostream &O) {
93 int64_t Imm = MI->getOperand(Op).getImm();
94 assert((Imm & 0x7) == Imm); // Ensure valid immediate.
95 printSSEAVXCC(Imm, O);
96 }
97
printAVXCC(const MCInst * MI,unsigned Op,raw_ostream & O)98 void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
99 raw_ostream &O) {
100 int64_t Imm = MI->getOperand(Op).getImm();
101 assert((Imm & 0x1f) == Imm); // Ensure valid immediate.
102 printSSEAVXCC(Imm, O);
103 }
104
printRoundingControl(const MCInst * MI,unsigned Op,raw_ostream & O)105 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
106 raw_ostream &O) {
107 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
108 switch (Imm) {
109 case 0: O << "{rn-sae}"; break;
110 case 1: O << "{rd-sae}"; break;
111 case 2: O << "{ru-sae}"; break;
112 case 3: O << "{rz-sae}"; break;
113 }
114 }
115
116 /// printPCRelImm - This is used to print an immediate value that ends up
117 /// being encoded as a pc-relative value.
printPCRelImm(const MCInst * MI,unsigned OpNo,raw_ostream & O)118 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
119 raw_ostream &O) {
120 const MCOperand &Op = MI->getOperand(OpNo);
121 if (Op.isImm())
122 O << formatImm(Op.getImm());
123 else {
124 assert(Op.isExpr() && "unknown pcrel immediate operand");
125 // If a symbolic branch target was added as a constant expression then print
126 // that address in hex.
127 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
128 int64_t Address;
129 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
130 O << formatHex((uint64_t)Address);
131 }
132 else {
133 // Otherwise, just print the expression.
134 O << *Op.getExpr();
135 }
136 }
137 }
138
printOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)139 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
140 raw_ostream &O) {
141 const MCOperand &Op = MI->getOperand(OpNo);
142 if (Op.isReg()) {
143 printRegName(O, Op.getReg());
144 } else if (Op.isImm()) {
145 O << formatImm((int64_t)Op.getImm());
146 } else {
147 assert(Op.isExpr() && "unknown operand kind in printOperand");
148 O << *Op.getExpr();
149 }
150 }
151
printMemReference(const MCInst * MI,unsigned Op,raw_ostream & O)152 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
153 raw_ostream &O) {
154 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
155 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
156 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
157 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
158 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
159
160 // If this has a segment register, print it.
161 if (SegReg.getReg()) {
162 printOperand(MI, Op+X86::AddrSegmentReg, O);
163 O << ':';
164 }
165
166 O << '[';
167
168 bool NeedPlus = false;
169 if (BaseReg.getReg()) {
170 printOperand(MI, Op+X86::AddrBaseReg, O);
171 NeedPlus = true;
172 }
173
174 if (IndexReg.getReg()) {
175 if (NeedPlus) O << " + ";
176 if (ScaleVal != 1)
177 O << ScaleVal << '*';
178 printOperand(MI, Op+X86::AddrIndexReg, O);
179 NeedPlus = true;
180 }
181
182 if (!DispSpec.isImm()) {
183 if (NeedPlus) O << " + ";
184 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
185 O << *DispSpec.getExpr();
186 } else {
187 int64_t DispVal = DispSpec.getImm();
188 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
189 if (NeedPlus) {
190 if (DispVal > 0)
191 O << " + ";
192 else {
193 O << " - ";
194 DispVal = -DispVal;
195 }
196 }
197 O << formatImm(DispVal);
198 }
199 }
200
201 O << ']';
202 }
203
printSrcIdx(const MCInst * MI,unsigned Op,raw_ostream & O)204 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
205 raw_ostream &O) {
206 const MCOperand &SegReg = MI->getOperand(Op+1);
207
208 // If this has a segment register, print it.
209 if (SegReg.getReg()) {
210 printOperand(MI, Op+1, O);
211 O << ':';
212 }
213 O << '[';
214 printOperand(MI, Op, O);
215 O << ']';
216 }
217
printDstIdx(const MCInst * MI,unsigned Op,raw_ostream & O)218 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
219 raw_ostream &O) {
220 // DI accesses are always ES-based.
221 O << "es:[";
222 printOperand(MI, Op, O);
223 O << ']';
224 }
225
printMemOffset(const MCInst * MI,unsigned Op,raw_ostream & O)226 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
227 raw_ostream &O) {
228 const MCOperand &DispSpec = MI->getOperand(Op);
229 const MCOperand &SegReg = MI->getOperand(Op+1);
230
231 // If this has a segment register, print it.
232 if (SegReg.getReg()) {
233 printOperand(MI, Op+1, O);
234 O << ':';
235 }
236
237 O << '[';
238
239 if (DispSpec.isImm()) {
240 O << formatImm(DispSpec.getImm());
241 } else {
242 assert(DispSpec.isExpr() && "non-immediate displacement?");
243 O << *DispSpec.getExpr();
244 }
245
246 O << ']';
247 }
248