xref: /llvm-project/llvm/lib/Target/X86/X86InstrSystem.td (revision 501a58344179242f702f55e0ee5c039290426c54) 
1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 instructions that are generally used in
10// privileged modes.  These are not typically used by the compiler, but are
11// supported for the assembler and disassembler.
12//
13//===----------------------------------------------------------------------===//
14
15let SchedRW = [WriteSystem] in {
16let Defs = [RAX, RDX] in
17def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let mayLoad = 1, mayStore = 0, hasSideEffects = 1, isTrap = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26
27  def UD1Wm   : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
28                  "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
29  def UD1Lm   : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
30                  "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
31  def UD1Qm   : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
32                   "ud1{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
33
34  def UD1Wr   : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
35                  "ud1{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16;
36  def UD1Lr   : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
37                  "ud1{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32;
38  def UD1Qr   : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
39                   "ud1{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
40}
41
42let isTerminator = 1 in
43  def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
44def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
45
46// Interrupt and SysCall Instructions.
47let Uses = [EFLAGS] in
48  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>, Requires<[Not64BitMode]>;
49
50def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>;
51
52def UBSAN_UD1 : PseudoI<(outs), (ins i32imm:$kind), [(ubsantrap (i32 timm:$kind))]>;
53// The long form of "int $3" turns into int3 as a size optimization.
54// FIXME: This doesn't work because InstAlias can't match immediate constants.
55//def : InstAlias<"int\t$3", (INT3)>;
56
57def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
58              [(int_x86_int timm:$trap)]>;
59
60
61def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
62def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", []>, TB;
63def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
64               Requires<[In64BitMode]>;
65
66def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
67
68def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", []>, TB;
69def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
70                  Requires<[In64BitMode]>;
71
72// FRED Instructions
73let hasSideEffects = 1, Defs = [RSP, EFLAGS] in {
74  def ERETS: I<0x01, MRM_CA, (outs), (ins), "erets",
75              []>, TB, XD, Requires<[In64BitMode]>;
76  def ERETU: I<0x01, MRM_CA, (outs), (ins), "eretu",
77              []>, TB, XS, Requires<[In64BitMode]>;
78} // hasSideEffects = 1, Defs = [RSP, EFLAGS]
79} // SchedRW
80
81def : Pat<(debugtrap),
82          (INT3)>, Requires<[NotPS]>;
83def : Pat<(debugtrap),
84          (INT (i8 0x41))>, Requires<[IsPS]>;
85
86//===----------------------------------------------------------------------===//
87//  Input/Output Instructions.
88//
89let SchedRW = [WriteSystem] in {
90let Defs = [AL], Uses = [DX] in
91def IN8rr  : I<0xEC, RawFrm, (outs), (ins), "in{b}\t{%dx, %al|al, dx}", []>;
92let Defs = [AX], Uses = [DX] in
93def IN16rr : I<0xED, RawFrm, (outs), (ins), "in{w}\t{%dx, %ax|ax, dx}", []>,
94               OpSize16;
95let Defs = [EAX], Uses = [DX] in
96def IN32rr : I<0xED, RawFrm, (outs), (ins), "in{l}\t{%dx, %eax|eax, dx}", []>,
97               OpSize32;
98
99let Defs = [AL] in
100def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
101                 "in{b}\t{$port, %al|al, $port}", []>;
102let Defs = [AX] in
103def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
104                 "in{w}\t{$port, %ax|ax, $port}", []>, OpSize16;
105let Defs = [EAX] in
106def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
107                 "in{l}\t{$port, %eax|eax, $port}", []>, OpSize32;
108
109let Uses = [DX, AL] in
110def OUT8rr  : I<0xEE, RawFrm, (outs), (ins), "out{b}\t{%al, %dx|dx, al}", []>;
111let Uses = [DX, AX] in
112def OUT16rr : I<0xEF, RawFrm, (outs), (ins), "out{w}\t{%ax, %dx|dx, ax}", []>,
113                OpSize16;
114let Uses = [DX, EAX] in
115def OUT32rr : I<0xEF, RawFrm, (outs), (ins), "out{l}\t{%eax, %dx|dx, eax}", []>,
116                OpSize32;
117
118let Uses = [AL] in
119def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
120                   "out{b}\t{%al, $port|$port, al}", []>;
121let Uses = [AX] in
122def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
123                   "out{w}\t{%ax, $port|$port, ax}", []>, OpSize16;
124let Uses = [EAX] in
125def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
126                  "out{l}\t{%eax, $port|$port, eax}", []>, OpSize32;
127
128} // SchedRW
129
130//===----------------------------------------------------------------------===//
131// Moves to and from debug registers
132
133let SchedRW = [WriteSystem] in {
134def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
135                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
136                Requires<[Not64BitMode]>;
137def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
138                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
139                Requires<[In64BitMode]>;
140
141def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
142                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
143                Requires<[Not64BitMode]>;
144def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
145                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
146                Requires<[In64BitMode]>;
147} // SchedRW
148
149//===----------------------------------------------------------------------===//
150// Moves to and from control registers
151
152let SchedRW = [WriteSystem] in {
153def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
154                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
155                Requires<[Not64BitMode]>;
156def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
157                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
158                Requires<[In64BitMode]>;
159
160def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
161                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB,
162                Requires<[Not64BitMode]>;
163def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
164                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB,
165                Requires<[In64BitMode]>;
166} // SchedRW
167
168//===----------------------------------------------------------------------===//
169// Segment override instruction prefixes
170
171let SchedRW = [WriteNop] in {
172def CS_PREFIX : I<0x2E, PrefixByte, (outs), (ins), "cs", []>;
173def SS_PREFIX : I<0x36, PrefixByte, (outs), (ins), "ss", []>;
174def DS_PREFIX : I<0x3E, PrefixByte, (outs), (ins), "ds", []>;
175def ES_PREFIX : I<0x26, PrefixByte, (outs), (ins), "es", []>;
176def FS_PREFIX : I<0x64, PrefixByte, (outs), (ins), "fs", []>;
177def GS_PREFIX : I<0x65, PrefixByte, (outs), (ins), "gs", []>;
178} // SchedRW
179
180//===----------------------------------------------------------------------===//
181// Address-size override prefixes.
182//
183
184let SchedRW = [WriteNop] in {
185def ADDR16_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr16", []>,
186                      Requires<[In32BitMode]>;
187def ADDR32_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr32", []>,
188                      Requires<[In64BitMode]>;
189} // SchedRW
190
191//===----------------------------------------------------------------------===//
192// Moves to and from segment registers.
193//
194
195let SchedRW = [WriteMove] in {
196def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
197                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
198def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
199                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
200def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
201                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
202let mayStore = 1 in {
203def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
204                "mov{w}\t{$src, $dst|$dst, $src}", []>;
205}
206def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
207                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
208def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
209                "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;
210def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
211                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
212let mayLoad = 1 in {
213def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
214                "mov{w}\t{$src, $dst|$dst, $src}", []>;
215}
216} // SchedRW
217
218//===----------------------------------------------------------------------===//
219// Segmentation support instructions.
220
221let SchedRW = [WriteSystem] in {
222def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
223// LKGS instructions
224let hasSideEffects = 1 in {
225  let mayLoad = 1 in
226  def LKGS16m : I<0x00, MRM6m, (outs), (ins i16mem:$src), "lkgs\t$src",
227                  []>, TB, XD, Requires<[In64BitMode]>;
228  def LKGS16r : I<0x00, MRM6r, (outs), (ins GR16:$src), "lkgs\t$src",
229                  []>, TB, XD, Requires<[In64BitMode]>;
230} // hasSideEffects
231
232let Defs = [EFLAGS] in {
233let mayLoad = 1 in
234def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
235                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
236                OpSize16;
237def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
238                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB,
239                OpSize16;
240
241let mayLoad = 1 in
242def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
243                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
244                OpSize32;
245def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
246                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB,
247                OpSize32;
248let mayLoad = 1 in
249def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
250                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
251def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
252                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
253
254let mayLoad = 1 in
255def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
256                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
257                OpSize16;
258def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16orGR32orGR64:$src),
259                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB,
260                OpSize16;
261let mayLoad = 1 in
262def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
263                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
264                OpSize32;
265def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR16orGR32orGR64:$src),
266                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB,
267                OpSize32;
268let mayLoad = 1 in
269def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
270                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
271def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR16orGR32orGR64:$src),
272                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
273}
274
275def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
276
277def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
278               "str{w}\t$dst", []>, TB, OpSize16;
279def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
280               "str{l}\t$dst", []>, TB, OpSize32;
281def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
282                "str{q}\t$dst", []>, TB;
283let mayStore = 1 in
284def STRm   : I<0x00, MRM1m, (outs), (ins i16mem:$dst), "str{w}\t$dst", []>, TB;
285
286def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src), "ltr{w}\t$src", []>, TB;
287let mayLoad = 1 in
288def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t$src", []>, TB;
289
290def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), "push{w}\t{%cs|cs}", []>,
291                 OpSize16, Requires<[Not64BitMode]>;
292def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), "push{l}\t{%cs|cs}", []>,
293                 OpSize32, Requires<[Not64BitMode]>;
294def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), "push{w}\t{%ss|ss}", []>,
295                 OpSize16, Requires<[Not64BitMode]>;
296def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), "push{l}\t{%ss|ss}", []>,
297                 OpSize32, Requires<[Not64BitMode]>;
298def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), "push{w}\t{%ds|ds}", []>,
299                 OpSize16, Requires<[Not64BitMode]>;
300def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), "push{l}\t{%ds|ds}", []>,
301                 OpSize32, Requires<[Not64BitMode]>;
302def PUSHES16 : I<0x06, RawFrm, (outs), (ins), "push{w}\t{%es|es}", []>,
303                 OpSize16, Requires<[Not64BitMode]>;
304def PUSHES32 : I<0x06, RawFrm, (outs), (ins), "push{l}\t{%es|es}", []>,
305                 OpSize32, Requires<[Not64BitMode]>;
306def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t{%fs|fs}", []>,
307                 OpSize16, TB;
308def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), "push{l}\t{%fs|fs}", []>, TB,
309                 OpSize32, Requires<[Not64BitMode]>;
310def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t{%gs|gs}", []>,
311                 OpSize16, TB;
312def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), "push{l}\t{%gs|gs}", []>, TB,
313                 OpSize32, Requires<[Not64BitMode]>;
314def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins), "push{q}\t{%fs|fs}", []>, TB,
315                 OpSize32, Requires<[In64BitMode]>;
316def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins), "push{q}\t{%gs|gs}", []>, TB,
317                 OpSize32, Requires<[In64BitMode]>;
318
319// No "pop cs" instruction.
320def POPSS16 : I<0x17, RawFrm, (outs), (ins), "pop{w}\t{%ss|ss}", []>,
321              OpSize16, Requires<[Not64BitMode]>;
322def POPSS32 : I<0x17, RawFrm, (outs), (ins), "pop{l}\t{%ss|ss}", []>,
323              OpSize32, Requires<[Not64BitMode]>;
324
325def POPDS16 : I<0x1F, RawFrm, (outs), (ins), "pop{w}\t{%ds|ds}", []>,
326              OpSize16, Requires<[Not64BitMode]>;
327def POPDS32 : I<0x1F, RawFrm, (outs), (ins), "pop{l}\t{%ds|ds}", []>,
328              OpSize32, Requires<[Not64BitMode]>;
329
330def POPES16 : I<0x07, RawFrm, (outs), (ins), "pop{w}\t{%es|es}", []>,
331              OpSize16, Requires<[Not64BitMode]>;
332def POPES32 : I<0x07, RawFrm, (outs), (ins), "pop{l}\t{%es|es}", []>,
333              OpSize32, Requires<[Not64BitMode]>;
334
335def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t{%fs|fs}", []>,
336                OpSize16, TB;
337def POPFS32 : I<0xa1, RawFrm, (outs), (ins), "pop{l}\t{%fs|fs}", []>, TB,
338                OpSize32, Requires<[Not64BitMode]>;
339def POPFS64 : I<0xa1, RawFrm, (outs), (ins), "pop{q}\t{%fs|fs}", []>, TB,
340                OpSize32, Requires<[In64BitMode]>;
341
342def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t{%gs|gs}", []>,
343                OpSize16, TB;
344def POPGS32 : I<0xa9, RawFrm, (outs), (ins), "pop{l}\t{%gs|gs}", []>, TB,
345                OpSize32, Requires<[Not64BitMode]>;
346def POPGS64 : I<0xa9, RawFrm, (outs), (ins), "pop{q}\t{%gs|gs}", []>, TB,
347                OpSize32, Requires<[In64BitMode]>;
348
349def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
350                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
351                Requires<[Not64BitMode]>;
352def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
353                "lds{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
354                Requires<[Not64BitMode]>;
355
356def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
357                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
358def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
359                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
360def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
361                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
362
363def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
364                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize16,
365                Requires<[Not64BitMode]>;
366def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
367                "les{l}\t{$src, $dst|$dst, $src}", []>, OpSize32,
368                Requires<[Not64BitMode]>;
369
370def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
371                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
372def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
373                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
374def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
375                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
376
377def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaquemem:$src),
378                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16;
379def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaquemem:$src),
380                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32;
381
382def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaquemem:$src),
383                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
384
385let Defs = [EFLAGS] in {
386def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg), "verr\t$seg", []>, TB;
387def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB;
388let mayLoad = 1 in {
389def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg), "verr\t$seg", []>, TB;
390def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg), "verw\t$seg", []>, TB;
391}
392} // Defs EFLAGS
393} // SchedRW
394
395//===----------------------------------------------------------------------===//
396// Descriptor-table support instructions
397
398let SchedRW = [WriteSystem] in {
399def SGDT16m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
400                "sgdtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
401def SGDT32m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
402                "sgdt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
403def SGDT64m : I<0x01, MRM0m, (outs), (ins opaquemem:$dst),
404                "sgdt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
405def SIDT16m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
406                "sidtw\t$dst", []>, TB, OpSize16, Requires<[Not64BitMode]>;
407def SIDT32m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
408                "sidt{l|d}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
409def SIDT64m : I<0x01, MRM1m, (outs), (ins opaquemem:$dst),
410                "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
411def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
412                "sldt{w}\t$dst", []>, TB, OpSize16;
413let mayStore = 1 in
414def SLDT16m : I<0x00, MRM0m, (outs), (ins i16mem:$dst),
415                "sldt{w}\t$dst", []>, TB;
416def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
417                "sldt{l}\t$dst", []>, OpSize32, TB;
418
419// LLDT is not interpreted specially in 64-bit mode because there is no sign
420//   extension.
421def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
422                 "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
423
424def LGDT16m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
425                "lgdtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
426def LGDT32m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
427                "lgdt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
428def LGDT64m : I<0x01, MRM2m, (outs), (ins opaquemem:$src),
429                "lgdt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
430def LIDT16m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
431                "lidtw\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;
432def LIDT32m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
433                "lidt{l|d}\t$src", []>, OpSize32, TB, Requires<[Not64BitMode]>;
434def LIDT64m : I<0x01, MRM3m, (outs), (ins opaquemem:$src),
435                "lidt{q}\t$src", []>, TB, Requires<[In64BitMode]>;
436def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
437                "lldt{w}\t$src", []>, TB;
438let mayLoad = 1 in
439def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
440                "lldt{w}\t$src", []>, TB;
441} // SchedRW
442
443//===----------------------------------------------------------------------===//
444// Specialized register support
445let SchedRW = [WriteSystem] in {
446let Uses = [EAX, ECX, EDX] in
447def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
448let Uses = [EAX, ECX, EDX] in
449def WRMSRNS : I<0x01, MRM_C6, (outs), (ins), "wrmsrns", []>, TB;
450let Defs = [EAX, EDX], Uses = [ECX] in
451def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
452let Defs = [RAX, EFLAGS], Uses = [RBX, RCX], Predicates = [In64BitMode] in
453def PBNDKB : I<0x01, MRM_C7, (outs), (ins), "pbndkb", []>, TB;
454let Uses = [RSI, RDI, RCX], Predicates = [In64BitMode] in {
455def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
456def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
457}
458
459multiclass Urdwrmsr<Map rrmap, string suffix> {
460  let mayLoad = 1 in {
461    let OpMap = rrmap in
462    def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
463                            "urdmsr\t{$src, $dst|$dst, $src}",
464                            [(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
465    def URDMSRri#suffix  : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
466                                "urdmsr\t{$imm, $dst|$dst, $imm}",
467                                [(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
468                           T_MAP7, VEX, XD, NoCD8;
469    def RDMSRri#suffix  : Ii32<0xf6, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
470                                "rdmsr\t{$imm, $dst|$dst, $imm}", []>,
471                           T_MAP7, VEX, XD, NoCD8;
472  }
473  let mayStore = 1 in {
474    let OpMap = rrmap in
475    def UWRMSRrr#suffix  : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
476                             "uwrmsr\t{$src2, $src1|$src1, $src2}",
477                             [(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
478    def UWRMSRir#suffix  : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
479                                "uwrmsr\t{$src, $imm|$imm, $src}",
480                                [(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
481                           T_MAP7, VEX, XS, NoCD8;
482    def WRMSRNSir#suffix  : Ii32<0xf6, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
483                                "wrmsrns\t{$src, $imm|$imm, $src}",
484                                []>, T_MAP7, VEX, XS, NoCD8;
485  }
486}
487
488let Predicates = [HasUSERMSR, NoEGPR] in
489  defm "" : Urdwrmsr<T8, "">;
490
491let Predicates = [HasUSERMSR, HasEGPR, In64BitMode] in
492  defm "" : Urdwrmsr<T_MAP4, "_EVEX">, EVEX;
493
494let Defs = [RAX, RDX], Uses = [ECX] in
495def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
496
497def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
498                "smsw{w}\t$dst", []>, OpSize16, TB;
499def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
500                "smsw{l}\t$dst", []>, OpSize32, TB;
501// no m form encodable; use SMSW16m
502def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
503                 "smsw{q}\t$dst", []>, TB;
504
505// For memory operands, there is only a 16-bit form
506def SMSW16m : I<0x01, MRM4m, (outs), (ins i16mem:$dst),
507                "smsw{w}\t$dst", []>, TB;
508
509def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
510                "lmsw{w}\t$src", []>, TB;
511let mayLoad = 1 in
512def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
513                "lmsw{w}\t$src", []>, TB;
514
515let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
516  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
517} // SchedRW
518
519//===----------------------------------------------------------------------===//
520// Cache instructions
521let SchedRW = [WriteSystem] in {
522def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
523def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [(int_x86_wbinvd)]>, TB, PS;
524
525// wbnoinvd is like wbinvd, except without invalidation
526// encoding: like wbinvd + an 0xF3 prefix
527def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
528                 [(int_x86_wbnoinvd)]>, TB, XS,
529                 Requires<[HasWBNOINVD]>;
530} // SchedRW
531
532//===----------------------------------------------------------------------===//
533// CET instructions
534// Use with caution, availability is not predicated on features.
535let SchedRW = [WriteSystem] in {
536  let Uses = [SSP] in {
537    let Defs = [SSP] in {
538      def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
539                       [(int_x86_incsspd GR32:$src)]>, TB, XS;
540      def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
541                       [(int_x86_incsspq GR64:$src)]>, TB, XS;
542    } // Defs SSP
543
544    let Constraints = "$src = $dst" in {
545      def RDSSPD : I<0x1E, MRM1r, (outs GR32:$dst), (ins GR32:$src),
546                     "rdsspd\t$dst",
547                     [(set GR32:$dst, (int_x86_rdsspd GR32:$src))]>, TB, XS;
548      def RDSSPQ : RI<0x1E, MRM1r, (outs GR64:$dst), (ins GR64:$src),
549                     "rdsspq\t$dst",
550                     [(set GR64:$dst, (int_x86_rdsspq GR64:$src))]>, TB, XS;
551    }
552
553    let Defs = [SSP] in {
554      def SAVEPREVSSP : I<0x01, MRM_EA, (outs), (ins), "saveprevssp",
555                       [(int_x86_saveprevssp)]>, TB, XS;
556      def RSTORSSP : I<0x01, MRM5m, (outs), (ins i32mem:$src),
557                       "rstorssp\t$src",
558                       [(int_x86_rstorssp addr:$src)]>, TB, XS;
559    } // Defs SSP
560  } // Uses SSP
561
562let Predicates = [NoEGPR] in {
563  def WRSSD : I<0xF6, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
564                "wrssd\t{$src, $dst|$dst, $src}",
565                [(int_x86_wrssd GR32:$src, addr:$dst)]>, T8;
566  def WRSSQ : RI<0xF6, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
567                 "wrssq\t{$src, $dst|$dst, $src}",
568                 [(int_x86_wrssq GR64:$src, addr:$dst)]>, T8;
569  def WRUSSD : I<0xF5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
570                 "wrussd\t{$src, $dst|$dst, $src}",
571                 [(int_x86_wrussd GR32:$src, addr:$dst)]>, T8, PD;
572  def WRUSSQ : RI<0xF5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
573                  "wrussq\t{$src, $dst|$dst, $src}",
574                  [(int_x86_wrussq GR64:$src, addr:$dst)]>, T8, PD;
575}
576
577let Predicates = [HasEGPR, In64BitMode] in {
578  def WRSSD_EVEX : I<0x66, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
579                     "wrssd\t{$src, $dst|$dst, $src}",
580                     [(int_x86_wrssd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4;
581  def WRSSQ_EVEX : RI<0x66, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
582                      "wrssq\t{$src, $dst|$dst, $src}",
583                      [(int_x86_wrssq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4;
584  def WRUSSD_EVEX : I<0x65, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
585                      "wrussd\t{$src, $dst|$dst, $src}",
586                      [(int_x86_wrussd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD;
587  def WRUSSQ_EVEX : RI<0x65, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
588                       "wrussq\t{$src, $dst|$dst, $src}",
589                       [(int_x86_wrussq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD;
590}
591
592  let Defs = [SSP] in {
593    let Uses = [SSP] in {
594        def SETSSBSY : I<0x01, MRM_E8, (outs), (ins), "setssbsy",
595                         [(int_x86_setssbsy)]>, TB, XS;
596    } // Uses SSP
597
598    def CLRSSBSY : I<0xAE, MRM6m, (outs), (ins i32mem:$src),
599                     "clrssbsy\t$src",
600                     [(int_x86_clrssbsy addr:$src)]>, TB, XS;
601  } // Defs SSP
602} // SchedRW
603
604let SchedRW = [WriteSystem] in {
605    def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, TB, XS;
606    def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, TB, XS;
607} // SchedRW
608
609//===----------------------------------------------------------------------===//
610// XSAVE instructions
611let SchedRW = [WriteSystem] in {
612// NOTE: No HasXSAVE predicate so that these can be used with _xgetbv/_xsetbv
613// on Windows without needing to enable the xsave feature to be compatible with
614// MSVC.
615let Defs = [EDX, EAX], Uses = [ECX] in
616def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
617
618let Uses = [EDX, EAX, ECX] in
619def XSETBV : I<0x01, MRM_D1, (outs), (ins),
620              "xsetbv",
621              [(int_x86_xsetbv ECX, EDX, EAX)]>, TB;
622
623
624let Uses = [EDX, EAX] in {
625def XSAVE : I<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
626              "xsave\t$dst",
627              [(int_x86_xsave addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE]>;
628def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaquemem:$dst),
629                 "xsave64\t$dst",
630                 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
631def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
632               "xrstor\t$dst",
633               [(int_x86_xrstor addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE]>;
634def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaquemem:$dst),
635                  "xrstor64\t$dst",
636                  [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
637def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
638                 "xsaveopt\t$dst",
639                 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEOPT]>;
640def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaquemem:$dst),
641                    "xsaveopt64\t$dst",
642                    [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEOPT, In64BitMode]>;
643def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
644               "xsavec\t$dst",
645               [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC]>;
646def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaquemem:$dst),
647                 "xsavec64\t$dst",
648                 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVEC, In64BitMode]>;
649def XSAVES : I<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
650               "xsaves\t$dst",
651               [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
652def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaquemem:$dst),
653                  "xsaves64\t$dst",
654                  [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVE, In64BitMode]>;
655def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
656                "xrstors\t$dst",
657                [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES]>;
658def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaquemem:$dst),
659                   "xrstors64\t$dst",
660                   [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[HasXSAVES, In64BitMode]>;
661} // Uses
662} // SchedRW
663
664//===----------------------------------------------------------------------===//
665// VIA PadLock crypto instructions
666let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
667  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
668
669def : InstAlias<"xstorerng", (XSTORE)>;
670
671let SchedRW = [WriteSystem] in {
672let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
673  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB, REP;
674  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB, REP;
675  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB, REP;
676  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB, REP;
677  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB, REP;
678}
679
680let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
681  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB, REP;
682  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB, REP;
683}
684let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
685  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB, REP;
686} // SchedRW
687
688//==-----------------------------------------------------------------------===//
689// PKU  - enable protection key
690let SchedRW = [WriteSystem] in {
691let Defs = [EAX, EDX], Uses = [ECX] in
692  def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru",
693                  [(set EAX, EDX, (X86rdpkru ECX))]>, TB;
694let Uses = [EAX, ECX, EDX] in
695  def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru",
696                  [(X86wrpkru EAX, EDX, ECX)]>, TB;
697} // SchedRW
698
699//===----------------------------------------------------------------------===//
700// FS/GS Base Instructions
701let Predicates = [HasFSGSBase, In64BitMode], SchedRW = [WriteSystem] in {
702  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
703                   "rdfsbase{l}\t$dst",
704                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
705  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
706                     "rdfsbase{q}\t$dst",
707                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
708  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
709                   "rdgsbase{l}\t$dst",
710                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
711  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
712                     "rdgsbase{q}\t$dst",
713                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
714  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
715                   "wrfsbase{l}\t$src",
716                   [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
717  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
718                      "wrfsbase{q}\t$src",
719                      [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
720  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
721                   "wrgsbase{l}\t$src",
722                   [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
723  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
724                      "wrgsbase{q}\t$src",
725                      [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
726}
727
728//===----------------------------------------------------------------------===//
729// INVPCID Instruction
730let SchedRW = [WriteSystem] in {
731def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
732                  "invpcid\t{$src2, $src1|$src1, $src2}",
733                  [(int_x86_invpcid GR32:$src1, addr:$src2)]>, T8, PD,
734                  Requires<[Not64BitMode, HasINVPCID]>;
735def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
736                  "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
737                  Requires<[In64BitMode]>;
738
739def INVPCID64_EVEX : I<0xF2, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
740                       "invpcid\t{$src2, $src1|$src1, $src2}", []>,
741                     EVEX, NoCD8, T_MAP4, XS, WIG, Requires<[In64BitMode]>;
742} // SchedRW
743
744let Predicates = [HasINVPCID, NoEGPR] in {
745  // The instruction can only use a 64 bit register as the register argument
746  // in 64 bit mode, while the intrinsic only accepts a 32 bit argument
747  // corresponding to it.
748  // The accepted values for now are 0,1,2,3 anyways (see Intel SDM -- INVCPID
749  // type),/ so it doesn't hurt us that one can't supply a 64 bit value here.
750  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
751            (INVPCID64
752              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
753              addr:$src2)>;
754}
755
756let Predicates = [HasINVPCID, HasEGPR] in {
757  def : Pat<(int_x86_invpcid GR32:$src1, addr:$src2),
758            (INVPCID64_EVEX
759              (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src1), sub_32bit),
760              addr:$src2)>;
761}
762
763
764//===----------------------------------------------------------------------===//
765// SMAP Instruction
766let Defs = [EFLAGS], SchedRW = [WriteSystem] in {
767  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
768  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
769}
770
771//===----------------------------------------------------------------------===//
772// SMX Instruction
773let SchedRW = [WriteSystem] in {
774let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
775  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
776} // Uses, Defs
777} // SchedRW
778
779//===----------------------------------------------------------------------===//
780// TS flag control instruction.
781let SchedRW = [WriteSystem] in {
782def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
783}
784
785//===----------------------------------------------------------------------===//
786// IF (inside EFLAGS) management instructions.
787let SchedRW = [WriteSystem], Uses = [EFLAGS], Defs = [EFLAGS] in {
788def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
789def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
790}
791
792//===----------------------------------------------------------------------===//
793// RDPID Instruction
794let SchedRW = [WriteSystem] in {
795def RDPID32 : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
796                "rdpid\t$dst", [(set GR32:$dst, (int_x86_rdpid))]>, TB, XS,
797                Requires<[Not64BitMode, HasRDPID]>;
798def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, TB, XS,
799                Requires<[In64BitMode, HasRDPID]>;
800} // SchedRW
801
802let Predicates = [In64BitMode, HasRDPID] in {
803  // Due to silly instruction definition, we have to compensate for the
804  // instruction outputing a 64-bit register.
805  def : Pat<(int_x86_rdpid),
806            (EXTRACT_SUBREG (RDPID64), sub_32bit)>;
807}
808
809
810//===----------------------------------------------------------------------===//
811// PTWRITE Instruction - Write Data to a Processor Trace Packet
812let SchedRW = [WriteSystem] in {
813def PTWRITEm: I<0xAE, MRM4m, (outs), (ins i32mem:$dst),
814                "ptwrite{l}\t$dst", [(int_x86_ptwrite32 (loadi32 addr:$dst))]>, TB, XS,
815                Requires<[HasPTWRITE]>;
816def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
817                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 (loadi64 addr:$dst))]>, TB, XS,
818                    Requires<[In64BitMode, HasPTWRITE]>;
819
820def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
821                 "ptwrite{l}\t$dst", [(int_x86_ptwrite32 GR32:$dst)]>, TB, XS,
822                    Requires<[HasPTWRITE]>;
823def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
824                    "ptwrite{q}\t$dst", [(int_x86_ptwrite64 GR64:$dst)]>, TB, XS,
825                    Requires<[In64BitMode, HasPTWRITE]>;
826} // SchedRW
827
828//===----------------------------------------------------------------------===//
829// RDPRU - Read Processor Register instruction.
830
831let SchedRW = [WriteSystem] in {
832let Uses = [ECX], Defs = [EAX, EDX] in
833   def RDPRU : I<0x01, MRM_FD, (outs), (ins), "rdpru", []>, TB,
834               Requires<[HasRDPRU]>;
835}
836
837//===----------------------------------------------------------------------===//
838// Platform Configuration instruction
839
840// From ISA docs:
841//  "This instruction is used to execute functions for configuring platform
842//   features.
843//   EAX: Leaf function to be invoked.
844//   RBX/RCX/RDX: Leaf-specific purpose."
845//  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
846//   AF, OF, and SF are cleared. In case of failure, the failure reason is
847//   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
848// Thus all these mentioned registers are considered clobbered.
849
850let SchedRW = [WriteSystem] in {
851let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
852    def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
853                  Requires<[HasPCONFIG]>;
854} // SchedRW
855